drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/omap-dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/pinctrl/consumer.h>
  42
  43 #include <linux/spi/spi.h>
  44
  45 #include <linux/platform_data/spi-omap2-mcspi.h>
  46
  47 #define OMAP2_MCSPI_MAX_FREQ            48000000
  48 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  49
  50 #define OMAP2_MCSPI_REVISION            0x00
  51 #define OMAP2_MCSPI_SYSSTATUS           0x14
  52 #define OMAP2_MCSPI_IRQSTATUS           0x18
  53 #define OMAP2_MCSPI_IRQENABLE           0x1c
  54 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  55 #define OMAP2_MCSPI_SYST                0x24
  56 #define OMAP2_MCSPI_MODULCTRL           0x28
  57
  58 /* per-channel banks, 0x14 bytes each, first is: */
  59 #define OMAP2_MCSPI_CHCONF0             0x2c
  60 #define OMAP2_MCSPI_CHSTAT0             0x30
  61 #define OMAP2_MCSPI_CHCTRL0             0x34
  62 #define OMAP2_MCSPI_TX0                 0x38
  63 #define OMAP2_MCSPI_RX0                 0x3c
  64
  65 /* per-register bitmasks: */
  66
  67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  70
  71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  86
  87 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  88 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  89 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  90
  91 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  92
  93 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  94
  95 /* We have 2 DMA channels per CS, one for RX and one for TX */
  96 struct omap2_mcspi_dma {
  97         struct dma_chan *dma_tx;
  98         struct dma_chan *dma_rx;
  99
 100         int dma_tx_sync_dev;
 101         int dma_rx_sync_dev;
 102
 103         struct completion dma_tx_completion;
 104         struct completion dma_rx_completion;
 105 };
 106
 107 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 108  * cache operations; better heuristics consider wordsize and bitrate.
 109  */
 110 #define DMA_MIN_BYTES                   160
 111
 112
 113 /*
 114  * Used for context save and restore, structure members to be updated whenever
 115  * corresponding registers are modified.
 116  */
 117 struct omap2_mcspi_regs {
 118         u32 modulctrl;
 119         u32 wakeupenable;
 120         struct list_head cs;
 121 };
 122
 123 struct omap2_mcspi {
 124         struct spi_master       *master;
 125         /* Virtual base address of the controller */
 126         void __iomem            *base;
 127         unsigned long           phys;
 128         /* SPI1 has 4 channels, while SPI2 has 2 */
 129         struct omap2_mcspi_dma  *dma_channels;
 130         struct device           *dev;
 131         struct omap2_mcspi_regs ctx;
 132         unsigned int            pin_dir:1;
 133 };
 134
 135 struct omap2_mcspi_cs {
 136         void __iomem            *base;
 137         unsigned long           phys;
 138         int                     word_len;
 139         u16                     mode;
 140         struct list_head        node;
 141         /* Context save and restore shadow register */
 142         u32                     chconf0;
 143 };
 144
 145 static inline void mcspi_write_reg(struct spi_master *master,
 146                 int idx, u32 val)
 147 {
 148         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 149
 150         __raw_writel(val, mcspi->base + idx);
 151 }
 152
 153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156
 157         return __raw_readl(mcspi->base + idx);
 158 }
 159
 160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 161                 int idx, u32 val)
 162 {
 163         struct omap2_mcspi_cs   *cs = spi->controller_state;
 164
 165         __raw_writel(val, cs->base +  idx);
 166 }
 167
 168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171
 172         return __raw_readl(cs->base + idx);
 173 }
 174
 175 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 176 {
 177         struct omap2_mcspi_cs *cs = spi->controller_state;
 178
 179         return cs->chconf0;
 180 }
 181
 182 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 183 {
 184         struct omap2_mcspi_cs *cs = spi->controller_state;
 185
 186         cs->chconf0 = val;
 187         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 188         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 189 }
 190
 191 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 192                 int is_read, int enable)
 193 {
 194         u32 l, rw;
 195
 196         l = mcspi_cached_chconf0(spi);
 197
 198         if (is_read) /* 1 is read, 0 write */
 199                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 200         else
 201                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 202
 203         if (enable)
 204                 l |= rw;
 205         else
 206                 l &= ~rw;
 207
 208         mcspi_write_chconf0(spi, l);
 209 }
 210
 211 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 212 {
 213         u32 l;
 214
 215         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 216         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 217         /* Flash post-writes */
 218         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 219 }
 220
 221 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 222 {
 223         u32 l;
 224
 225         l = mcspi_cached_chconf0(spi);
 226         if (cs_active)
 227                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 228         else
 229                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 230
 231         mcspi_write_chconf0(spi, l);
 232 }
 233
 234 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 235 {
 236         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 237         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 238         u32 l;
 239
 240         /*
 241          * Setup when switching from (reset default) slave mode
 242          * to single-channel master mode
 243          */
 244         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 245         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 246         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 247         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 248
 249         ctx->modulctrl = l;
 250 }
 251
 252 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 253 {
 254         struct spi_master       *spi_cntrl = mcspi->master;
 255         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 256         struct omap2_mcspi_cs   *cs;
 257
 258         /* McSPI: context restore */
 259         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 260         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 261
 262         list_for_each_entry(cs, &ctx->cs, node)
 263                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 264 }
 265
 266 static int omap2_prepare_transfer(struct spi_master *master)
 267 {
 268         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 269
 270         pm_runtime_get_sync(mcspi->dev);
 271         return 0;
 272 }
 273
 274 static int omap2_unprepare_transfer(struct spi_master *master)
 275 {
 276         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 277
 278         pm_runtime_mark_last_busy(mcspi->dev);
 279         pm_runtime_put_autosuspend(mcspi->dev);
 280         return 0;
 281 }
 282
 283 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 284 {
 285         unsigned long timeout;
 286
 287         timeout = jiffies + msecs_to_jiffies(1000);
 288         while (!(__raw_readl(reg) & bit)) {
 289                 if (time_after(jiffies, timeout)) {
 290                         if (!(__raw_readl(reg) & bit))
 291                                 return -ETIMEDOUT;
 292                         else
 293                                 return 0;
 294                 }
 295                 cpu_relax();
 296         }
 297         return 0;
 298 }
 299
 300 static void omap2_mcspi_rx_callback(void *data)
 301 {
 302         struct spi_device *spi = data;
 303         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 304         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 305
 306         /* We must disable the DMA RX request */
 307         omap2_mcspi_set_dma_req(spi, 1, 0);
 308
 309         complete(&mcspi_dma->dma_rx_completion);
 310 }
 311
 312 static void omap2_mcspi_tx_callback(void *data)
 313 {
 314         struct spi_device *spi = data;
 315         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 316         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 317
 318         /* We must disable the DMA TX request */
 319         omap2_mcspi_set_dma_req(spi, 0, 0);
 320
 321         complete(&mcspi_dma->dma_tx_completion);
 322 }
 323
 324 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 325                                 struct spi_transfer *xfer,
 326                                 struct dma_slave_config cfg)
 327 {
 328         struct omap2_mcspi      *mcspi;
 329         struct omap2_mcspi_dma  *mcspi_dma;
 330         unsigned int            count;
 331
 332         mcspi = spi_master_get_devdata(spi->master);
 333         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 334         count = xfer->len;
 335
 336         if (mcspi_dma->dma_tx) {
 337                 struct dma_async_tx_descriptor *tx;
 338                 struct scatterlist sg;
 339
 340                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 341
 342                 sg_init_table(&sg, 1);
 343                 sg_dma_address(&sg) = xfer->tx_dma;
 344                 sg_dma_len(&sg) = xfer->len;
 345
 346                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 347                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 348                 if (tx) {
 349                         tx->callback = omap2_mcspi_tx_callback;
 350                         tx->callback_param = spi;
 351                         dmaengine_submit(tx);
 352                 } else {
 353                         /* FIXME: fall back to PIO? */
 354                 }
 355         }
 356         dma_async_issue_pending(mcspi_dma->dma_tx);
 357         omap2_mcspi_set_dma_req(spi, 0, 1);
 358
 359 }
 360
 361 static unsigned
 362 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 363                                 struct dma_slave_config cfg,
 364                                 unsigned es)
 365 {
 366         struct omap2_mcspi      *mcspi;
 367         struct omap2_mcspi_dma  *mcspi_dma;
 368         unsigned int            count;
 369         u32                     l;
 370         int                     elements = 0;
 371         int                     word_len, element_count;
 372         struct omap2_mcspi_cs   *cs = spi->controller_state;
 373         mcspi = spi_master_get_devdata(spi->master);
 374         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 375         count = xfer->len;
 376         word_len = cs->word_len;
 377         l = mcspi_cached_chconf0(spi);
 378
 379         if (word_len <= 8)
 380                 element_count = count;
 381         else if (word_len <= 16)
 382                 element_count = count >> 1;
 383         else /* word_len <= 32 */
 384                 element_count = count >> 2;
 385
 386         if (mcspi_dma->dma_rx) {
 387                 struct dma_async_tx_descriptor *tx;
 388                 struct scatterlist sg;
 389                 size_t len = xfer->len - es;
 390
 391                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 392
 393                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
 394                         len -= es;
 395
 396                 sg_init_table(&sg, 1);
 397                 sg_dma_address(&sg) = xfer->rx_dma;
 398                 sg_dma_len(&sg) = len;
 399
 400                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 401                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 402                                 DMA_CTRL_ACK);
 403                 if (tx) {
 404                         tx->callback = omap2_mcspi_rx_callback;
 405                         tx->callback_param = spi;
 406                         dmaengine_submit(tx);
 407                 } else {
 408                                 /* FIXME: fall back to PIO? */
 409                 }
 410         }
 411
 412         dma_async_issue_pending(mcspi_dma->dma_rx);
 413         omap2_mcspi_set_dma_req(spi, 1, 1);
 414
 415         wait_for_completion(&mcspi_dma->dma_rx_completion);
 416         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 417                          DMA_FROM_DEVICE);
 418         omap2_mcspi_set_enable(spi, 0);
 419
 420         elements = element_count - 1;
 421
 422         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 423                 elements--;
 424
 425                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 426                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 427                         u32 w;
 428
 429                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 430                         if (word_len <= 8)
 431                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 432                         else if (word_len <= 16)
 433                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 434                         else /* word_len <= 32 */
 435                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 436                 } else {
 437                         dev_err(&spi->dev, "DMA RX penultimate word empty");
 438                         count -= (word_len <= 8)  ? 2 :
 439                                 (word_len <= 16) ? 4 :
 440                                 /* word_len <= 32 */ 8;
 441                         omap2_mcspi_set_enable(spi, 1);
 442                         return count;
 443                 }
 444         }
 445         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 446                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 447                 u32 w;
 448
 449                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 450                 if (word_len <= 8)
 451                         ((u8 *)xfer->rx_buf)[elements] = w;
 452                 else if (word_len <= 16)
 453                         ((u16 *)xfer->rx_buf)[elements] = w;
 454                 else /* word_len <= 32 */
 455                         ((u32 *)xfer->rx_buf)[elements] = w;
 456         } else {
 457                 dev_err(&spi->dev, "DMA RX last word empty");
 458                 count -= (word_len <= 8)  ? 1 :
 459                          (word_len <= 16) ? 2 :
 460                        /* word_len <= 32 */ 4;
 461         }
 462         omap2_mcspi_set_enable(spi, 1);
 463         return count;
 464 }
 465
 466 static unsigned
 467 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 468 {
 469         struct omap2_mcspi      *mcspi;
 470         struct omap2_mcspi_cs   *cs = spi->controller_state;
 471         struct omap2_mcspi_dma  *mcspi_dma;
 472         unsigned int            count;
 473         u32                     l;
 474         u8                      *rx;
 475         const u8                *tx;
 476         struct dma_slave_config cfg;
 477         enum dma_slave_buswidth width;
 478         unsigned es;
 479         void __iomem            *chstat_reg;
 480
 481         mcspi = spi_master_get_devdata(spi->master);
 482         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 483         l = mcspi_cached_chconf0(spi);
 484
 485
 486         if (cs->word_len <= 8) {
 487                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 488                 es = 1;
 489         } else if (cs->word_len <= 16) {
 490                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 491                 es = 2;
 492         } else {
 493                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 494                 es = 4;
 495         }
 496
 497         memset(&cfg, 0, sizeof(cfg));
 498         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 499         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 500         cfg.src_addr_width = width;
 501         cfg.dst_addr_width = width;
 502         cfg.src_maxburst = 1;
 503         cfg.dst_maxburst = 1;
 504
 505         rx = xfer->rx_buf;
 506         tx = xfer->tx_buf;
 507
 508         count = xfer->len;
 509
 510         if (tx != NULL)
 511                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 512
 513         if (rx != NULL)
 514                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 515
 516         if (tx != NULL) {
 517                 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 518                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 519                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 520                                  DMA_TO_DEVICE);
 521
 522                 /* for TX_ONLY mode, be sure all words have shifted out */
 523                 if (rx == NULL) {
 524                         if (mcspi_wait_for_reg_bit(chstat_reg,
 525                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0)
 526                                 dev_err(&spi->dev, "TXS timed out\n");
 527                         else if (mcspi_wait_for_reg_bit(chstat_reg,
 528                                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 529                                 dev_err(&spi->dev, "EOT timed out\n");
 530                 }
 531         }
 532         return count;
 533 }
 534
 535 static unsigned
 536 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 537 {
 538         struct omap2_mcspi      *mcspi;
 539         struct omap2_mcspi_cs   *cs = spi->controller_state;
 540         unsigned int            count, c;
 541         u32                     l;
 542         void __iomem            *base = cs->base;
 543         void __iomem            *tx_reg;
 544         void __iomem            *rx_reg;
 545         void __iomem            *chstat_reg;
 546         int                     word_len;
 547
 548         mcspi = spi_master_get_devdata(spi->master);
 549         count = xfer->len;
 550         c = count;
 551         word_len = cs->word_len;
 552
 553         l = mcspi_cached_chconf0(spi);
 554
 555         /* We store the pre-calculated register addresses on stack to speed
 556          * up the transfer loop. */
 557         tx_reg          = base + OMAP2_MCSPI_TX0;
 558         rx_reg          = base + OMAP2_MCSPI_RX0;
 559         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 560
 561         if (c < (word_len>>3))
 562                 return 0;
 563
 564         if (word_len <= 8) {
 565                 u8              *rx;
 566                 const u8        *tx;
 567
 568                 rx = xfer->rx_buf;
 569                 tx = xfer->tx_buf;
 570
 571                 do {
 572                         c -= 1;
 573                         if (tx != NULL) {
 574                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 575                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 576                                         dev_err(&spi->dev, "TXS timed out\n");
 577                                         goto out;
 578                                 }
 579                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 580                                                 word_len, *tx);
 581                                 __raw_writel(*tx++, tx_reg);
 582                         }
 583                         if (rx != NULL) {
 584                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 585                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 586                                         dev_err(&spi->dev, "RXS timed out\n");
 587                                         goto out;
 588                                 }
 589
 590                                 if (c == 1 && tx == NULL &&
 591                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 592                                         omap2_mcspi_set_enable(spi, 0);
 593                                         *rx++ = __raw_readl(rx_reg);
 594                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 595                                                     word_len, *(rx - 1));
 596                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 597                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 598                                                 dev_err(&spi->dev,
 599                                                         "RXS timed out\n");
 600                                                 goto out;
 601                                         }
 602                                         c = 0;
 603                                 } else if (c == 0 && tx == NULL) {
 604                                         omap2_mcspi_set_enable(spi, 0);
 605                                 }
 606
 607                                 *rx++ = __raw_readl(rx_reg);
 608                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 609                                                 word_len, *(rx - 1));
 610                         }
 611                 } while (c);
 612         } else if (word_len <= 16) {
 613                 u16             *rx;
 614                 const u16       *tx;
 615
 616                 rx = xfer->rx_buf;
 617                 tx = xfer->tx_buf;
 618                 do {
 619                         c -= 2;
 620                         if (tx != NULL) {
 621                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 622                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 623                                         dev_err(&spi->dev, "TXS timed out\n");
 624                                         goto out;
 625                                 }
 626                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 627                                                 word_len, *tx);
 628                                 __raw_writel(*tx++, tx_reg);
 629                         }
 630                         if (rx != NULL) {
 631                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 632                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 633                                         dev_err(&spi->dev, "RXS timed out\n");
 634                                         goto out;
 635                                 }
 636
 637                                 if (c == 2 && tx == NULL &&
 638                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 639                                         omap2_mcspi_set_enable(spi, 0);
 640                                         *rx++ = __raw_readl(rx_reg);
 641                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 642                                                     word_len, *(rx - 1));
 643                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 644                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 645                                                 dev_err(&spi->dev,
 646                                                         "RXS timed out\n");
 647                                                 goto out;
 648                                         }
 649                                         c = 0;
 650                                 } else if (c == 0 && tx == NULL) {
 651                                         omap2_mcspi_set_enable(spi, 0);
 652                                 }
 653
 654                                 *rx++ = __raw_readl(rx_reg);
 655                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 656                                                 word_len, *(rx - 1));
 657                         }
 658                 } while (c >= 2);
 659         } else if (word_len <= 32) {
 660                 u32             *rx;
 661                 const u32       *tx;
 662
 663                 rx = xfer->rx_buf;
 664                 tx = xfer->tx_buf;
 665                 do {
 666                         c -= 4;
 667                         if (tx != NULL) {
 668                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 669                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 670                                         dev_err(&spi->dev, "TXS timed out\n");
 671                                         goto out;
 672                                 }
 673                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 674                                                 word_len, *tx);
 675                                 __raw_writel(*tx++, tx_reg);
 676                         }
 677                         if (rx != NULL) {
 678                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 679                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 680                                         dev_err(&spi->dev, "RXS timed out\n");
 681                                         goto out;
 682                                 }
 683
 684                                 if (c == 4 && tx == NULL &&
 685                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 686                                         omap2_mcspi_set_enable(spi, 0);
 687                                         *rx++ = __raw_readl(rx_reg);
 688                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 689                                                     word_len, *(rx - 1));
 690                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 691                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 692                                                 dev_err(&spi->dev,
 693                                                         "RXS timed out\n");
 694                                                 goto out;
 695                                         }
 696                                         c = 0;
 697                                 } else if (c == 0 && tx == NULL) {
 698                                         omap2_mcspi_set_enable(spi, 0);
 699                                 }
 700
 701                                 *rx++ = __raw_readl(rx_reg);
 702                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 703                                                 word_len, *(rx - 1));
 704                         }
 705                 } while (c >= 4);
 706         }
 707
 708         /* for TX_ONLY mode, be sure all words have shifted out */
 709         if (xfer->rx_buf == NULL) {
 710                 if (mcspi_wait_for_reg_bit(chstat_reg,
 711                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 712                         dev_err(&spi->dev, "TXS timed out\n");
 713                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 714                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 715                         dev_err(&spi->dev, "EOT timed out\n");
 716
 717                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 718                  * otherwise these rx datas will affect the direct following
 719                  * RX_ONLY transfer.
 720                  */
 721                 omap2_mcspi_set_enable(spi, 0);
 722         }
 723 out:
 724         omap2_mcspi_set_enable(spi, 1);
 725         return count - c;
 726 }
 727
 728 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 729 {
 730         u32 div;
 731
 732         for (div = 0; div < 15; div++)
 733                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 734                         return div;
 735
 736         return 15;
 737 }
 738
 739 /* called only when no transfer is active to this device */
 740 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 741                 struct spi_transfer *t)
 742 {
 743         struct omap2_mcspi_cs *cs = spi->controller_state;
 744         struct omap2_mcspi *mcspi;
 745         struct spi_master *spi_cntrl;
 746         u32 l = 0, div = 0;
 747         u8 word_len = spi->bits_per_word;
 748         u32 speed_hz = spi->max_speed_hz;
 749
 750         mcspi = spi_master_get_devdata(spi->master);
 751         spi_cntrl = mcspi->master;
 752
 753         if (t != NULL && t->bits_per_word)
 754                 word_len = t->bits_per_word;
 755
 756         cs->word_len = word_len;
 757
 758         if (t && t->speed_hz)
 759                 speed_hz = t->speed_hz;
 760
 761         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 762         div = omap2_mcspi_calc_divisor(speed_hz);
 763
 764         l = mcspi_cached_chconf0(spi);
 765
 766         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 767          * REVISIT: this controller could support SPI_3WIRE mode.
 768          */
 769         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 770                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 771                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 772                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 773         } else {
 774                 l |= OMAP2_MCSPI_CHCONF_IS;
 775                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 776                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 777         }
 778
 779         /* wordlength */
 780         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 781         l |= (word_len - 1) << 7;
 782
 783         /* set chipselect polarity; manage with FORCE */
 784         if (!(spi->mode & SPI_CS_HIGH))
 785                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 786         else
 787                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 788
 789         /* set clock divisor */
 790         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 791         l |= div << 2;
 792
 793         /* set SPI mode 0..3 */
 794         if (spi->mode & SPI_CPOL)
 795                 l |= OMAP2_MCSPI_CHCONF_POL;
 796         else
 797                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 798         if (spi->mode & SPI_CPHA)
 799                 l |= OMAP2_MCSPI_CHCONF_PHA;
 800         else
 801                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 802
 803         mcspi_write_chconf0(spi, l);
 804
 805         cs->mode = spi->mode;
 806
 807         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 808                         OMAP2_MCSPI_MAX_FREQ >> div,
 809                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 810                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 811
 812         return 0;
 813 }
 814
 815 /*
 816  * Note that we currently allow DMA only if we get a channel
 817  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 818  */
 819 static int omap2_mcspi_request_dma(struct spi_device *spi)
 820 {
 821         struct spi_master       *master = spi->master;
 822         struct omap2_mcspi      *mcspi;
 823         struct omap2_mcspi_dma  *mcspi_dma;
 824         dma_cap_mask_t mask;
 825         unsigned sig;
 826
 827         mcspi = spi_master_get_devdata(master);
 828         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 829
 830         init_completion(&mcspi_dma->dma_rx_completion);
 831         init_completion(&mcspi_dma->dma_tx_completion);
 832
 833         dma_cap_zero(mask);
 834         dma_cap_set(DMA_SLAVE, mask);
 835         sig = mcspi_dma->dma_rx_sync_dev;
 836         mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 837         if (!mcspi_dma->dma_rx)
 838                 goto no_dma;
 839
 840         sig = mcspi_dma->dma_tx_sync_dev;
 841         mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 842         if (!mcspi_dma->dma_tx) {
 843                 dma_release_channel(mcspi_dma->dma_rx);
 844                 mcspi_dma->dma_rx = NULL;
 845                 goto no_dma;
 846         }
 847
 848         return 0;
 849
 850 no_dma:
 851         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 852         return -EAGAIN;
 853 }
 854
 855 static int omap2_mcspi_setup(struct spi_device *spi)
 856 {
 857         int                     ret;
 858         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 859         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 860         struct omap2_mcspi_dma  *mcspi_dma;
 861         struct omap2_mcspi_cs   *cs = spi->controller_state;
 862
 863         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 864                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 865                         spi->bits_per_word);
 866                 return -EINVAL;
 867         }
 868
 869         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 870
 871         if (!cs) {
 872                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 873                 if (!cs)
 874                         return -ENOMEM;
 875                 cs->base = mcspi->base + spi->chip_select * 0x14;
 876                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 877                 cs->mode = 0;
 878                 cs->chconf0 = 0;
 879                 spi->controller_state = cs;
 880                 /* Link this to context save list */
 881                 list_add_tail(&cs->node, &ctx->cs);
 882         }
 883
 884         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 885                 ret = omap2_mcspi_request_dma(spi);
 886                 if (ret < 0 && ret != -EAGAIN)
 887                         return ret;
 888         }
 889
 890         ret = pm_runtime_get_sync(mcspi->dev);
 891         if (ret < 0)
 892                 return ret;
 893
 894         ret = omap2_mcspi_setup_transfer(spi, NULL);
 895         pm_runtime_mark_last_busy(mcspi->dev);
 896         pm_runtime_put_autosuspend(mcspi->dev);
 897
 898         return ret;
 899 }
 900
 901 static void omap2_mcspi_cleanup(struct spi_device *spi)
 902 {
 903         struct omap2_mcspi      *mcspi;
 904         struct omap2_mcspi_dma  *mcspi_dma;
 905         struct omap2_mcspi_cs   *cs;
 906
 907         mcspi = spi_master_get_devdata(spi->master);
 908
 909         if (spi->controller_state) {
 910                 /* Unlink controller state from context save list */
 911                 cs = spi->controller_state;
 912                 list_del(&cs->node);
 913
 914                 kfree(cs);
 915         }
 916
 917         if (spi->chip_select < spi->master->num_chipselect) {
 918                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 919
 920                 if (mcspi_dma->dma_rx) {
 921                         dma_release_channel(mcspi_dma->dma_rx);
 922                         mcspi_dma->dma_rx = NULL;
 923                 }
 924                 if (mcspi_dma->dma_tx) {
 925                         dma_release_channel(mcspi_dma->dma_tx);
 926                         mcspi_dma->dma_tx = NULL;
 927                 }
 928         }
 929 }
 930
 931 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
 932 {
 933
 934         /* We only enable one channel at a time -- the one whose message is
 935          * -- although this controller would gladly
 936          * arbitrate among multiple channels.  This corresponds to "single
 937          * channel" master mode.  As a side effect, we need to manage the
 938          * chipselect with the FORCE bit ... CS != channel enable.
 939          */
 940
 941         struct spi_device               *spi;
 942         struct spi_transfer             *t = NULL;
 943         struct spi_master               *master;
 944         struct omap2_mcspi_dma          *mcspi_dma;
 945         int                             cs_active = 0;
 946         struct omap2_mcspi_cs           *cs;
 947         struct omap2_mcspi_device_config *cd;
 948         int                             par_override = 0;
 949         int                             status = 0;
 950         u32                             chconf;
 951
 952         spi = m->spi;
 953         master = spi->master;
 954         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 955         cs = spi->controller_state;
 956         cd = spi->controller_data;
 957
 958         omap2_mcspi_set_enable(spi, 1);
 959         list_for_each_entry(t, &m->transfers, transfer_list) {
 960                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 961                         status = -EINVAL;
 962                         break;
 963                 }
 964                 if (par_override || t->speed_hz || t->bits_per_word) {
 965                         par_override = 1;
 966                         status = omap2_mcspi_setup_transfer(spi, t);
 967                         if (status < 0)
 968                                 break;
 969                         if (!t->speed_hz && !t->bits_per_word)
 970                                 par_override = 0;
 971                 }
 972                 if (cd && cd->cs_per_word) {
 973                         chconf = mcspi->ctx.modulctrl;
 974                         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
 975                         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
 976                         mcspi->ctx.modulctrl =
 977                                 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
 978                 }
 979
 980
 981                 if (!cs_active) {
 982                         omap2_mcspi_force_cs(spi, 1);
 983                         cs_active = 1;
 984                 }
 985
 986                 chconf = mcspi_cached_chconf0(spi);
 987                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 988                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 989
 990                 if (t->tx_buf == NULL)
 991                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 992                 else if (t->rx_buf == NULL)
 993                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 994
 995                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 996                         /* Turbo mode is for more than one word */
 997                         if (t->len > ((cs->word_len + 7) >> 3))
 998                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 999                 }
1000
1001                 mcspi_write_chconf0(spi, chconf);
1002
1003                 if (t->len) {
1004                         unsigned        count;
1005
1006                         /* RX_ONLY mode needs dummy data in TX reg */
1007                         if (t->tx_buf == NULL)
1008                                 __raw_writel(0, cs->base
1009                                                 + OMAP2_MCSPI_TX0);
1010
1011                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1012                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1013                                 count = omap2_mcspi_txrx_dma(spi, t);
1014                         else
1015                                 count = omap2_mcspi_txrx_pio(spi, t);
1016                         m->actual_length += count;
1017
1018                         if (count != t->len) {
1019                                 status = -EIO;
1020                                 break;
1021                         }
1022                 }
1023
1024                 if (t->delay_usecs)
1025                         udelay(t->delay_usecs);
1026
1027                 /* ignore the "leave it on after last xfer" hint */
1028                 if (t->cs_change) {
1029                         omap2_mcspi_force_cs(spi, 0);
1030                         cs_active = 0;
1031                 }
1032         }
1033         /* Restore defaults if they were overriden */
1034         if (par_override) {
1035                 par_override = 0;
1036                 status = omap2_mcspi_setup_transfer(spi, NULL);
1037         }
1038
1039         if (cs_active)
1040                 omap2_mcspi_force_cs(spi, 0);
1041
1042         if (cd && cd->cs_per_word) {
1043                 chconf = mcspi->ctx.modulctrl;
1044                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1045                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1046                 mcspi->ctx.modulctrl =
1047                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1048         }
1049
1050         /*
1051          * The slave driver could have changed spi->mode in which case
1052          * it will be different from cs->mode (the current hardware setup).
1053          * If so, set par_override (even though its not a parity issue) so
1054          * omap2_mcspi_setup_transfer will be called to configure the hardware
1055          * with the correct mode on the first iteration of the loop below.
1056          */
1057         if (spi->mode != cs->mode)
1058                 par_override = 1;
1059
1060         omap2_mcspi_set_enable(spi, 0);
1061
1062         m->status = status;
1063
1064 }
1065
1066 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1067                 struct spi_message *m)
1068 {
1069         struct spi_device       *spi;
1070         struct omap2_mcspi      *mcspi;
1071         struct omap2_mcspi_dma  *mcspi_dma;
1072         struct spi_transfer     *t;
1073
1074         spi = m->spi;
1075         mcspi = spi_master_get_devdata(master);
1076         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1077         m->actual_length = 0;
1078         m->status = 0;
1079
1080         /* reject invalid messages and transfers */
1081         if (list_empty(&m->transfers))
1082                 return -EINVAL;
1083         list_for_each_entry(t, &m->transfers, transfer_list) {
1084                 const void      *tx_buf = t->tx_buf;
1085                 void            *rx_buf = t->rx_buf;
1086                 unsigned        len = t->len;
1087
1088                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1089                                 || (len && !(rx_buf || tx_buf))
1090                                 || (t->bits_per_word &&
1091                                         (  t->bits_per_word < 4
1092                                            || t->bits_per_word > 32))) {
1093                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1094                                         t->speed_hz,
1095                                         len,
1096                                         tx_buf ? "tx" : "",
1097                                         rx_buf ? "rx" : "",
1098                                         t->bits_per_word);
1099                         return -EINVAL;
1100                 }
1101                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1102                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1103                                         t->speed_hz,
1104                                         OMAP2_MCSPI_MAX_FREQ >> 15);
1105                         return -EINVAL;
1106                 }
1107
1108                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1109                         continue;
1110
1111                 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1112                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1113                                         len, DMA_TO_DEVICE);
1114                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1115                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1116                                                 'T', len);
1117                                 return -EINVAL;
1118                         }
1119                 }
1120                 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1121                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1122                                         DMA_FROM_DEVICE);
1123                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1124                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1125                                                 'R', len);
1126                                 if (tx_buf != NULL)
1127                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1128                                                         len, DMA_TO_DEVICE);
1129                                 return -EINVAL;
1130                         }
1131                 }
1132         }
1133
1134         omap2_mcspi_work(mcspi, m);
1135         spi_finalize_current_message(master);
1136         return 0;
1137 }
1138
1139 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1140 {
1141         struct spi_master       *master = mcspi->master;
1142         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1143         int                     ret = 0;
1144
1145         ret = pm_runtime_get_sync(mcspi->dev);
1146         if (ret < 0)
1147                 return ret;
1148
1149         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1150                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1151         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1152
1153         omap2_mcspi_set_master_mode(master);
1154         pm_runtime_mark_last_busy(mcspi->dev);
1155         pm_runtime_put_autosuspend(mcspi->dev);
1156         return 0;
1157 }
1158
1159 static int omap_mcspi_runtime_resume(struct device *dev)
1160 {
1161         struct omap2_mcspi      *mcspi;
1162         struct spi_master       *master;
1163
1164         master = dev_get_drvdata(dev);
1165         mcspi = spi_master_get_devdata(master);
1166         omap2_mcspi_restore_ctx(mcspi);
1167
1168         return 0;
1169 }
1170
1171 static struct omap2_mcspi_platform_config omap2_pdata = {
1172         .regs_offset = 0,
1173 };
1174
1175 static struct omap2_mcspi_platform_config omap4_pdata = {
1176         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1177 };
1178
1179 static const struct of_device_id omap_mcspi_of_match[] = {
1180         {
1181                 .compatible = "ti,omap2-mcspi",
1182                 .data = &omap2_pdata,
1183         },
1184         {
1185                 .compatible = "ti,omap4-mcspi",
1186                 .data = &omap4_pdata,
1187         },
1188         { },
1189 };
1190 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1191
1192 static int omap2_mcspi_probe(struct platform_device *pdev)
1193 {
1194         struct spi_master       *master;
1195         const struct omap2_mcspi_platform_config *pdata;
1196         struct omap2_mcspi      *mcspi;
1197         struct resource         *r;
1198         int                     status = 0, i;
1199         u32                     regs_offset = 0;
1200         static int              bus_num = 1;
1201         struct device_node      *node = pdev->dev.of_node;
1202         const struct of_device_id *match;
1203         struct pinctrl *pinctrl;
1204
1205         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1206         if (master == NULL) {
1207                 dev_dbg(&pdev->dev, "master allocation failed\n");
1208                 return -ENOMEM;
1209         }
1210
1211         /* the spi->mode bits understood by this driver: */
1212         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1213
1214         master->setup = omap2_mcspi_setup;
1215         master->prepare_transfer_hardware = omap2_prepare_transfer;
1216         master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1217         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1218         master->cleanup = omap2_mcspi_cleanup;
1219         master->dev.of_node = node;
1220
1221         dev_set_drvdata(&pdev->dev, master);
1222
1223         mcspi = spi_master_get_devdata(master);
1224         mcspi->master = master;
1225
1226         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1227         if (match) {
1228                 u32 num_cs = 1; /* default number of chipselect */
1229                 pdata = match->data;
1230
1231                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1232                 master->num_chipselect = num_cs;
1233                 master->bus_num = bus_num++;
1234                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1235                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1236         } else {
1237                 pdata = pdev->dev.platform_data;
1238                 master->num_chipselect = pdata->num_cs;
1239                 if (pdev->id != -1)
1240                         master->bus_num = pdev->id;
1241                 mcspi->pin_dir = pdata->pin_dir;
1242         }
1243         regs_offset = pdata->regs_offset;
1244
1245         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1246         if (r == NULL) {
1247                 status = -ENODEV;
1248                 goto free_master;
1249         }
1250
1251         r->start += regs_offset;
1252         r->end += regs_offset;
1253         mcspi->phys = r->start;
1254
1255         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1256         if (IS_ERR(mcspi->base)) {
1257                 status = PTR_ERR(mcspi->base);
1258                 goto free_master;
1259         }
1260
1261         mcspi->dev = &pdev->dev;
1262
1263         INIT_LIST_HEAD(&mcspi->ctx.cs);
1264
1265         mcspi->dma_channels = kcalloc(master->num_chipselect,
1266                         sizeof(struct omap2_mcspi_dma),
1267                         GFP_KERNEL);
1268
1269         if (mcspi->dma_channels == NULL)
1270                 goto free_master;
1271
1272         for (i = 0; i < master->num_chipselect; i++) {
1273                 char dma_ch_name[14];
1274                 struct resource *dma_res;
1275
1276                 sprintf(dma_ch_name, "rx%d", i);
1277                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1278                                 dma_ch_name);
1279                 if (!dma_res) {
1280                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1281                         status = -ENODEV;
1282                         break;
1283                 }
1284
1285                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1286                 sprintf(dma_ch_name, "tx%d", i);
1287                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1288                                 dma_ch_name);
1289                 if (!dma_res) {
1290                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1291                         status = -ENODEV;
1292                         break;
1293                 }
1294
1295                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1296         }
1297
1298         if (status < 0)
1299                 goto dma_chnl_free;
1300
1301         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1302         if (IS_ERR(pinctrl))
1303                 dev_warn(&pdev->dev,
1304                                 "pins are not configured from the driver\n");
1305
1306         pm_runtime_use_autosuspend(&pdev->dev);
1307         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1308         pm_runtime_enable(&pdev->dev);
1309
1310         status = omap2_mcspi_master_setup(mcspi);
1311         if (status < 0)
1312                 goto disable_pm;
1313
1314         status = spi_register_master(master);
1315         if (status < 0)
1316                 goto disable_pm;
1317
1318         return status;
1319
1320 disable_pm:
1321         pm_runtime_disable(&pdev->dev);
1322 dma_chnl_free:
1323         kfree(mcspi->dma_channels);
1324 free_master:
1325         spi_master_put(master);
1326         return status;
1327 }
1328
1329 static int omap2_mcspi_remove(struct platform_device *pdev)
1330 {
1331         struct spi_master       *master;
1332         struct omap2_mcspi      *mcspi;
1333         struct omap2_mcspi_dma  *dma_channels;
1334
1335         master = dev_get_drvdata(&pdev->dev);
1336         mcspi = spi_master_get_devdata(master);
1337         dma_channels = mcspi->dma_channels;
1338
1339         pm_runtime_put_sync(mcspi->dev);
1340         pm_runtime_disable(&pdev->dev);
1341
1342         spi_unregister_master(master);
1343         kfree(dma_channels);
1344
1345         return 0;
1346 }
1347
1348 /* work with hotplug and coldplug */
1349 MODULE_ALIAS("platform:omap2_mcspi");
1350
1351 #ifdef  CONFIG_SUSPEND
1352 /*
1353  * When SPI wake up from off-mode, CS is in activate state. If it was in
1354  * unactive state when driver was suspend, then force it to unactive state at
1355  * wake up.
1356  */
1357 static int omap2_mcspi_resume(struct device *dev)
1358 {
1359         struct spi_master       *master = dev_get_drvdata(dev);
1360         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1361         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1362         struct omap2_mcspi_cs   *cs;
1363
1364         pm_runtime_get_sync(mcspi->dev);
1365         list_for_each_entry(cs, &ctx->cs, node) {
1366                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1367                         /*
1368                          * We need to toggle CS state for OMAP take this
1369                          * change in account.
1370                          */
1371                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1372                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1373                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1374                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1375                 }
1376         }
1377         pm_runtime_mark_last_busy(mcspi->dev);
1378         pm_runtime_put_autosuspend(mcspi->dev);
1379         return 0;
1380 }
1381 #else
1382 #define omap2_mcspi_resume      NULL
1383 #endif
1384
1385 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1386         .resume = omap2_mcspi_resume,
1387         .runtime_resume = omap_mcspi_runtime_resume,
1388 };
1389
1390 static struct platform_driver omap2_mcspi_driver = {
1391         .driver = {
1392                 .name =         "omap2_mcspi",
1393                 .owner =        THIS_MODULE,
1394                 .pm =           &omap2_mcspi_pm_ops,
1395                 .of_match_table = omap_mcspi_of_match,
1396         },
1397         .probe =        omap2_mcspi_probe,
1398         .remove =       omap2_mcspi_remove,
1399 };
1400
1401 module_platform_driver(omap2_mcspi_driver);
1402 MODULE_LICENSE("GPL");