2 * Freescale MXS SPI master driver
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
42 #include <linux/highmem.h>
43 #include <linux/clk.h>
44 #include <linux/err.h>
45 #include <linux/completion.h>
46 #include <linux/gpio.h>
47 #include <linux/regulator/consumer.h>
48 #include <linux/module.h>
49 #include <linux/stmp_device.h>
50 #include <linux/spi/spi.h>
51 #include <linux/spi/mxs-spi.h>
53 #define DRIVER_NAME "mxs-spi"
55 /* Use 10S timeout for very long transfers, it should suffice. */
56 #define SSP_TIMEOUT 10000
58 #define SG_MAXLEN 0xff00
61 * Flags for txrx functions. More efficient that using an argument register for
64 #define TXRX_WRITE (1<<0) /* This is a write */
65 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
72 static int mxs_spi_setup_transfer(struct spi_device *dev,
73 struct spi_transfer *t)
75 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
76 struct mxs_ssp *ssp = &spi->ssp;
79 hz = dev->max_speed_hz;
81 hz = min(hz, t->speed_hz);
83 dev_err(&dev->dev, "Cannot continue with zero clock\n");
87 mxs_ssp_set_clk_rate(ssp, hz);
89 writel(BM_SSP_CTRL0_LOCK_CS,
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
91 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
92 BF_SSP_CTRL1_WORD_LENGTH
93 (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
94 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
95 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
96 ssp->base + HW_SSP_CTRL1(ssp));
98 writel(0x0, ssp->base + HW_SSP_CMD0);
99 writel(0x0, ssp->base + HW_SSP_CMD1);
104 static int mxs_spi_setup(struct spi_device *dev)
108 if (!dev->bits_per_word)
109 dev->bits_per_word = 8;
111 if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
114 err = mxs_spi_setup_transfer(dev, NULL);
117 "Failed to setup transfer, error = %d\n", err);
123 static uint32_t mxs_spi_cs_to_reg(unsigned cs)
128 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
130 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
131 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
132 * the datasheet for further details. In SPI mode, they are used to
133 * toggle the chip-select lines (nCS pins).
136 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
138 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
143 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
145 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
146 struct mxs_ssp *ssp = &spi->ssp;
150 reg = readl_relaxed(ssp->base + offset);
159 } while (time_before(jiffies, timeout));
164 static void mxs_ssp_dma_irq_callback(void *param)
166 struct mxs_spi *spi = param;
170 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
172 struct mxs_ssp *ssp = dev_id;
173 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
175 readl(ssp->base + HW_SSP_CTRL1(ssp)),
176 readl(ssp->base + HW_SSP_STATUS(ssp)));
180 static int mxs_spi_txrx_dma(struct mxs_spi *spi,
181 unsigned char *buf, int len,
184 struct mxs_ssp *ssp = &spi->ssp;
185 struct dma_async_tx_descriptor *desc = NULL;
186 const bool vmalloced_buf = is_vmalloc_addr(buf);
187 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
188 const int sgs = DIV_ROUND_UP(len, desc_len);
192 struct page *vm_page;
196 struct scatterlist sg;
202 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
206 INIT_COMPLETION(spi->c);
208 /* Chip select was already programmed into CTRL0 */
209 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
210 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
212 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
214 if (!(flags & TXRX_WRITE))
215 ctrl0 |= BM_SSP_CTRL0_READ;
217 /* Queue the DMA data transfer. */
218 for (sg_count = 0; sg_count < sgs; sg_count++) {
219 /* Prepare the transfer descriptor. */
220 min = min(len, desc_len);
223 * De-assert CS on last segment if flag is set (i.e., no more
224 * transfers will follow)
226 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
227 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
229 if (ssp->devid == IMX23_SSP) {
230 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
234 dma_xfer[sg_count].pio[0] = ctrl0;
235 dma_xfer[sg_count].pio[3] = min;
238 vm_page = vmalloc_to_page(buf);
243 sg_buf = page_address(vm_page) +
244 ((size_t)buf & ~PAGE_MASK);
249 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
250 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
251 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
256 /* Queue the PIO register write transfer. */
257 desc = dmaengine_prep_slave_sg(ssp->dmach,
258 (struct scatterlist *)dma_xfer[sg_count].pio,
259 (ssp->devid == IMX23_SSP) ? 1 : 4,
261 sg_count ? DMA_PREP_INTERRUPT : 0);
264 "Failed to get PIO reg. write descriptor.\n");
269 desc = dmaengine_prep_slave_sg(ssp->dmach,
270 &dma_xfer[sg_count].sg, 1,
271 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
272 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
276 "Failed to get DMA data write descriptor.\n");
283 * The last descriptor must have this callback,
284 * to finish the DMA transaction.
286 desc->callback = mxs_ssp_dma_irq_callback;
287 desc->callback_param = spi;
289 /* Start the transfer. */
290 dmaengine_submit(desc);
291 dma_async_issue_pending(ssp->dmach);
293 ret = wait_for_completion_timeout(&spi->c,
294 msecs_to_jiffies(SSP_TIMEOUT));
296 dev_err(ssp->dev, "DMA transfer timeout\n");
298 dmaengine_terminate_all(ssp->dmach);
305 while (--sg_count >= 0) {
307 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
308 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
316 static int mxs_spi_txrx_pio(struct mxs_spi *spi,
317 unsigned char *buf, int len,
320 struct mxs_ssp *ssp = &spi->ssp;
322 writel(BM_SSP_CTRL0_IGNORE_CRC,
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
326 if (len == 0 && (flags & TXRX_DEASSERT_CS))
327 writel(BM_SSP_CTRL0_IGNORE_CRC,
328 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
330 if (ssp->devid == IMX23_SSP) {
331 writel(BM_SSP_CTRL0_XFER_COUNT,
332 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
334 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
336 writel(1, ssp->base + HW_SSP_XFER_SIZE);
339 if (flags & TXRX_WRITE)
340 writel(BM_SSP_CTRL0_READ,
341 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
343 writel(BM_SSP_CTRL0_READ,
344 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
346 writel(BM_SSP_CTRL0_RUN,
347 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
349 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
352 if (flags & TXRX_WRITE)
353 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
355 writel(BM_SSP_CTRL0_DATA_XFER,
356 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
358 if (!(flags & TXRX_WRITE)) {
359 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
360 BM_SSP_STATUS_FIFO_EMPTY, 0))
363 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
366 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
378 static int mxs_spi_transfer_one(struct spi_master *master,
379 struct spi_message *m)
381 struct mxs_spi *spi = spi_master_get_devdata(master);
382 struct mxs_ssp *ssp = &spi->ssp;
383 struct spi_transfer *t, *tmp_t;
387 /* Program CS register bits here, it will be used for all transfers. */
388 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
389 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
390 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
391 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
393 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
395 status = mxs_spi_setup_transfer(m->spi, t);
399 /* De-assert on last transfer, inverted by cs_change flag */
400 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
401 TXRX_DEASSERT_CS : 0;
404 * Small blocks can be transfered via PIO.
405 * Measured by empiric means:
407 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
409 * DMA only: 2.164808 seconds, 473.0KB/s
410 * Combined: 1.676276 seconds, 610.9KB/s
413 writel(BM_SSP_CTRL1_DMA_ENABLE,
414 ssp->base + HW_SSP_CTRL1(ssp) +
415 STMP_OFFSET_REG_CLR);
418 status = mxs_spi_txrx_pio(spi,
420 t->len, flag | TXRX_WRITE);
422 status = mxs_spi_txrx_pio(spi,
426 writel(BM_SSP_CTRL1_DMA_ENABLE,
427 ssp->base + HW_SSP_CTRL1(ssp) +
428 STMP_OFFSET_REG_SET);
431 status = mxs_spi_txrx_dma(spi,
432 (void *)t->tx_buf, t->len,
435 status = mxs_spi_txrx_dma(spi,
441 stmp_reset_block(ssp->base);
445 m->actual_length += t->len;
449 spi_finalize_current_message(master);
454 static const struct of_device_id mxs_spi_dt_ids[] = {
455 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
456 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
459 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
461 static int mxs_spi_probe(struct platform_device *pdev)
463 const struct of_device_id *of_id =
464 of_match_device(mxs_spi_dt_ids, &pdev->dev);
465 struct device_node *np = pdev->dev.of_node;
466 struct spi_master *master;
469 struct resource *iores;
473 int ret = 0, irq_err;
476 * Default clock speed for the SPI core. 160MHz seems to
477 * work reasonably well with most SPI flashes, so use this
478 * as a default. Override with "clock-frequency" DT prop.
480 const int clk_freq_default = 160000000;
482 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
483 irq_err = platform_get_irq(pdev, 0);
487 base = devm_ioremap_resource(&pdev->dev, iores);
489 return PTR_ERR(base);
491 clk = devm_clk_get(&pdev->dev, NULL);
495 devid = (enum mxs_ssp_id) of_id->data;
496 ret = of_property_read_u32(np, "clock-frequency",
499 clk_freq = clk_freq_default;
501 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
505 master->transfer_one_message = mxs_spi_transfer_one;
506 master->setup = mxs_spi_setup;
507 master->bits_per_word_mask = SPI_BPW_MASK(8);
508 master->mode_bits = SPI_CPOL | SPI_CPHA;
509 master->num_chipselect = 3;
510 master->dev.of_node = np;
511 master->flags = SPI_MASTER_HALF_DUPLEX;
513 spi = spi_master_get_devdata(master);
515 ssp->dev = &pdev->dev;
520 init_completion(&spi->c);
522 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
525 goto out_master_free;
527 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
529 dev_err(ssp->dev, "Failed to request DMA\n");
531 goto out_master_free;
534 ret = clk_prepare_enable(ssp->clk);
536 goto out_dma_release;
538 clk_set_rate(ssp->clk, clk_freq);
539 ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
541 ret = stmp_reset_block(ssp->base);
543 goto out_disable_clk;
545 platform_set_drvdata(pdev, master);
547 ret = spi_register_master(master);
549 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
550 goto out_disable_clk;
556 clk_disable_unprepare(ssp->clk);
558 dma_release_channel(ssp->dmach);
560 spi_master_put(master);
564 static int mxs_spi_remove(struct platform_device *pdev)
566 struct spi_master *master;
570 master = spi_master_get(platform_get_drvdata(pdev));
571 spi = spi_master_get_devdata(master);
574 spi_unregister_master(master);
575 clk_disable_unprepare(ssp->clk);
576 dma_release_channel(ssp->dmach);
577 spi_master_put(master);
582 static struct platform_driver mxs_spi_driver = {
583 .probe = mxs_spi_probe,
584 .remove = mxs_spi_remove,
587 .owner = THIS_MODULE,
588 .of_match_table = mxs_spi_dt_ids,
592 module_platform_driver(mxs_spi_driver);
594 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
595 MODULE_DESCRIPTION("MXS SPI master driver");
596 MODULE_LICENSE("GPL");
597 MODULE_ALIAS("platform:mxs-spi");