2 * Freescale SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
14 * Copyright (c) 2012 Aeroflex Gaisler AB.
15 * Author: Andreas Larsson <andreas@gaisler.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/gpio.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_gpio.h>
36 #include <linux/of_platform.h>
37 #include <linux/platform_device.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/spi_bitbang.h>
40 #include <linux/types.h>
42 #include "spi-fsl-lib.h"
43 #include "spi-fsl-cpm.h"
44 #include "spi-fsl-spi.h"
49 struct fsl_spi_match_data {
53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
61 static const struct of_device_id of_fsl_spi_match[] = {
63 .compatible = "fsl,spi",
64 .data = &of_fsl_spi_fsl_config,
67 .compatible = "aeroflexgaisler,spictrl",
68 .data = &of_fsl_spi_grlib_config,
72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
74 static int fsl_spi_get_type(struct device *dev)
76 const struct of_device_id *match;
79 match = of_match_node(of_fsl_spi_match, dev->of_node);
80 if (match && match->data)
81 return ((struct fsl_spi_match_data *)match->data)->type;
86 static void fsl_spi_change_mode(struct spi_device *spi)
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
89 struct spi_mpc8xxx_cs *cs = spi->controller_state;
90 struct fsl_spi_reg *reg_base = mspi->reg_base;
91 __be32 __iomem *mode = ®_base->mode;
94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags);
100 /* Turn off SPI unit prior changing mode */
101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
103 /* When in CPM mode, we need to reinit tx and rx. */
104 if (mspi->flags & SPI_CPM_MODE) {
105 fsl_spi_cpm_reinit_txrx(mspi);
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108 local_irq_restore(flags);
111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
114 struct fsl_spi_platform_data *pdata;
115 bool pol = spi->mode & SPI_CS_HIGH;
116 struct spi_mpc8xxx_cs *cs = spi->controller_state;
118 pdata = spi->dev.parent->parent->platform_data;
120 if (value == BITBANG_CS_INACTIVE) {
121 if (pdata->cs_control)
122 pdata->cs_control(spi, !pol);
125 if (value == BITBANG_CS_ACTIVE) {
126 mpc8xxx_spi->rx_shift = cs->rx_shift;
127 mpc8xxx_spi->tx_shift = cs->tx_shift;
128 mpc8xxx_spi->get_rx = cs->get_rx;
129 mpc8xxx_spi->get_tx = cs->get_tx;
131 fsl_spi_change_mode(spi);
133 if (pdata->cs_control)
134 pdata->cs_control(spi, pol);
138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
139 int bits_per_word, int msb_first)
144 if (bits_per_word <= 8) {
147 } else if (bits_per_word <= 16) {
152 if (bits_per_word <= 8)
157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
158 int bits_per_word, int msb_first)
162 if (bits_per_word <= 16) {
164 *rx_shift = 16; /* LSB in bit 16 */
165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
173 struct spi_device *spi,
174 struct mpc8xxx_spi *mpc8xxx_spi,
179 if (bits_per_word <= 8) {
180 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
181 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
182 } else if (bits_per_word <= 16) {
183 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
184 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
185 } else if (bits_per_word <= 32) {
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
191 if (mpc8xxx_spi->set_shifts)
192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
194 !(spi->mode & SPI_LSB_FIRST));
196 mpc8xxx_spi->rx_shift = cs->rx_shift;
197 mpc8xxx_spi->tx_shift = cs->tx_shift;
198 mpc8xxx_spi->get_rx = cs->get_rx;
199 mpc8xxx_spi->get_tx = cs->get_tx;
201 return bits_per_word;
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
205 struct spi_device *spi,
208 /* QE uses Little Endian for words > 8
209 * so transform all words > 8 into 8 bits
210 * Unfortnatly that doesn't work for LSB so
211 * reject these for now */
212 /* Note: 32 bits word, LSB works iff
213 * tfcr/rfcr is set to CPMFCR_GBL */
214 if (spi->mode & SPI_LSB_FIRST &&
217 if (bits_per_word > 8)
218 return 8; /* pretend its 8 bits */
219 return bits_per_word;
222 static int fsl_spi_setup_transfer(struct spi_device *spi,
223 struct spi_transfer *t)
225 struct mpc8xxx_spi *mpc8xxx_spi;
226 int bits_per_word = 0;
229 struct spi_mpc8xxx_cs *cs = spi->controller_state;
231 mpc8xxx_spi = spi_master_get_devdata(spi->master);
234 bits_per_word = t->bits_per_word;
238 /* spi_transfer level calls that work per-word */
240 bits_per_word = spi->bits_per_word;
243 hz = spi->max_speed_hz;
245 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
246 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
249 else if (mpc8xxx_spi->flags & SPI_QE)
250 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
253 if (bits_per_word < 0)
254 return bits_per_word;
256 if (bits_per_word == 32)
259 bits_per_word = bits_per_word - 1;
261 /* mask out bits we are going to set */
262 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 cs->hw_mode |= SPMODE_LEN(bits_per_word);
267 if ((mpc8xxx_spi->spibrg / hz) > 64) {
268 cs->hw_mode |= SPMODE_DIV16;
269 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
271 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
272 "Will use %d Hz instead.\n", dev_name(&spi->dev),
273 hz, mpc8xxx_spi->spibrg / 1024);
277 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
282 cs->hw_mode |= SPMODE_PM(pm);
284 fsl_spi_change_mode(spi);
288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
289 struct spi_transfer *t, unsigned int len)
292 struct fsl_spi_reg *reg_base = mspi->reg_base;
297 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
300 word = mspi->get_tx(mspi);
301 mpc8xxx_spi_write_reg(®_base->transmit, word);
306 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
309 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
310 struct fsl_spi_reg *reg_base;
311 unsigned int len = t->len;
315 reg_base = mpc8xxx_spi->reg_base;
316 bits_per_word = spi->bits_per_word;
317 if (t->bits_per_word)
318 bits_per_word = t->bits_per_word;
320 if (bits_per_word > 8) {
321 /* invalid length? */
326 if (bits_per_word > 16) {
327 /* invalid length? */
333 mpc8xxx_spi->tx = t->tx_buf;
334 mpc8xxx_spi->rx = t->rx_buf;
336 reinit_completion(&mpc8xxx_spi->done);
338 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
339 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
341 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
345 wait_for_completion(&mpc8xxx_spi->done);
347 /* disable rx ints */
348 mpc8xxx_spi_write_reg(®_base->mask, 0);
350 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
351 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
353 return mpc8xxx_spi->count;
356 static int fsl_spi_do_one_msg(struct spi_master *master,
357 struct spi_message *m)
359 struct spi_device *spi = m->spi;
360 struct spi_transfer *t, *first;
361 unsigned int cs_change;
362 const int nsecs = 50;
365 /* Don't allow changes if CS is active */
366 first = list_first_entry(&m->transfers, struct spi_transfer,
368 list_for_each_entry(t, &m->transfers, transfer_list) {
369 if ((first->bits_per_word != t->bits_per_word) ||
370 (first->speed_hz != t->speed_hz)) {
373 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
380 list_for_each_entry(t, &m->transfers, transfer_list) {
381 if (t->bits_per_word || t->speed_hz) {
383 status = fsl_spi_setup_transfer(spi, t);
389 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
392 cs_change = t->cs_change;
394 status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
399 m->actual_length += t->len;
402 udelay(t->delay_usecs);
406 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
412 spi_finalize_current_message(master);
414 if (status || !cs_change) {
416 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
419 fsl_spi_setup_transfer(spi, NULL);
423 static int fsl_spi_setup(struct spi_device *spi)
425 struct mpc8xxx_spi *mpc8xxx_spi;
426 struct fsl_spi_reg *reg_base;
429 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
431 if (!spi->max_speed_hz)
435 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
438 spi_set_ctldata(spi, cs);
440 mpc8xxx_spi = spi_master_get_devdata(spi->master);
442 reg_base = mpc8xxx_spi->reg_base;
444 hw_mode = cs->hw_mode; /* Save original settings */
445 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
446 /* mask out bits we are going to set */
447 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
448 | SPMODE_REV | SPMODE_LOOP);
450 if (spi->mode & SPI_CPHA)
451 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
452 if (spi->mode & SPI_CPOL)
453 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
454 if (!(spi->mode & SPI_LSB_FIRST))
455 cs->hw_mode |= SPMODE_REV;
456 if (spi->mode & SPI_LOOP)
457 cs->hw_mode |= SPMODE_LOOP;
459 retval = fsl_spi_setup_transfer(spi, NULL);
461 cs->hw_mode = hw_mode; /* Restore settings */
465 if (mpc8xxx_spi->type == TYPE_GRLIB) {
466 if (gpio_is_valid(spi->cs_gpio)) {
469 retval = gpio_request(spi->cs_gpio,
470 dev_name(&spi->dev));
474 desel = !(spi->mode & SPI_CS_HIGH);
475 retval = gpio_direction_output(spi->cs_gpio, desel);
477 gpio_free(spi->cs_gpio);
480 } else if (spi->cs_gpio != -ENOENT) {
481 if (spi->cs_gpio < 0)
485 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
486 * indicates to use native chipselect if present, or allow for
487 * an always selected chip
491 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
492 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
497 static void fsl_spi_cleanup(struct spi_device *spi)
499 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
500 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
502 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
503 gpio_free(spi->cs_gpio);
506 spi_set_ctldata(spi, NULL);
509 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
511 struct fsl_spi_reg *reg_base = mspi->reg_base;
513 /* We need handle RX first */
514 if (events & SPIE_NE) {
515 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
518 mspi->get_rx(rx_data, mspi);
521 if ((events & SPIE_NF) == 0)
522 /* spin until TX is done */
524 mpc8xxx_spi_read_reg(®_base->event)) &
528 /* Clear the events */
529 mpc8xxx_spi_write_reg(®_base->event, events);
533 u32 word = mspi->get_tx(mspi);
535 mpc8xxx_spi_write_reg(®_base->transmit, word);
537 complete(&mspi->done);
541 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
543 struct mpc8xxx_spi *mspi = context_data;
544 irqreturn_t ret = IRQ_NONE;
546 struct fsl_spi_reg *reg_base = mspi->reg_base;
548 /* Get interrupt events(tx/rx) */
549 events = mpc8xxx_spi_read_reg(®_base->event);
553 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
555 if (mspi->flags & SPI_CPM_MODE)
556 fsl_spi_cpm_irq(mspi, events);
558 fsl_spi_cpu_irq(mspi, events);
563 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
565 iounmap(mspi->reg_base);
566 fsl_spi_cpm_free(mspi);
569 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
571 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
572 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
574 u16 cs = spi->chip_select;
576 if (gpio_is_valid(spi->cs_gpio)) {
577 gpio_set_value(spi->cs_gpio, on);
578 } else if (cs < mpc8xxx_spi->native_chipselects) {
579 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
580 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
581 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
585 static void fsl_spi_grlib_probe(struct device *dev)
587 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
588 struct spi_master *master = dev_get_drvdata(dev);
589 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
590 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
594 capabilities = mpc8xxx_spi_read_reg(®_base->cap);
596 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
597 mbits = SPCAP_MAXWLEN(capabilities);
599 mpc8xxx_spi->max_bits_per_word = mbits + 1;
601 mpc8xxx_spi->native_chipselects = 0;
602 if (SPCAP_SSEN(capabilities)) {
603 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
604 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
606 master->num_chipselect = mpc8xxx_spi->native_chipselects;
607 pdata->cs_control = fsl_spi_grlib_cs_control;
610 static struct spi_master * fsl_spi_probe(struct device *dev,
611 struct resource *mem, unsigned int irq)
613 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
614 struct spi_master *master;
615 struct mpc8xxx_spi *mpc8xxx_spi;
616 struct fsl_spi_reg *reg_base;
620 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
621 if (master == NULL) {
626 dev_set_drvdata(dev, master);
628 mpc8xxx_spi_probe(dev, mem, irq);
630 master->setup = fsl_spi_setup;
631 master->cleanup = fsl_spi_cleanup;
632 master->transfer_one_message = fsl_spi_do_one_msg;
634 mpc8xxx_spi = spi_master_get_devdata(master);
635 mpc8xxx_spi->spi_remove = fsl_spi_remove;
636 mpc8xxx_spi->max_bits_per_word = 32;
637 mpc8xxx_spi->type = fsl_spi_get_type(dev);
639 ret = fsl_spi_cpm_init(mpc8xxx_spi);
643 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
644 if (mpc8xxx_spi->reg_base == NULL) {
649 if (mpc8xxx_spi->type == TYPE_GRLIB)
650 fsl_spi_grlib_probe(dev);
652 master->bits_per_word_mask =
653 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
654 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
656 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
657 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
659 if (mpc8xxx_spi->set_shifts)
660 /* 8 bits per word and MSB first */
661 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
662 &mpc8xxx_spi->tx_shift, 8, 1);
664 /* Register for SPI Interrupt */
665 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
666 0, "fsl_spi", mpc8xxx_spi);
671 reg_base = mpc8xxx_spi->reg_base;
673 /* SPI controller initializations */
674 mpc8xxx_spi_write_reg(®_base->mode, 0);
675 mpc8xxx_spi_write_reg(®_base->mask, 0);
676 mpc8xxx_spi_write_reg(®_base->command, 0);
677 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
679 /* Enable SPI interface */
680 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
681 if (mpc8xxx_spi->max_bits_per_word < 8) {
682 regval &= ~SPMODE_LEN(0xF);
683 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
685 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
688 mpc8xxx_spi_write_reg(®_base->mode, regval);
690 ret = spi_register_master(master);
694 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
695 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
700 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
702 iounmap(mpc8xxx_spi->reg_base);
704 fsl_spi_cpm_free(mpc8xxx_spi);
706 spi_master_put(master);
711 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
713 struct device *dev = spi->dev.parent->parent;
714 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
715 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
716 u16 cs = spi->chip_select;
717 int gpio = pinfo->gpios[cs];
718 bool alow = pinfo->alow_flags[cs];
720 gpio_set_value(gpio, on ^ alow);
723 static int of_fsl_spi_get_chipselects(struct device *dev)
725 struct device_node *np = dev->of_node;
726 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
727 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
732 ngpios = of_gpio_count(np);
735 * SPI w/o chip-select line. One SPI device is still permitted
738 pdata->max_chipselect = 1;
742 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
745 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
747 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
749 if (!pinfo->alow_flags) {
751 goto err_alloc_flags;
754 for (; i < ngpios; i++) {
756 enum of_gpio_flags flags;
758 gpio = of_get_gpio_flags(np, i, &flags);
759 if (!gpio_is_valid(gpio)) {
760 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
765 ret = gpio_request(gpio, dev_name(dev));
767 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
771 pinfo->gpios[i] = gpio;
772 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
774 ret = gpio_direction_output(pinfo->gpios[i],
775 pinfo->alow_flags[i]);
777 dev_err(dev, "can't set output direction for gpio "
778 "#%d: %d\n", i, ret);
783 pdata->max_chipselect = ngpios;
784 pdata->cs_control = fsl_spi_cs_control;
790 if (gpio_is_valid(pinfo->gpios[i]))
791 gpio_free(pinfo->gpios[i]);
795 kfree(pinfo->alow_flags);
796 pinfo->alow_flags = NULL;
803 static int of_fsl_spi_free_chipselects(struct device *dev)
805 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
806 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
812 for (i = 0; i < pdata->max_chipselect; i++) {
813 if (gpio_is_valid(pinfo->gpios[i]))
814 gpio_free(pinfo->gpios[i]);
818 kfree(pinfo->alow_flags);
822 static int of_fsl_spi_probe(struct platform_device *ofdev)
824 struct device *dev = &ofdev->dev;
825 struct device_node *np = ofdev->dev.of_node;
826 struct spi_master *master;
831 ret = of_mpc8xxx_spi_probe(ofdev);
835 type = fsl_spi_get_type(&ofdev->dev);
836 if (type == TYPE_FSL) {
837 ret = of_fsl_spi_get_chipselects(dev);
842 ret = of_address_to_resource(np, 0, &mem);
846 irq = irq_of_parse_and_map(np, 0);
852 master = fsl_spi_probe(dev, &mem, irq);
853 if (IS_ERR(master)) {
854 ret = PTR_ERR(master);
861 if (type == TYPE_FSL)
862 of_fsl_spi_free_chipselects(dev);
866 static int of_fsl_spi_remove(struct platform_device *ofdev)
868 struct spi_master *master = platform_get_drvdata(ofdev);
869 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
872 ret = mpc8xxx_spi_remove(&ofdev->dev);
875 if (mpc8xxx_spi->type == TYPE_FSL)
876 of_fsl_spi_free_chipselects(&ofdev->dev);
880 static struct platform_driver of_fsl_spi_driver = {
883 .owner = THIS_MODULE,
884 .of_match_table = of_fsl_spi_match,
886 .probe = of_fsl_spi_probe,
887 .remove = of_fsl_spi_remove,
890 #ifdef CONFIG_MPC832x_RDB
893 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
894 * only. The driver should go away soon, since newer MPC8323E-RDB's device
895 * tree can work with OpenFirmware driver. But for now we support old trees
898 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
900 struct resource *mem;
902 struct spi_master *master;
904 if (!dev_get_platdata(&pdev->dev))
907 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911 irq = platform_get_irq(pdev, 0);
915 master = fsl_spi_probe(&pdev->dev, mem, irq);
916 return PTR_ERR_OR_ZERO(master);
919 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
921 return mpc8xxx_spi_remove(&pdev->dev);
924 MODULE_ALIAS("platform:mpc8xxx_spi");
925 static struct platform_driver mpc8xxx_spi_driver = {
926 .probe = plat_mpc8xxx_spi_probe,
927 .remove = plat_mpc8xxx_spi_remove,
929 .name = "mpc8xxx_spi",
930 .owner = THIS_MODULE,
934 static bool legacy_driver_failed;
936 static void __init legacy_driver_register(void)
938 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
941 static void __exit legacy_driver_unregister(void)
943 if (legacy_driver_failed)
945 platform_driver_unregister(&mpc8xxx_spi_driver);
948 static void __init legacy_driver_register(void) {}
949 static void __exit legacy_driver_unregister(void) {}
950 #endif /* CONFIG_MPC832x_RDB */
952 static int __init fsl_spi_init(void)
954 legacy_driver_register();
955 return platform_driver_register(&of_fsl_spi_driver);
957 module_init(fsl_spi_init);
959 static void __exit fsl_spi_exit(void)
961 platform_driver_unregister(&of_fsl_spi_driver);
962 legacy_driver_unregister();
964 module_exit(fsl_spi_exit);
966 MODULE_AUTHOR("Kumar Gala");
967 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
968 MODULE_LICENSE("GPL");