drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/highmem.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27
  28 #include "spi-dw.h"
  29
  30 #ifdef CONFIG_DEBUG_FS
  31 #include <linux/debugfs.h>
  32 #endif
  33
  34 #define START_STATE     ((void *)0)
  35 #define RUNNING_STATE   ((void *)1)
  36 #define DONE_STATE      ((void *)2)
  37 #define ERROR_STATE     ((void *)-1)
  38
  39 #define QUEUE_RUNNING   0
  40 #define QUEUE_STOPPED   1
  41
  42 #define MRST_SPI_DEASSERT       0
  43 #define MRST_SPI_ASSERT         1
  44
  45 /* Slave spi_dev related */
  46 struct chip_data {
  47         u16 cr0;
  48         u8 cs;                  /* chip select pin */
  49         u8 n_bytes;             /* current is a 1/2/4 byte op */
  50         u8 tmode;               /* TR/TO/RO/EEPROM */
  51         u8 type;                /* SPI/SSP/MicroWire */
  52
  53         u8 poll_mode;           /* 1 means use poll mode */
  54
  55         u32 dma_width;
  56         u32 rx_threshold;
  57         u32 tx_threshold;
  58         u8 enable_dma;
  59         u8 bits_per_word;
  60         u16 clk_div;            /* baud rate divider */
  61         u32 speed_hz;           /* baud rate */
  62         void (*cs_control)(u32 command);
  63 };
  64
  65 #ifdef CONFIG_DEBUG_FS
  66 #define SPI_REGS_BUFSIZE        1024
  67 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  68                                 size_t count, loff_t *ppos)
  69 {
  70         struct dw_spi *dws;
  71         char *buf;
  72         u32 len = 0;
  73         ssize_t ret;
  74
  75         dws = file->private_data;
  76
  77         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  78         if (!buf)
  79                 return 0;
  80
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "MRST SPI0 registers:\n");
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "=================================\n");
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  97         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  99         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
 101         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 102                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
 103         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 104                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
 105         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 106                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
 107         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 108                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
 109         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 110                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
 111         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 112                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
 113         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 114                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
 115         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 116                         "=================================\n");
 117
 118         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 119         kfree(buf);
 120         return ret;
 121 }
 122
 123 static const struct file_operations mrst_spi_regs_ops = {
 124         .owner          = THIS_MODULE,
 125         .open           = simple_open,
 126         .read           = spi_show_regs,
 127         .llseek         = default_llseek,
 128 };
 129
 130 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 131 {
 132         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 133         if (!dws->debugfs)
 134                 return -ENOMEM;
 135
 136         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 137                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 138         return 0;
 139 }
 140
 141 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 142 {
 143         if (dws->debugfs)
 144                 debugfs_remove_recursive(dws->debugfs);
 145 }
 146
 147 #else
 148 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 149 {
 150         return 0;
 151 }
 152
 153 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 154 {
 155 }
 156 #endif /* CONFIG_DEBUG_FS */
 157
 158 /* Return the max entries we can fill into tx fifo */
 159 static inline u32 tx_max(struct dw_spi *dws)
 160 {
 161         u32 tx_left, tx_room, rxtx_gap;
 162
 163         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 164         tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
 165
 166         /*
 167          * Another concern is about the tx/rx mismatch, we
 168          * though to use (dws->fifo_len - rxflr - txflr) as
 169          * one maximum value for tx, but it doesn't cover the
 170          * data which is out of tx/rx fifo and inside the
 171          * shift registers. So a control from sw point of
 172          * view is taken.
 173          */
 174         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 175                         / dws->n_bytes;
 176
 177         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 178 }
 179
 180 /* Return the max entries we should read out of rx fifo */
 181 static inline u32 rx_max(struct dw_spi *dws)
 182 {
 183         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 184
 185         return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
 186 }
 187
 188 static void dw_writer(struct dw_spi *dws)
 189 {
 190         u32 max = tx_max(dws);
 191         u16 txw = 0;
 192
 193         while (max--) {
 194                 /* Set the tx word if the transfer's original "tx" is not null */
 195                 if (dws->tx_end - dws->len) {
 196                         if (dws->n_bytes == 1)
 197                                 txw = *(u8 *)(dws->tx);
 198                         else
 199                                 txw = *(u16 *)(dws->tx);
 200                 }
 201                 dw_writew(dws, DW_SPI_DR, txw);
 202                 dws->tx += dws->n_bytes;
 203         }
 204 }
 205
 206 static void dw_reader(struct dw_spi *dws)
 207 {
 208         u32 max = rx_max(dws);
 209         u16 rxw;
 210
 211         while (max--) {
 212                 rxw = dw_readw(dws, DW_SPI_DR);
 213                 /* Care rx only if the transfer's original "rx" is not null */
 214                 if (dws->rx_end - dws->len) {
 215                         if (dws->n_bytes == 1)
 216                                 *(u8 *)(dws->rx) = rxw;
 217                         else
 218                                 *(u16 *)(dws->rx) = rxw;
 219                 }
 220                 dws->rx += dws->n_bytes;
 221         }
 222 }
 223
 224 static void *next_transfer(struct dw_spi *dws)
 225 {
 226         struct spi_message *msg = dws->cur_msg;
 227         struct spi_transfer *trans = dws->cur_transfer;
 228
 229         /* Move to next transfer */
 230         if (trans->transfer_list.next != &msg->transfers) {
 231                 dws->cur_transfer =
 232                         list_entry(trans->transfer_list.next,
 233                                         struct spi_transfer,
 234                                         transfer_list);
 235                 return RUNNING_STATE;
 236         } else
 237                 return DONE_STATE;
 238 }
 239
 240 /*
 241  * Note: first step is the protocol driver prepares
 242  * a dma-capable memory, and this func just need translate
 243  * the virt addr to physical
 244  */
 245 static int map_dma_buffers(struct dw_spi *dws)
 246 {
 247         if (!dws->cur_msg->is_dma_mapped
 248                 || !dws->dma_inited
 249                 || !dws->cur_chip->enable_dma
 250                 || !dws->dma_ops)
 251                 return 0;
 252
 253         if (dws->cur_transfer->tx_dma)
 254                 dws->tx_dma = dws->cur_transfer->tx_dma;
 255
 256         if (dws->cur_transfer->rx_dma)
 257                 dws->rx_dma = dws->cur_transfer->rx_dma;
 258
 259         return 1;
 260 }
 261
 262 /* Caller already set message->status; dma and pio irqs are blocked */
 263 static void giveback(struct dw_spi *dws)
 264 {
 265         struct spi_transfer *last_transfer;
 266         unsigned long flags;
 267         struct spi_message *msg;
 268
 269         spin_lock_irqsave(&dws->lock, flags);
 270         msg = dws->cur_msg;
 271         dws->cur_msg = NULL;
 272         dws->cur_transfer = NULL;
 273         dws->prev_chip = dws->cur_chip;
 274         dws->cur_chip = NULL;
 275         dws->dma_mapped = 0;
 276         queue_work(dws->workqueue, &dws->pump_messages);
 277         spin_unlock_irqrestore(&dws->lock, flags);
 278
 279         last_transfer = list_entry(msg->transfers.prev,
 280                                         struct spi_transfer,
 281                                         transfer_list);
 282
 283         if (!last_transfer->cs_change && dws->cs_control)
 284                 dws->cs_control(MRST_SPI_DEASSERT);
 285
 286         msg->state = NULL;
 287         if (msg->complete)
 288                 msg->complete(msg->context);
 289 }
 290
 291 static void int_error_stop(struct dw_spi *dws, const char *msg)
 292 {
 293         /* Stop the hw */
 294         spi_enable_chip(dws, 0);
 295
 296         dev_err(&dws->master->dev, "%s\n", msg);
 297         dws->cur_msg->state = ERROR_STATE;
 298         tasklet_schedule(&dws->pump_transfers);
 299 }
 300
 301 void dw_spi_xfer_done(struct dw_spi *dws)
 302 {
 303         /* Update total byte transferred return count actual bytes read */
 304         dws->cur_msg->actual_length += dws->len;
 305
 306         /* Move to next transfer */
 307         dws->cur_msg->state = next_transfer(dws);
 308
 309         /* Handle end of message */
 310         if (dws->cur_msg->state == DONE_STATE) {
 311                 dws->cur_msg->status = 0;
 312                 giveback(dws);
 313         } else
 314                 tasklet_schedule(&dws->pump_transfers);
 315 }
 316 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 317
 318 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 319 {
 320         u16 irq_status = dw_readw(dws, DW_SPI_ISR);
 321
 322         /* Error handling */
 323         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 324                 dw_readw(dws, DW_SPI_TXOICR);
 325                 dw_readw(dws, DW_SPI_RXOICR);
 326                 dw_readw(dws, DW_SPI_RXUICR);
 327                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 328                 return IRQ_HANDLED;
 329         }
 330
 331         dw_reader(dws);
 332         if (dws->rx_end == dws->rx) {
 333                 spi_mask_intr(dws, SPI_INT_TXEI);
 334                 dw_spi_xfer_done(dws);
 335                 return IRQ_HANDLED;
 336         }
 337         if (irq_status & SPI_INT_TXEI) {
 338                 spi_mask_intr(dws, SPI_INT_TXEI);
 339                 dw_writer(dws);
 340                 /* Enable TX irq always, it will be disabled when RX finished */
 341                 spi_umask_intr(dws, SPI_INT_TXEI);
 342         }
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 348 {
 349         struct dw_spi *dws = dev_id;
 350         u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
 351
 352         if (!irq_status)
 353                 return IRQ_NONE;
 354
 355         if (!dws->cur_msg) {
 356                 spi_mask_intr(dws, SPI_INT_TXEI);
 357                 return IRQ_HANDLED;
 358         }
 359
 360         return dws->transfer_handler(dws);
 361 }
 362
 363 /* Must be called inside pump_transfers() */
 364 static void poll_transfer(struct dw_spi *dws)
 365 {
 366         do {
 367                 dw_writer(dws);
 368                 dw_reader(dws);
 369                 cpu_relax();
 370         } while (dws->rx_end > dws->rx);
 371
 372         dw_spi_xfer_done(dws);
 373 }
 374
 375 static void pump_transfers(unsigned long data)
 376 {
 377         struct dw_spi *dws = (struct dw_spi *)data;
 378         struct spi_message *message = NULL;
 379         struct spi_transfer *transfer = NULL;
 380         struct spi_transfer *previous = NULL;
 381         struct spi_device *spi = NULL;
 382         struct chip_data *chip = NULL;
 383         u8 bits = 0;
 384         u8 imask = 0;
 385         u8 cs_change = 0;
 386         u16 txint_level = 0;
 387         u16 clk_div = 0;
 388         u32 speed = 0;
 389         u32 cr0 = 0;
 390
 391         /* Get current state information */
 392         message = dws->cur_msg;
 393         transfer = dws->cur_transfer;
 394         chip = dws->cur_chip;
 395         spi = message->spi;
 396
 397         if (message->state == ERROR_STATE) {
 398                 message->status = -EIO;
 399                 goto early_exit;
 400         }
 401
 402         /* Handle end of message */
 403         if (message->state == DONE_STATE) {
 404                 message->status = 0;
 405                 goto early_exit;
 406         }
 407
 408         /* Delay if requested at end of transfer*/
 409         if (message->state == RUNNING_STATE) {
 410                 previous = list_entry(transfer->transfer_list.prev,
 411                                         struct spi_transfer,
 412                                         transfer_list);
 413                 if (previous->delay_usecs)
 414                         udelay(previous->delay_usecs);
 415         }
 416
 417         dws->n_bytes = chip->n_bytes;
 418         dws->dma_width = chip->dma_width;
 419         dws->cs_control = chip->cs_control;
 420
 421         dws->rx_dma = transfer->rx_dma;
 422         dws->tx_dma = transfer->tx_dma;
 423         dws->tx = (void *)transfer->tx_buf;
 424         dws->tx_end = dws->tx + transfer->len;
 425         dws->rx = transfer->rx_buf;
 426         dws->rx_end = dws->rx + transfer->len;
 427         dws->cs_change = transfer->cs_change;
 428         dws->len = dws->cur_transfer->len;
 429         if (chip != dws->prev_chip)
 430                 cs_change = 1;
 431
 432         cr0 = chip->cr0;
 433
 434         /* Handle per transfer options for bpw and speed */
 435         if (transfer->speed_hz) {
 436                 speed = chip->speed_hz;
 437
 438                 if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
 439                         speed = transfer->speed_hz;
 440                         if (speed > dws->max_freq) {
 441                                 printk(KERN_ERR "MRST SPI0: unsupported"
 442                                         "freq: %dHz\n", speed);
 443                                 message->status = -EIO;
 444                                 goto early_exit;
 445                         }
 446
 447                         /* clk_div doesn't support odd number */
 448                         clk_div = dws->max_freq / speed;
 449                         clk_div = (clk_div + 1) & 0xfffe;
 450
 451                         chip->speed_hz = speed;
 452                         chip->clk_div = clk_div;
 453                 }
 454         }
 455         if (transfer->bits_per_word) {
 456                 bits = transfer->bits_per_word;
 457
 458                 switch (bits) {
 459                 case 8:
 460                 case 16:
 461                         dws->n_bytes = dws->dma_width = bits >> 3;
 462                         break;
 463                 default:
 464                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 465                                 "%db\n", bits);
 466                         message->status = -EIO;
 467                         goto early_exit;
 468                 }
 469
 470                 cr0 = (bits - 1)
 471                         | (chip->type << SPI_FRF_OFFSET)
 472                         | (spi->mode << SPI_MODE_OFFSET)
 473                         | (chip->tmode << SPI_TMOD_OFFSET);
 474         }
 475         message->state = RUNNING_STATE;
 476
 477         /*
 478          * Adjust transfer mode if necessary. Requires platform dependent
 479          * chipselect mechanism.
 480          */
 481         if (dws->cs_control) {
 482                 if (dws->rx && dws->tx)
 483                         chip->tmode = SPI_TMOD_TR;
 484                 else if (dws->rx)
 485                         chip->tmode = SPI_TMOD_RO;
 486                 else
 487                         chip->tmode = SPI_TMOD_TO;
 488
 489                 cr0 &= ~SPI_TMOD_MASK;
 490                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 491         }
 492
 493         /* Check if current transfer is a DMA transaction */
 494         dws->dma_mapped = map_dma_buffers(dws);
 495
 496         /*
 497          * Interrupt mode
 498          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 499          */
 500         if (!dws->dma_mapped && !chip->poll_mode) {
 501                 int templen = dws->len / dws->n_bytes;
 502                 txint_level = dws->fifo_len / 2;
 503                 txint_level = (templen > txint_level) ? txint_level : templen;
 504
 505                 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
 506                 dws->transfer_handler = interrupt_transfer;
 507         }
 508
 509         /*
 510          * Reprogram registers only if
 511          *      1. chip select changes
 512          *      2. clk_div is changed
 513          *      3. control value changes
 514          */
 515         if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
 516                 spi_enable_chip(dws, 0);
 517
 518                 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
 519                         dw_writew(dws, DW_SPI_CTRL0, cr0);
 520
 521                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 522                 spi_chip_sel(dws, spi->chip_select);
 523
 524                 /* Set the interrupt mask, for poll mode just disable all int */
 525                 spi_mask_intr(dws, 0xff);
 526                 if (imask)
 527                         spi_umask_intr(dws, imask);
 528                 if (txint_level)
 529                         dw_writew(dws, DW_SPI_TXFLTR, txint_level);
 530
 531                 spi_enable_chip(dws, 1);
 532                 if (cs_change)
 533                         dws->prev_chip = chip;
 534         }
 535
 536         if (dws->dma_mapped)
 537                 dws->dma_ops->dma_transfer(dws, cs_change);
 538
 539         if (chip->poll_mode)
 540                 poll_transfer(dws);
 541
 542         return;
 543
 544 early_exit:
 545         giveback(dws);
 546         return;
 547 }
 548
 549 static void pump_messages(struct work_struct *work)
 550 {
 551         struct dw_spi *dws =
 552                 container_of(work, struct dw_spi, pump_messages);
 553         unsigned long flags;
 554
 555         /* Lock queue and check for queue work */
 556         spin_lock_irqsave(&dws->lock, flags);
 557         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 558                 dws->busy = 0;
 559                 spin_unlock_irqrestore(&dws->lock, flags);
 560                 return;
 561         }
 562
 563         /* Make sure we are not already running a message */
 564         if (dws->cur_msg) {
 565                 spin_unlock_irqrestore(&dws->lock, flags);
 566                 return;
 567         }
 568
 569         /* Extract head of queue */
 570         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 571         list_del_init(&dws->cur_msg->queue);
 572
 573         /* Initial message state*/
 574         dws->cur_msg->state = START_STATE;
 575         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 576                                                 struct spi_transfer,
 577                                                 transfer_list);
 578         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 579
 580         /* Mark as busy and launch transfers */
 581         tasklet_schedule(&dws->pump_transfers);
 582
 583         dws->busy = 1;
 584         spin_unlock_irqrestore(&dws->lock, flags);
 585 }
 586
 587 /* spi_device use this to queue in their spi_msg */
 588 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 589 {
 590         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 591         unsigned long flags;
 592
 593         spin_lock_irqsave(&dws->lock, flags);
 594
 595         if (dws->run == QUEUE_STOPPED) {
 596                 spin_unlock_irqrestore(&dws->lock, flags);
 597                 return -ESHUTDOWN;
 598         }
 599
 600         msg->actual_length = 0;
 601         msg->status = -EINPROGRESS;
 602         msg->state = START_STATE;
 603
 604         list_add_tail(&msg->queue, &dws->queue);
 605
 606         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 607
 608                 if (dws->cur_transfer || dws->cur_msg)
 609                         queue_work(dws->workqueue,
 610                                         &dws->pump_messages);
 611                 else {
 612                         /* If no other data transaction in air, just go */
 613                         spin_unlock_irqrestore(&dws->lock, flags);
 614                         pump_messages(&dws->pump_messages);
 615                         return 0;
 616                 }
 617         }
 618
 619         spin_unlock_irqrestore(&dws->lock, flags);
 620         return 0;
 621 }
 622
 623 /* This may be called twice for each spi dev */
 624 static int dw_spi_setup(struct spi_device *spi)
 625 {
 626         struct dw_spi_chip *chip_info = NULL;
 627         struct chip_data *chip;
 628
 629         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 630                 return -EINVAL;
 631
 632         /* Only alloc on first setup */
 633         chip = spi_get_ctldata(spi);
 634         if (!chip) {
 635                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 636                 if (!chip)
 637                         return -ENOMEM;
 638         }
 639
 640         /*
 641          * Protocol drivers may change the chip settings, so...
 642          * if chip_info exists, use it
 643          */
 644         chip_info = spi->controller_data;
 645
 646         /* chip_info doesn't always exist */
 647         if (chip_info) {
 648                 if (chip_info->cs_control)
 649                         chip->cs_control = chip_info->cs_control;
 650
 651                 chip->poll_mode = chip_info->poll_mode;
 652                 chip->type = chip_info->type;
 653
 654                 chip->rx_threshold = 0;
 655                 chip->tx_threshold = 0;
 656
 657                 chip->enable_dma = chip_info->enable_dma;
 658         }
 659
 660         if (spi->bits_per_word <= 8) {
 661                 chip->n_bytes = 1;
 662                 chip->dma_width = 1;
 663         } else if (spi->bits_per_word <= 16) {
 664                 chip->n_bytes = 2;
 665                 chip->dma_width = 2;
 666         } else {
 667                 /* Never take >16b case for MRST SPIC */
 668                 dev_err(&spi->dev, "invalid wordsize\n");
 669                 return -EINVAL;
 670         }
 671         chip->bits_per_word = spi->bits_per_word;
 672
 673         if (!spi->max_speed_hz) {
 674                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 675                 return -EINVAL;
 676         }
 677
 678         chip->tmode = 0; /* Tx & Rx */
 679         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 680         chip->cr0 = (chip->bits_per_word - 1)
 681                         | (chip->type << SPI_FRF_OFFSET)
 682                         | (spi->mode  << SPI_MODE_OFFSET)
 683                         | (chip->tmode << SPI_TMOD_OFFSET);
 684
 685         spi_set_ctldata(spi, chip);
 686         return 0;
 687 }
 688
 689 static void dw_spi_cleanup(struct spi_device *spi)
 690 {
 691         struct chip_data *chip = spi_get_ctldata(spi);
 692         kfree(chip);
 693 }
 694
 695 static int init_queue(struct dw_spi *dws)
 696 {
 697         INIT_LIST_HEAD(&dws->queue);
 698         spin_lock_init(&dws->lock);
 699
 700         dws->run = QUEUE_STOPPED;
 701         dws->busy = 0;
 702
 703         tasklet_init(&dws->pump_transfers,
 704                         pump_transfers, (unsigned long)dws);
 705
 706         INIT_WORK(&dws->pump_messages, pump_messages);
 707         dws->workqueue = create_singlethread_workqueue(
 708                                         dev_name(dws->master->dev.parent));
 709         if (dws->workqueue == NULL)
 710                 return -EBUSY;
 711
 712         return 0;
 713 }
 714
 715 static int start_queue(struct dw_spi *dws)
 716 {
 717         unsigned long flags;
 718
 719         spin_lock_irqsave(&dws->lock, flags);
 720
 721         if (dws->run == QUEUE_RUNNING || dws->busy) {
 722                 spin_unlock_irqrestore(&dws->lock, flags);
 723                 return -EBUSY;
 724         }
 725
 726         dws->run = QUEUE_RUNNING;
 727         dws->cur_msg = NULL;
 728         dws->cur_transfer = NULL;
 729         dws->cur_chip = NULL;
 730         dws->prev_chip = NULL;
 731         spin_unlock_irqrestore(&dws->lock, flags);
 732
 733         queue_work(dws->workqueue, &dws->pump_messages);
 734
 735         return 0;
 736 }
 737
 738 static int stop_queue(struct dw_spi *dws)
 739 {
 740         unsigned long flags;
 741         unsigned limit = 50;
 742         int status = 0;
 743
 744         spin_lock_irqsave(&dws->lock, flags);
 745         dws->run = QUEUE_STOPPED;
 746         while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
 747                 spin_unlock_irqrestore(&dws->lock, flags);
 748                 msleep(10);
 749                 spin_lock_irqsave(&dws->lock, flags);
 750         }
 751
 752         if (!list_empty(&dws->queue) || dws->busy)
 753                 status = -EBUSY;
 754         spin_unlock_irqrestore(&dws->lock, flags);
 755
 756         return status;
 757 }
 758
 759 static int destroy_queue(struct dw_spi *dws)
 760 {
 761         int status;
 762
 763         status = stop_queue(dws);
 764         if (status != 0)
 765                 return status;
 766         destroy_workqueue(dws->workqueue);
 767         return 0;
 768 }
 769
 770 /* Restart the controller, disable all interrupts, clean rx fifo */
 771 static void spi_hw_init(struct dw_spi *dws)
 772 {
 773         spi_enable_chip(dws, 0);
 774         spi_mask_intr(dws, 0xff);
 775         spi_enable_chip(dws, 1);
 776
 777         /*
 778          * Try to detect the FIFO depth if not set by interface driver,
 779          * the depth could be from 2 to 256 from HW spec
 780          */
 781         if (!dws->fifo_len) {
 782                 u32 fifo;
 783                 for (fifo = 2; fifo <= 257; fifo++) {
 784                         dw_writew(dws, DW_SPI_TXFLTR, fifo);
 785                         if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
 786                                 break;
 787                 }
 788
 789                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 790                 dw_writew(dws, DW_SPI_TXFLTR, 0);
 791         }
 792 }
 793
 794 int dw_spi_add_host(struct dw_spi *dws)
 795 {
 796         struct spi_master *master;
 797         int ret;
 798
 799         BUG_ON(dws == NULL);
 800
 801         master = spi_alloc_master(dws->parent_dev, 0);
 802         if (!master) {
 803                 ret = -ENOMEM;
 804                 goto exit;
 805         }
 806
 807         dws->master = master;
 808         dws->type = SSI_MOTO_SPI;
 809         dws->prev_chip = NULL;
 810         dws->dma_inited = 0;
 811         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 812         snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
 813                         dws->bus_num);
 814
 815         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 816                         dws->name, dws);
 817         if (ret < 0) {
 818                 dev_err(&master->dev, "can not get IRQ\n");
 819                 goto err_free_master;
 820         }
 821
 822         master->mode_bits = SPI_CPOL | SPI_CPHA;
 823         master->bus_num = dws->bus_num;
 824         master->num_chipselect = dws->num_cs;
 825         master->cleanup = dw_spi_cleanup;
 826         master->setup = dw_spi_setup;
 827         master->transfer = dw_spi_transfer;
 828
 829         /* Basic HW init */
 830         spi_hw_init(dws);
 831
 832         if (dws->dma_ops && dws->dma_ops->dma_init) {
 833                 ret = dws->dma_ops->dma_init(dws);
 834                 if (ret) {
 835                         dev_warn(&master->dev, "DMA init failed\n");
 836                         dws->dma_inited = 0;
 837                 }
 838         }
 839
 840         /* Initial and start queue */
 841         ret = init_queue(dws);
 842         if (ret) {
 843                 dev_err(&master->dev, "problem initializing queue\n");
 844                 goto err_diable_hw;
 845         }
 846         ret = start_queue(dws);
 847         if (ret) {
 848                 dev_err(&master->dev, "problem starting queue\n");
 849                 goto err_diable_hw;
 850         }
 851
 852         spi_master_set_devdata(master, dws);
 853         ret = spi_register_master(master);
 854         if (ret) {
 855                 dev_err(&master->dev, "problem registering spi master\n");
 856                 goto err_queue_alloc;
 857         }
 858
 859         mrst_spi_debugfs_init(dws);
 860         return 0;
 861
 862 err_queue_alloc:
 863         destroy_queue(dws);
 864         if (dws->dma_ops && dws->dma_ops->dma_exit)
 865                 dws->dma_ops->dma_exit(dws);
 866 err_diable_hw:
 867         spi_enable_chip(dws, 0);
 868         free_irq(dws->irq, dws);
 869 err_free_master:
 870         spi_master_put(master);
 871 exit:
 872         return ret;
 873 }
 874 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 875
 876 void dw_spi_remove_host(struct dw_spi *dws)
 877 {
 878         int status = 0;
 879
 880         if (!dws)
 881                 return;
 882         mrst_spi_debugfs_remove(dws);
 883
 884         /* Remove the queue */
 885         status = destroy_queue(dws);
 886         if (status != 0)
 887                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 888                         "complete, message memory not freed\n");
 889
 890         if (dws->dma_ops && dws->dma_ops->dma_exit)
 891                 dws->dma_ops->dma_exit(dws);
 892         spi_enable_chip(dws, 0);
 893         /* Disable clk */
 894         spi_set_clk(dws, 0);
 895         free_irq(dws->irq, dws);
 896
 897         /* Disconnect from the SPI framework */
 898         spi_unregister_master(dws->master);
 899 }
 900 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 901
 902 int dw_spi_suspend_host(struct dw_spi *dws)
 903 {
 904         int ret = 0;
 905
 906         ret = stop_queue(dws);
 907         if (ret)
 908                 return ret;
 909         spi_enable_chip(dws, 0);
 910         spi_set_clk(dws, 0);
 911         return ret;
 912 }
 913 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 914
 915 int dw_spi_resume_host(struct dw_spi *dws)
 916 {
 917         int ret;
 918
 919         spi_hw_init(dws);
 920         ret = start_queue(dws);
 921         if (ret)
 922                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 923         return ret;
 924 }
 925 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 926
 927 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 928 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 929 MODULE_LICENSE("GPL v2");