drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/slab.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/types.h>
  26
  27 #include "spi-dw.h"
  28
  29 #ifdef CONFIG_SPI_DW_MID_DMA
  30 #include <linux/intel_mid_dma.h>
  31 #include <linux/pci.h>
  32
  33 struct mid_dma {
  34         struct intel_mid_dma_slave      dmas_tx;
  35         struct intel_mid_dma_slave      dmas_rx;
  36 };
  37
  38 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  39 {
  40         struct dw_spi *dws = param;
  41
  42         return dws->dmac && (&dws->dmac->dev == chan->device->dev);
  43 }
  44
  45 static int mid_spi_dma_init(struct dw_spi *dws)
  46 {
  47         struct mid_dma *dw_dma = dws->dma_priv;
  48         struct intel_mid_dma_slave *rxs, *txs;
  49         dma_cap_mask_t mask;
  50
  51         /*
  52          * Get pci device for DMA controller, currently it could only
  53          * be the DMA controller of either Moorestown or Medfield
  54          */
  55         dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
  56         if (!dws->dmac)
  57                 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  58
  59         dma_cap_zero(mask);
  60         dma_cap_set(DMA_SLAVE, mask);
  61
  62         /* 1. Init rx channel */
  63         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  64         if (!dws->rxchan)
  65                 goto err_exit;
  66         rxs = &dw_dma->dmas_rx;
  67         rxs->hs_mode = LNW_DMA_HW_HS;
  68         rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  69         dws->rxchan->private = rxs;
  70
  71         /* 2. Init tx channel */
  72         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  73         if (!dws->txchan)
  74                 goto free_rxchan;
  75         txs = &dw_dma->dmas_tx;
  76         txs->hs_mode = LNW_DMA_HW_HS;
  77         txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  78         dws->txchan->private = txs;
  79
  80         dws->dma_inited = 1;
  81         return 0;
  82
  83 free_rxchan:
  84         dma_release_channel(dws->rxchan);
  85 err_exit:
  86         return -1;
  87
  88 }
  89
  90 static void mid_spi_dma_exit(struct dw_spi *dws)
  91 {
  92         if (!dws->dma_inited)
  93                 return;
  94         dma_release_channel(dws->txchan);
  95         dma_release_channel(dws->rxchan);
  96 }
  97
  98 /*
  99  * dws->dma_chan_done is cleared before the dma transfer starts,
 100  * callback for rx/tx channel will each increment it by 1.
 101  * Reaching 2 means the whole spi transaction is done.
 102  */
 103 static void dw_spi_dma_done(void *arg)
 104 {
 105         struct dw_spi *dws = arg;
 106
 107         if (++dws->dma_chan_done != 2)
 108                 return;
 109         dw_spi_xfer_done(dws);
 110 }
 111
 112 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 113 {
 114         struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
 115         struct dma_chan *txchan, *rxchan;
 116         struct dma_slave_config txconf, rxconf;
 117         u16 dma_ctrl = 0;
 118
 119         /* 1. setup DMA related registers */
 120         if (cs_change) {
 121                 spi_enable_chip(dws, 0);
 122                 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
 123                 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 124                 if (dws->tx_dma)
 125                         dma_ctrl |= 0x2;
 126                 if (dws->rx_dma)
 127                         dma_ctrl |= 0x1;
 128                 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 129                 spi_enable_chip(dws, 1);
 130         }
 131
 132         dws->dma_chan_done = 0;
 133         txchan = dws->txchan;
 134         rxchan = dws->rxchan;
 135
 136         /* 2. Prepare the TX dma transfer */
 137         txconf.direction = DMA_MEM_TO_DEV;
 138         txconf.dst_addr = dws->dma_addr;
 139         txconf.dst_maxburst = LNW_DMA_MSIZE_16;
 140         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 141         txconf.dst_addr_width = dws->dma_width;
 142         txconf.device_fc = false;
 143
 144         txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
 145                                        (unsigned long) &txconf);
 146
 147         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 148         dws->tx_sgl.dma_address = dws->tx_dma;
 149         dws->tx_sgl.length = dws->len;
 150
 151         txdesc = dmaengine_prep_slave_sg(txchan,
 152                                 &dws->tx_sgl,
 153                                 1,
 154                                 DMA_MEM_TO_DEV,
 155                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 156         txdesc->callback = dw_spi_dma_done;
 157         txdesc->callback_param = dws;
 158
 159         /* 3. Prepare the RX dma transfer */
 160         rxconf.direction = DMA_DEV_TO_MEM;
 161         rxconf.src_addr = dws->dma_addr;
 162         rxconf.src_maxburst = LNW_DMA_MSIZE_16;
 163         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 164         rxconf.src_addr_width = dws->dma_width;
 165         rxconf.device_fc = false;
 166
 167         rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
 168                                        (unsigned long) &rxconf);
 169
 170         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 171         dws->rx_sgl.dma_address = dws->rx_dma;
 172         dws->rx_sgl.length = dws->len;
 173
 174         rxdesc = dmaengine_prep_slave_sg(rxchan,
 175                                 &dws->rx_sgl,
 176                                 1,
 177                                 DMA_DEV_TO_MEM,
 178                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 179         rxdesc->callback = dw_spi_dma_done;
 180         rxdesc->callback_param = dws;
 181
 182         /* rx must be started before tx due to spi instinct */
 183         rxdesc->tx_submit(rxdesc);
 184         txdesc->tx_submit(txdesc);
 185         return 0;
 186 }
 187
 188 static struct dw_spi_dma_ops mid_dma_ops = {
 189         .dma_init       = mid_spi_dma_init,
 190         .dma_exit       = mid_spi_dma_exit,
 191         .dma_transfer   = mid_spi_dma_transfer,
 192 };
 193 #endif
 194
 195 /* Some specific info for SPI0 controller on Moorestown */
 196
 197 /* HW info for MRST CLk Control Unit, one 32b reg */
 198 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 199 #define MRST_CLK_SPI0_REG       0xff11d86c
 200 #define CLK_SPI_BDIV_OFFSET     0
 201 #define CLK_SPI_BDIV_MASK       0x00000007
 202 #define CLK_SPI_CDIV_OFFSET     9
 203 #define CLK_SPI_CDIV_MASK       0x00000e00
 204 #define CLK_SPI_DISABLE_OFFSET  8
 205
 206 int dw_spi_mid_init(struct dw_spi *dws)
 207 {
 208         void __iomem *clk_reg;
 209         u32 clk_cdiv;
 210
 211         clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
 212         if (!clk_reg)
 213                 return -ENOMEM;
 214
 215         /* get SPI controller operating freq info */
 216         clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
 217         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 218         iounmap(clk_reg);
 219
 220         dws->num_cs = 16;
 221         dws->fifo_len = 40;     /* FIFO has 40 words buffer */
 222
 223 #ifdef CONFIG_SPI_DW_MID_DMA
 224         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
 225         if (!dws->dma_priv)
 226                 return -ENOMEM;
 227         dws->dma_ops = &mid_dma_ops;
 228 #endif
 229         return 0;
 230 }