1 /* drivers/spi/rk29xx_spim.h
\r
3 * Copyright (C) 2010 ROCKCHIP, Inc.
\r
5 * This software is licensed under the terms of the GNU General Public
\r
6 * License version 2, as published by the Free Software Foundation, and
\r
7 * may be copied, distributed, and modified under those terms.
\r
9 * This program is distributed in the hope that it will be useful,
\r
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
12 * GNU General Public License for more details.
\r
14 #ifndef __DRIVERS_SPIM_RK29XX_HEADER_H
\r
15 #define __DRIVERS_SPIM_RK29XX_HEADER_H
\r
16 #include <linux/io.h>
\r
17 #ifdef CONFIG_ARCH_RK30
\r
18 #include <plat/dma-pl330.h>
\r
20 #include <mach/dma-pl330.h>
\r
23 /* SPI register offsets */
\r
24 #define SPIM_CTRLR0 0x0000
\r
25 #define SPIM_CTRLR1 0x0004
\r
26 #define SPIM_ENR 0x0008
\r
27 #define SPIM_SER 0x000c
\r
28 #define SPIM_BAUDR 0x0010
\r
29 #define SPIM_TXFTLR 0x0014
\r
30 #define SPIM_RXFTLR 0x0018
\r
31 #define SPIM_TXFLR 0x001c
\r
32 #define SPIM_RXFLR 0x0020
\r
33 #define SPIM_SR 0x0024
\r
34 #define SPIM_IPR 0x0028
\r
35 #define SPIM_IMR 0x002c
\r
36 #define SPIM_ISR 0x0030
\r
37 #define SPIM_RISR 0x0034
\r
38 #define SPIM_ICR 0x0038
\r
39 #define SPIM_DMACR 0x003c
\r
40 #define SPIM_DMATDLR 0x0040
\r
41 #define SPIM_DMARDLR 0x0044
\r
42 #define SPIM_TXDR 0x0400
\r
43 #define SPIM_RXDR 0x0800
\r
45 /* --------Bit fields in CTRLR0--------begin */
\r
47 #define SPI_DFS_OFFSET 0 /* Data Frame Size */
\r
48 #define SPI_DFS_4BIT 0x00
\r
49 #define SPI_DFS_8BIT 0x01
\r
50 #define SPI_DFS_16BIT 0x02
\r
51 #define SPI_DFS_RESV 0x03
\r
53 #define SPI_FRF_OFFSET 16 /* Frame Format */
\r
54 #define SPI_FRF_SPI 0x00 /* motorola spi */
\r
55 #define SPI_FRF_SSP 0x01 /* Texas Instruments SSP*/
\r
56 #define SPI_FRF_MICROWIRE 0x02 /* National Semiconductors Microwire */
\r
57 #define SPI_FRF_RESV 0x03
\r
59 #define SPI_MODE_OFFSET 6 /* SCPH & SCOL */
\r
61 #define SPI_SCPH_OFFSET 6 /* Serial Clock Phase */
\r
62 #define SPI_SCPH_TOGMID 0 /* Serial clock toggles in middle of first data bit */
\r
63 #define SPI_SCPH_TOGSTA 1 /* Serial clock toggles at start of first data bit */
\r
65 #define SPI_SCOL_OFFSET 7 /* Serial Clock Polarity */
\r
67 #define SPI_OPMOD_OFFSET 20
\r
68 #define SPI_OPMOD_MASTER 0
\r
69 #define SPI_OPMOD_SLAVE 1
\r
71 #define SPI_TMOD_OFFSET 18 /* Transfer Mode */
\r
72 #define SPI_TMOD_TR 0x00 /* xmit & recv */
\r
73 #define SPI_TMOD_TO 0x01 /* xmit only */
\r
74 #define SPI_TMOD_RO 0x02 /* recv only */
\r
75 #define SPI_TMOD_RESV 0x03
\r
77 #define SPI_CFS_OFFSET 2 /* Control Frame Size */
\r
79 #define SPI_CSM_OFFSET 8 /* Chip Select Mode */
\r
80 #define SPI_CSM_KEEP 0x00 /* ss_n keep low after every frame data is transferred */
\r
81 #define SPI_CSM_HALF 0x01 /* ss_n be high for half sclk_out cycles after every frame data is transferred */
\r
82 #define SPI_CSM_ONE 0x02 /* ss_n be high for one sclk_out cycle after every frame data is transferred */
\r
84 #define SPI_SSN_DELAY_OFFSET 10
\r
85 #define SPI_SSN_DELAY_HALF 0x00
\r
86 #define SPI_SSN_DELAY_ONE 0x01
\r
88 #define SPI_HALF_WORLD_TX_OFFSET 13
\r
89 #define SPI_HALF_WORLD_ON 0x00
\r
90 #define SPI_HALF_WORLD_OFF 0x01
\r
93 /* --------Bit fields in CTRLR0--------end */
\r
96 /* Bit fields in SR, 7 bits */
\r
97 #define SR_MASK 0x7f /* cover 7 bits */
\r
98 #define SR_BUSY (1 << 0)
\r
99 #define SR_TF_FULL (1 << 1)
\r
100 #define SR_TF_EMPT (1 << 2)
\r
101 #define SR_RF_EMPT (1 << 3)
\r
102 #define SR_RF_FULL (1 << 4)
\r
104 /* Bit fields in ISR, IMR, RISR, 7 bits */
\r
105 #define SPI_INT_TXEI (1 << 0)
\r
106 #define SPI_INT_TXOI (1 << 1)
\r
107 #define SPI_INT_RXUI (1 << 2)
\r
108 #define SPI_INT_RXOI (1 << 3)
\r
109 #define SPI_INT_RXFI (1 << 4)
\r
111 /* Bit fields in DMACR */
\r
112 #define SPI_DMACR_TX_ENABLE (1 << 1)
\r
113 #define SPI_DMACR_RX_ENABLE (1 << 0)
\r
115 /* Bit fields in ICR */
\r
116 #define SPI_CLEAR_INT_ALL (1<< 0)
\r
117 #define SPI_CLEAR_INT_RXUI (1 << 1)
\r
118 #define SPI_CLEAR_INT_RXOI (1 << 2)
\r
119 #define SPI_CLEAR_INT_TXOI (1 << 3)
\r
121 enum rk29xx_ssi_type {
\r
127 struct rk29xx_spi {
\r
128 struct spi_master *master;
\r
129 struct spi_device *cur_dev;
\r
130 enum rk29xx_ssi_type type;
\r
132 void __iomem *regs;
\r
133 unsigned long paddr;
\r
137 u32 fifo_len; /* depth of the FIFO buffer */
\r
138 struct clk *clock_spim; /* clk apb */
\r
140 struct platform_device *pdev;
\r
142 /* Driver message queue */
\r
143 struct workqueue_struct *workqueue;
\r
144 struct work_struct pump_messages;
\r
146 struct mutex dma_lock;
\r
147 struct list_head queue;
\r
151 /* Message Transfer pump */
\r
152 struct tasklet_struct pump_transfers;
\r
153 struct tasklet_struct dma_transfers;
\r
155 /* Current message transfer state info */
\r
156 struct spi_message *cur_msg;
\r
157 struct spi_transfer *cur_transfer;
\r
158 struct chip_data *cur_chip;
\r
159 struct chip_data *prev_chip;
\r
168 void *buffer_tx_dma;
\r
169 void *buffer_rx_dma;
\r
172 u8 n_bytes; /* current is a 1/2 bytes op */
\r
173 u8 max_bits_per_word; /* maxim is 16b */
\r
176 int (*write)(struct rk29xx_spi *dws);
\r
177 int (*read)(struct rk29xx_spi *dws);
\r
178 irqreturn_t (*transfer_handler)(struct rk29xx_spi *dws);
\r
179 void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);
\r
182 struct completion xfer_completion;
\r
184 struct completion tx_completion;
\r
185 struct completion rx_completion;
\r
187 unsigned cur_speed;
\r
188 unsigned long sfr_start;
\r
190 enum dma_ch rx_dmach;
\r
191 enum dma_ch tx_dmach;
\r
196 struct device *dma_dev;
\r
197 dma_addr_t dma_addr;
\r
199 /* Bus interface info */
\r
201 #ifdef CONFIG_DEBUG_FS
\r
202 struct dentry *debugfs;
\r
204 #ifdef CONFIG_CPU_FREQ
\r
205 struct notifier_block freq_transition;
\r
209 #define rk29xx_readl(dw, off) \
\r
210 __raw_readl(dw->regs + off)
\r
211 #define rk29xx_writel(dw,off,val) \
\r
212 __raw_writel(val, dw->regs + off)
\r
213 #define rk29xx_readw(dw, off) \
\r
214 __raw_readw(dw->regs + off)
\r
215 #define rk29xx_writew(dw,off,val) \
\r
216 __raw_writel(val, dw->regs + off)
\r
218 static inline void spi_enable_chip(struct rk29xx_spi *dws, int enable)
\r
220 rk29xx_writel(dws, SPIM_ENR, (enable ? 1 : 0));
\r
223 static inline void spi_set_clk(struct rk29xx_spi *dws, u16 div)
\r
225 rk29xx_writel(dws, SPIM_BAUDR, div);
\r
228 /* Disable IRQ bits */
\r
229 static inline void spi_mask_intr(struct rk29xx_spi *dws, u32 mask)
\r
233 new_mask = rk29xx_readl(dws, SPIM_IMR) & ~mask;
\r
234 rk29xx_writel(dws, SPIM_IMR, new_mask);
\r
237 /* Enable IRQ bits */
\r
238 static inline void spi_umask_intr(struct rk29xx_spi *dws, u32 mask)
\r
242 new_mask = rk29xx_readl(dws, SPIM_IMR) | mask;
\r
243 rk29xx_writel(dws, SPIM_IMR, new_mask);
\r
246 //spi transfer mode add by lyx
\r
247 #define rk29xx_SPI_HALF_DUPLEX 0
\r
248 #define rk29xx_SPI_FULL_DUPLEX 1
\r
251 * Each SPI slave device to work with rk29xx spi controller should
\r
252 * has such a structure claiming its working mode (PIO/DMA etc),
\r
253 * which can be save in the "controller_data" member of the
\r
254 * struct spi_device
\r
256 struct rk29xx_spi_chip {
\r
257 u8 transfer_mode;/*full or half duplex*/
\r
258 u8 poll_mode; /* 0 for contoller polling mode */
\r
259 u8 type; /* SPI/SSP/Micrwire */
\r
262 void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);
\r
265 #endif /* __DRIVERS_SPIM_RK29XX_HEADER_H */
\r