drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 #if 0\r
  44 #define DBG   printk\r
  45 //#define PRINT_TRANS_DATA\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_BUFFER_SIZE PAGE_SIZE\r
  51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO\r
  52 \r
  53 \r
  54 #define START_STATE     ((void *)0)\r
  55 #define RUNNING_STATE   ((void *)1)\r
  56 #define DONE_STATE      ((void *)2)\r
  57 #define ERROR_STATE     ((void *)-1)\r
  58 \r
  59 #define QUEUE_RUNNING   0\r
  60 #define QUEUE_STOPPED   1\r
  61 \r
  62 #define MRST_SPI_DEASSERT       0\r
  63 #define MRST_SPI_ASSERT         1  ///CS0\r
  64 #define MRST_SPI_ASSERT1        2  ///CS1\r
  65 \r
  66 /* Slave spi_dev related */\r
  67 struct chip_data {\r
  68         u16 cr0;\r
  69         u8 cs;                  /* chip select pin */\r
  70         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  71         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  72         u8 mode;                /* ??? */\r
  73         u8 type;                /* SPI/SSP/MicroWire */\r
  74 \r
  75         u8 poll_mode;           /* 1 means use poll mode */\r
  76         u8 slave_enable;\r
  77         u32 dma_width;\r
  78         u32 rx_threshold;\r
  79         u32 tx_threshold;\r
  80         u8 enable_dma:1;\r
  81         u8 bits_per_word;\r
  82         u16 clk_div;            /* baud rate divider */\r
  83         u32 speed_hz;           /* baud rate */\r
  84         int (*write)(struct rk29xx_spi *dws);\r
  85         int (*read)(struct rk29xx_spi *dws);\r
  86         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  87 };\r
  88 \r
  89 #define SUSPND    (1<<0)\r
  90 #define SPIBUSY   (1<<1)\r
  91 #define RXBUSY    (1<<2)\r
  92 #define TXBUSY    (1<<3)\r
  93 \r
  94 //\r
  95 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  96 void rk29_lcd_spim_spin_lock(void)\r
  97 {\r
  98 #ifdef CONFIG_LCD_USE_SPI0\r
  99         disable_irq(IRQ_SPI0);\r
 100 #endif\r
 101 \r
 102 #ifdef CONFIG_LCD_USE_SPI1\r
 103         disable_irq(IRQ_SPI1);\r
 104 #endif\r
 105 \r
 106         preempt_disable();\r
 107 }\r
 108 \r
 109 void rk29_lcd_spim_spin_unlock(void)\r
 110 {\r
 111         preempt_enable();\r
 112         \r
 113 #ifdef CONFIG_LCD_USE_SPI0\r
 114         enable_irq(IRQ_SPI0);\r
 115 #endif\r
 116 \r
 117 #ifdef CONFIG_LCD_USE_SPI1\r
 118         enable_irq(IRQ_SPI1);\r
 119 #endif\r
 120 }\r
 121 #else\r
 122 void rk29_lcd_spim_spin_lock(void)\r
 123 {\r
 124      return;\r
 125 }\r
 126 \r
 127 void rk29_lcd_spim_spin_unlock(void)\r
 128 {\r
 129      return;\r
 130 }\r
 131 #endif\r
 132 \r
 133 #if defined(PRINT_TRANS_DATA)\r
 134 static void printk_transfer_data(unsigned char *buf, int len)\r
 135 {\r
 136         int i = 0;\r
 137         for(i=0; i<len; i++)\r
 138                 printk("0x%x,",*buf++);\r
 139 \r
 140         printk("\n");\r
 141 \r
 142 }\r
 143 #endif\r
 144 \r
 145 #if 0\r
 146 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 147         DBG("MRST SPI0 registers:\n");\r
 148         DBG("=================================\n");\r
 149         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 150         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 151         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 152         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 153         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 154         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 155         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 156         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 157         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 158         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 159         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 160         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 161         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 162         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 163         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 164         DBG("=================================\n");\r
 165 \r
 166 }\r
 167 #endif\r
 168 \r
 169 #ifdef CONFIG_DEBUG_FS\r
 170 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 171 {\r
 172         file->private_data = inode->i_private;\r
 173         return 0;\r
 174 }\r
 175 \r
 176 #define SPI_REGS_BUFSIZE        1024\r
 177 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 178                                 size_t count, loff_t *ppos)\r
 179 {\r
 180         struct rk29xx_spi *dws;\r
 181         char *buf;\r
 182         u32 len = 0;\r
 183         ssize_t ret;\r
 184 \r
 185         dws = file->private_data;\r
 186 \r
 187         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 188         if (!buf)\r
 189                 return 0;\r
 190 \r
 191         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 192                         "MRST SPI0 registers:\n");\r
 193         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 194                         "=================================\n");\r
 195         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 196                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 197         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 198                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 199         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 200                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 201         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 202                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 203         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 204                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 205         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 206                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 207         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 208                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 209         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 210                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 211         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 212                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 213         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 214                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 215         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 216                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 217         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 218                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 219         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 220                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 221         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 222                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 223         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 224                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 225         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 226                         "=================================\n");\r
 227 \r
 228         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 229         kfree(buf);\r
 230         return ret;\r
 231 }\r
 232 \r
 233 static const struct file_operations mrst_spi_regs_ops = {\r
 234         .owner          = THIS_MODULE,\r
 235         .open           = spi_show_regs_open,\r
 236         .read           = spi_show_regs,\r
 237 };\r
 238 \r
 239 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 240 {\r
 241         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 242         if (!dws->debugfs)\r
 243                 return -ENOMEM;\r
 244 \r
 245         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 246                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 247         return 0;\r
 248 }\r
 249 \r
 250 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 251 {\r
 252         if (dws->debugfs)\r
 253                 debugfs_remove_recursive(dws->debugfs);\r
 254 }\r
 255 \r
 256 #else\r
 257 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 258 {\r
 259         return 0;\r
 260 }\r
 261 \r
 262 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 263 {\r
 264 }\r
 265 #endif /* CONFIG_DEBUG_FS */\r
 266 \r
 267 static void dma_transfer(struct rk29xx_spi *dws) ;\r
 268 static void transfer_complete(struct rk29xx_spi *dws);\r
 269 \r
 270 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 271 {\r
 272         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 273         //if spi was slave, it is SR_BUSY always.  \r
 274         if(dws->cur_chip) {\r
 275                 if(dws->cur_chip->slave_enable == 1)\r
 276                         return;\r
 277         }\r
 278         \r
 279         while (time_before(jiffies, end)) {\r
 280                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 281                         return;\r
 282         }\r
 283         dev_err(&dws->master->dev,\r
 284                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 285 }\r
 286 \r
 287 #if defined(QUICK_TRANSFER)\r
 288 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 289 {\r
 290         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 291 \r
 292         while (time_before(jiffies, end)) {\r
 293                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 294                         return;\r
 295         }\r
 296         dev_err(&dws->master->dev,\r
 297                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 298 }\r
 299 #endif\r
 300 \r
 301 static void flush(struct rk29xx_spi *dws)\r
 302 {\r
 303         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 304                 rk29xx_readw(dws, SPIM_RXDR);\r
 305 \r
 306         wait_till_not_busy(dws);\r
 307 }\r
 308 \r
 309 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 310 {\r
 311         #if 1\r
 312         if (flag)\r
 313                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 314         else            \r
 315                 rk29xx_writel(dws, SPIM_SER, 0);\r
 316         return;\r
 317         #else\r
 318         \r
 319         #error "Warning: not support"\r
 320         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 321         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 322 \r
 323         if (flag == 0) {\r
 324                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 325         }\r
 326         else {\r
 327                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 328         }\r
 329         #endif\r
 330 }\r
 331 \r
 332 static int null_writer(struct rk29xx_spi *dws)\r
 333 {\r
 334         u8 n_bytes = dws->n_bytes;\r
 335 \r
 336         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 337                 || (dws->tx == dws->tx_end))\r
 338                 return 0;\r
 339         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 340         dws->tx += n_bytes;\r
 341         //wait_till_not_busy(dws);\r
 342 \r
 343         return 1;\r
 344 }\r
 345 \r
 346 static int null_reader(struct rk29xx_spi *dws)\r
 347 {\r
 348         u8 n_bytes = dws->n_bytes;\r
 349         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 350         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 351                 && (dws->rx < dws->rx_end)) {\r
 352                 rk29xx_readw(dws, SPIM_RXDR);\r
 353                 dws->rx += n_bytes;\r
 354         }\r
 355         wait_till_not_busy(dws);\r
 356         return dws->rx == dws->rx_end;\r
 357 }\r
 358 \r
 359 static int u8_writer(struct rk29xx_spi *dws)\r
 360 {       \r
 361         //spi_dump_regs(dws)\r
 362 #if defined(PRINT_TRANS_DATA)\r
 363         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 364 #endif\r
 365         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 366                 || (dws->tx == dws->tx_end))\r
 367                 return 0;\r
 368         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 369         ++dws->tx;\r
 370         //wait_till_not_busy(dws);\r
 371 \r
 372         return 1;\r
 373 }\r
 374 \r
 375 static int u8_reader(struct rk29xx_spi *dws)\r
 376 {\r
 377     //spi_dump_regs(dws);\r
 378         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 379                 && (dws->rx < dws->rx_end)) {\r
 380                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 381 #if defined(PRINT_TRANS_DATA)\r
 382                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 383 #endif\r
 384                 ++dws->rx;\r
 385         }\r
 386 \r
 387         wait_till_not_busy(dws);\r
 388         return dws->rx == dws->rx_end;\r
 389 }\r
 390 \r
 391 static int u16_writer(struct rk29xx_spi *dws)\r
 392 {       \r
 393 #if defined(PRINT_TRANS_DATA)\r
 394         DBG("tx: 0x%04x\n", *(u16 *)(dws->tx));\r
 395 #endif\r
 396         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 397                 || (dws->tx == dws->tx_end))\r
 398                 return 0;\r
 399 \r
 400         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 401         dws->tx += 2;\r
 402         //wait_till_not_busy(dws);\r
 403 \r
 404         return 1;\r
 405 }\r
 406 \r
 407 static int u16_reader(struct rk29xx_spi *dws)\r
 408 {\r
 409         u16 temp;\r
 410 \r
 411         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 412                 && (dws->rx < dws->rx_end)) {\r
 413                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 414                 *(u16 *)(dws->rx) = temp;\r
 415 #if defined(PRINT_TRANS_DATA)\r
 416                 DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 417 #endif\r
 418                 dws->rx += 2;\r
 419         }\r
 420 \r
 421         wait_till_not_busy(dws);\r
 422         return dws->rx == dws->rx_end;\r
 423 }\r
 424 \r
 425 static void *next_transfer(struct rk29xx_spi *dws)\r
 426 {\r
 427         struct spi_message *msg = dws->cur_msg;\r
 428         struct spi_transfer *trans = dws->cur_transfer;\r
 429 \r
 430         /* Move to next transfer */\r
 431         if (trans->transfer_list.next != &msg->transfers) {\r
 432                 dws->cur_transfer =\r
 433                         list_entry(trans->transfer_list.next,\r
 434                                         struct spi_transfer,\r
 435                                         transfer_list);\r
 436                 return RUNNING_STATE;\r
 437         } else\r
 438                 return DONE_STATE;\r
 439 }\r
 440 \r
 441 static void rk29_spi_dma_rxcb(void *buf_id,\r
 442                                  int size, enum rk29_dma_buffresult res)\r
 443 {\r
 444         struct rk29xx_spi *dws = buf_id;\r
 445         unsigned long flags;\r
 446 \r
 447         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 448         \r
 449         spin_lock_irqsave(&dws->lock, flags);\r
 450 \r
 451         if (res == RK29_RES_OK)\r
 452                 dws->state &= ~RXBUSY;\r
 453         else\r
 454                 dev_err(&dws->master->dev, "error:DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);\r
 455 \r
 456         //copy data from dma to transfer buf\r
 457         if(dws->cur_transfer && (dws->cur_transfer->rx_buf != NULL))\r
 458         {\r
 459                 memcpy(dws->cur_transfer->rx_buf, dws->buffer_rx_dma, dws->cur_transfer->len);\r
 460                 \r
 461                 #if defined(PRINT_TRANS_DATA)\r
 462                 printk("dma rx:");\r
 463                 printk_transfer_data(dws->cur_transfer->rx_buf, dws->cur_transfer->len);\r
 464                 #endif\r
 465         }\r
 466         \r
 467         spin_unlock_irqrestore(&dws->lock, flags);\r
 468         \r
 469         /* If the other done */\r
 470         if (!(dws->state & TXBUSY))\r
 471         {\r
 472                 //complete(&dws->xfer_completion);      \r
 473                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 474                 //DMA could not lose intterupt\r
 475                 transfer_complete(dws);\r
 476         }\r
 477 \r
 478 }\r
 479 \r
 480 static void rk29_spi_dma_txcb(void *buf_id,\r
 481                                  int size, enum rk29_dma_buffresult res)\r
 482 {\r
 483         struct rk29xx_spi *dws = buf_id;\r
 484         unsigned long flags;\r
 485 \r
 486         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 487         \r
 488         spin_lock_irqsave(&dws->lock, flags);\r
 489 \r
 490         if (res == RK29_RES_OK)\r
 491                 dws->state &= ~TXBUSY;\r
 492         else\r
 493                 dev_err(&dws->master->dev, "error:DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);\r
 494 \r
 495         spin_unlock_irqrestore(&dws->lock, flags);\r
 496         \r
 497         /* If the other done */\r
 498         if (!(dws->state & RXBUSY)) \r
 499         {\r
 500                 //complete(&dws->xfer_completion);\r
 501                 \r
 502                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 503                 //DMA could not lose intterupt\r
 504                 transfer_complete(dws);\r
 505         }\r
 506 \r
 507 }\r
 508 \r
 509 \r
 510 static struct rk29_dma_client rk29_spi_dma_client = {\r
 511         .name = "rk29xx-spi-dma",\r
 512 };\r
 513 \r
 514 static int acquire_dma(struct rk29xx_spi *dws)\r
 515 {       \r
 516         if (dws->dma_inited) {\r
 517                 return 0;\r
 518         }\r
 519 \r
 520         dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);\r
 521         if (!dws->buffer_tx_dma)\r
 522         {\r
 523                 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");\r
 524                 return -1;\r
 525         }\r
 526 \r
 527         dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);\r
 528         if (!dws->buffer_rx_dma)\r
 529         {\r
 530                 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");\r
 531                 return -1;\r
 532         }\r
 533 \r
 534         if(rk29_dma_request(dws->rx_dmach, \r
 535                 &rk29_spi_dma_client, NULL) < 0) {\r
 536                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 537                 return -1;\r
 538         }\r
 539 \r
 540         if (rk29_dma_request(dws->tx_dmach,\r
 541                                         &rk29_spi_dma_client, NULL) < 0) {\r
 542                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 543                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 544                 return -1;\r
 545         }\r
 546 \r
 547         if (dws->tx_dma) {\r
 548                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 549                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 550                         return -1;\r
 551                 }\r
 552                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 553                                         dws->sfr_start + SPIM_TXDR)) {\r
 554                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 555                         return -1;\r
 556                 }\r
 557         }\r
 558 \r
 559         if (dws->rx_dma) {\r
 560                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 561                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 562                         return -1;\r
 563                 }\r
 564                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 565                                         dws->sfr_start + SPIM_RXDR)) {\r
 566                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 567                         return -1;\r
 568                 }\r
 569         }\r
 570         \r
 571         dws->dma_inited = 1;\r
 572         return 0;\r
 573 }\r
 574 \r
 575 static void release_dma(struct rk29xx_spi *dws)\r
 576 {\r
 577         if(!dws && dws->dma_inited) {\r
 578                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 579                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 580         }\r
 581 }\r
 582 \r
 583 /*\r
 584  * Note: first step is the protocol driver prepares\r
 585  * a dma-capable memory, and this func just need translate\r
 586  * the virt addr to physical\r
 587  */\r
 588 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 589 {\r
 590         if (!dws->dma_inited || !dws->cur_chip->enable_dma)\r
 591         {\r
 592                 printk("%s:error\n",__func__);\r
 593                 return -1;\r
 594         }\r
 595 \r
 596         if(dws->cur_transfer->tx_buf)\r
 597         {\r
 598                 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);\r
 599         }\r
 600         \r
 601         dws->cur_transfer->tx_dma = dws->tx_dma;\r
 602         dws->cur_transfer->rx_dma = dws->rx_dma;\r
 603         \r
 604         return 0;\r
 605 }\r
 606 \r
 607 /* Caller already set message->status; dma and pio irqs are blocked */\r
 608 static void giveback(struct rk29xx_spi *dws)\r
 609 {\r
 610         struct spi_transfer *last_transfer;\r
 611         unsigned long flags;\r
 612         struct spi_message *msg;\r
 613 \r
 614         spin_lock_irqsave(&dws->lock, flags);\r
 615         msg = dws->cur_msg;\r
 616         dws->cur_msg = NULL;\r
 617         dws->cur_transfer = NULL;\r
 618         dws->prev_chip = dws->cur_chip;\r
 619         dws->cur_chip = NULL;\r
 620         dws->dma_mapped = 0;\r
 621 \r
 622         \r
 623         /*it is important to close intterrupt*/\r
 624         spi_mask_intr(dws, 0xff);\r
 625         rk29xx_writew(dws, SPIM_DMACR, 0);\r
 626         \r
 627         queue_work(dws->workqueue, &dws->pump_messages);\r
 628         spin_unlock_irqrestore(&dws->lock, flags);\r
 629 \r
 630         last_transfer = list_entry(msg->transfers.prev,\r
 631                                         struct spi_transfer,\r
 632                                         transfer_list);\r
 633 \r
 634         if (!last_transfer->cs_change && dws->cs_control)\r
 635                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 636 \r
 637         msg->state = NULL;\r
 638         if (msg->complete)\r
 639                 msg->complete(msg->context);\r
 640 \r
 641         DBG("%s ok\n",__func__);\r
 642 \r
 643 }\r
 644 \r
 645 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 646 {\r
 647         /* Stop and reset hw */\r
 648         flush(dws);\r
 649         spi_enable_chip(dws, 0);\r
 650 \r
 651         dev_err(&dws->master->dev, "%s\n", msg);\r
 652         dws->cur_msg->state = ERROR_STATE;\r
 653         tasklet_schedule(&dws->pump_transfers);\r
 654 }\r
 655 \r
 656 static void transfer_complete(struct rk29xx_spi *dws)\r
 657 {\r
 658         /* Update total byte transfered return count actual bytes read */\r
 659         dws->cur_msg->actual_length += dws->len;\r
 660 \r
 661         /* Move to next transfer */\r
 662         dws->cur_msg->state = next_transfer(dws);\r
 663 \r
 664         /* Handle end of message */\r
 665         if (dws->cur_msg->state == DONE_STATE) {\r
 666                 dws->cur_msg->status = 0;\r
 667                 giveback(dws);\r
 668         } else\r
 669                 tasklet_schedule(&dws->pump_transfers);\r
 670 }\r
 671 \r
 672 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 673 {\r
 674         u16 irq_status, irq_mask = 0x1f;\r
 675         u32 int_level = dws->fifo_len / 2;\r
 676         u32 left;\r
 677 \r
 678         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 679         /* Error handling */\r
 680         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 681                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 682                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 683                 mutex_unlock(&dws->dma_lock);   \r
 684                 return IRQ_HANDLED;\r
 685         }\r
 686 \r
 687         if (irq_status & SPI_INT_TXEI) {\r
 688                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 689 \r
 690                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 691                 left = (left > int_level) ? int_level : left;\r
 692 \r
 693                 while (left--) {\r
 694                         dws->write(dws);\r
 695                         wait_till_not_busy(dws);\r
 696                 }\r
 697                 if (dws->rx) {\r
 698                     dws->read(dws);\r
 699                 }\r
 700 \r
 701                 /* Re-enable the IRQ if there is still data left to tx */\r
 702                 if (dws->tx_end > dws->tx)\r
 703                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 704                 else\r
 705                         transfer_complete(dws);\r
 706         }\r
 707 \r
 708         if (irq_status & SPI_INT_RXFI) {\r
 709                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 710                 \r
 711                 dws->read(dws);\r
 712 \r
 713                 /* Re-enable the IRQ if there is still data left to rx */\r
 714                 if (dws->rx_end > dws->rx) {\r
 715                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 716                     left = (left > int_level) ? int_level : left;\r
 717 \r
 718                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 719                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 720                 }\r
 721                 else {\r
 722                         transfer_complete(dws);\r
 723                 }\r
 724                 \r
 725         }       \r
 726 \r
 727         return IRQ_HANDLED;\r
 728 }\r
 729 \r
 730 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 731 {\r
 732         struct rk29xx_spi *dws = dev_id;\r
 733 \r
 734         if (!dws->cur_msg) {\r
 735                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 736                 /* Never fail */\r
 737                 return IRQ_HANDLED;\r
 738         }\r
 739 \r
 740         return dws->transfer_handler(dws);\r
 741 }\r
 742 \r
 743 /* Must be called inside pump_transfers() */\r
 744 static void poll_transfer(struct rk29xx_spi *dws)\r
 745 {\r
 746 #if defined(PRINT_TRANS_DATA)\r
 747         DBG("%s\n",__func__);\r
 748 #endif\r
 749         while (dws->write(dws)) {\r
 750                 wait_till_not_busy(dws);\r
 751                 dws->read(dws);\r
 752         }\r
 753         transfer_complete(dws);\r
 754 }\r
 755 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 756 {\r
 757     if(cs >= dws->master->num_chipselect)\r
 758                 return;\r
 759 \r
 760         if (dws->cs_control){\r
 761             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 762         }\r
 763         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 764 }\r
 765 \r
 766 static void pump_transfers(unsigned long data)\r
 767 {\r
 768         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 769         struct spi_message *message = NULL;\r
 770         struct spi_transfer *transfer = NULL;\r
 771         struct spi_transfer *previous = NULL;\r
 772         struct spi_device *spi = NULL;\r
 773         struct chip_data *chip = NULL;\r
 774         u8 bits = 0;\r
 775         u8 spi_dfs = 0;\r
 776         u8 imask = 0;\r
 777         u8 cs_change = 0;\r
 778         u16 txint_level = 0;\r
 779         u16 rxint_level = 0;\r
 780         u16 clk_div = 0;\r
 781         u32 speed = 0;\r
 782         u32 cr0 = 0;\r
 783 \r
 784         if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){      \r
 785                 dma_transfer(dws);\r
 786                 return;\r
 787         }       \r
 788         \r
 789         DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);\r
 790 \r
 791         /* Get current state information */\r
 792         message = dws->cur_msg;\r
 793         transfer = dws->cur_transfer;\r
 794         chip = dws->cur_chip;\r
 795         spi = message->spi;     \r
 796         if (unlikely(!chip->clk_div))\r
 797                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 798         if (message->state == ERROR_STATE) {\r
 799                 message->status = -EIO;\r
 800                 goto early_exit;\r
 801         }\r
 802 \r
 803         /* Handle end of message */\r
 804         if (message->state == DONE_STATE) {\r
 805                 message->status = 0;\r
 806                 goto early_exit;\r
 807         }\r
 808 \r
 809         /* Delay if requested at end of transfer*/\r
 810         if (message->state == RUNNING_STATE) {\r
 811                 previous = list_entry(transfer->transfer_list.prev,\r
 812                                         struct spi_transfer,\r
 813                                         transfer_list);\r
 814                 if (previous->delay_usecs)\r
 815                         udelay(previous->delay_usecs);\r
 816         }\r
 817 \r
 818         dws->n_bytes = chip->n_bytes;\r
 819         dws->dma_width = chip->dma_width;\r
 820         dws->cs_control = chip->cs_control;\r
 821 \r
 822         //dws->rx_dma = transfer->rx_dma;\r
 823         //dws->tx_dma = transfer->tx_dma;\r
 824         dws->tx = (void *)transfer->tx_buf;\r
 825         dws->tx_end = dws->tx + transfer->len;\r
 826         dws->rx = (void *)transfer->rx_buf;\r
 827         dws->rx_end = dws->rx + transfer->len;\r
 828         dws->write = dws->tx ? chip->write : null_writer;\r
 829         dws->read = dws->rx ? chip->read : null_reader;\r
 830         dws->cs_change = transfer->cs_change;\r
 831         dws->len = dws->cur_transfer->len;\r
 832         if (chip != dws->prev_chip)\r
 833                 cs_change = 1;\r
 834 \r
 835         cr0 = chip->cr0;\r
 836 \r
 837         /* Handle per transfer options for bpw and speed */\r
 838         if (transfer->speed_hz) {\r
 839                 speed = chip->speed_hz;\r
 840 \r
 841                 if (transfer->speed_hz != speed) {\r
 842                         speed = transfer->speed_hz;\r
 843                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 844                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
 845                                         "freq: %dHz\n", speed);\r
 846                                 message->status = -EIO;\r
 847                                 goto early_exit;\r
 848                         }\r
 849 \r
 850                         /* clk_div doesn't support odd number */\r
 851                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 852                         clk_div = (clk_div + 1) & 0xfffe;\r
 853 \r
 854                         chip->speed_hz = speed;\r
 855                         chip->clk_div = clk_div;\r
 856                 }\r
 857         }\r
 858         \r
 859         if (transfer->bits_per_word) {\r
 860                 bits = transfer->bits_per_word;\r
 861 \r
 862                 switch (bits) {\r
 863                 case 8:\r
 864                         dws->n_bytes = 1;\r
 865                         dws->dma_width = 1;\r
 866                         dws->read = (dws->read != null_reader) ?\r
 867                                         u8_reader : null_reader;\r
 868                         dws->write = (dws->write != null_writer) ?\r
 869                                         u8_writer : null_writer;\r
 870                         spi_dfs = SPI_DFS_8BIT;\r
 871                         break;\r
 872                 case 16:\r
 873                         dws->n_bytes = 2;\r
 874                         dws->dma_width = 2;\r
 875                         dws->read = (dws->read != null_reader) ?\r
 876                                         u16_reader : null_reader;\r
 877                         dws->write = (dws->write != null_writer) ?\r
 878                                         u16_writer : null_writer;\r
 879                         spi_dfs = SPI_DFS_16BIT;\r
 880                         break;\r
 881                 default:\r
 882                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 883                                 "%db\n", bits);\r
 884                         message->status = -EIO;\r
 885                         goto early_exit;\r
 886                 }\r
 887 \r
 888                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 889                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 890                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 891                         | (chip->type << SPI_FRF_OFFSET)\r
 892                         | (spi->mode << SPI_MODE_OFFSET)\r
 893                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 894         }\r
 895         message->state = RUNNING_STATE;\r
 896  \r
 897         /*\r
 898          * Adjust transfer mode if necessary. Requires platform dependent\r
 899          * chipselect mechanism.\r
 900          */\r
 901         if (dws->cs_control) {\r
 902                 if (dws->rx && dws->tx)\r
 903                         chip->tmode = SPI_TMOD_TR;\r
 904                 else if (dws->rx)\r
 905                         chip->tmode = SPI_TMOD_RO;\r
 906                 else\r
 907                         chip->tmode = SPI_TMOD_TO;\r
 908 \r
 909                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);               \r
 910                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
 911                 cr0 &= ~(0x1 << SPI_OPMOD_OFFSET);      \r
 912                 cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
 913                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 914                 cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);\r
 915         } \r
 916 \r
 917         /*\r
 918          * Interrupt mode\r
 919          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 920          */\r
 921         if (!dws->dma_mapped && !chip->poll_mode) {     \r
 922                 int templen ;\r
 923                 \r
 924                 if (chip->tmode == SPI_TMOD_RO) {\r
 925                         templen = dws->len / dws->n_bytes - 1;\r
 926                         rxint_level = dws->fifo_len / 2;\r
 927                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 928                         imask |= SPI_INT_RXFI;\r
 929                 }\r
 930                 else {  \r
 931                         templen = dws->len / dws->n_bytes;\r
 932                         txint_level = dws->fifo_len / 2;\r
 933                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 934                         imask |= SPI_INT_TXEI;\r
 935                 }\r
 936                 dws->transfer_handler = interrupt_transfer;\r
 937         }\r
 938 \r
 939         /*\r
 940          * Reprogram registers only if\r
 941          *      1. chip select changes\r
 942          *      2. clk_div is changed\r
 943          *      3. control value changes\r
 944          */\r
 945         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div || imask) {\r
 946                 spi_enable_chip(dws, 0);\r
 947                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
 948                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
 949 \r
 950                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 951                 spi_chip_sel(dws, spi->chip_select);\r
 952 \r
 953         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 954                 \r
 955                 if (txint_level)\r
 956                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 957                 spi_enable_chip(dws, 1);        \r
 958                         \r
 959                 if (rxint_level)\r
 960                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 961                 /* Set the interrupt mask, for poll mode just diable all int */\r
 962                 spi_mask_intr(dws, 0xff);\r
 963                 if (imask)\r
 964                         spi_umask_intr(dws, imask);\r
 965                 \r
 966                 if (cs_change)\r
 967                         dws->prev_chip = chip;\r
 968         } \r
 969 \r
 970         if (chip->poll_mode)\r
 971                 poll_transfer(dws);\r
 972 \r
 973         return;\r
 974 \r
 975 early_exit:\r
 976         giveback(dws);\r
 977         return;\r
 978 }\r
 979 \r
 980 static void dma_transfer(struct rk29xx_spi *dws) \r
 981 {\r
 982         struct spi_message *message = NULL;\r
 983         struct spi_transfer *transfer = NULL;\r
 984         struct spi_transfer *previous = NULL;\r
 985         struct spi_device *spi = NULL;\r
 986         struct chip_data *chip = NULL;\r
 987         //unsigned long val;    \r
 988         //unsigned long flags;\r
 989         //int ms;\r
 990         int iRet;\r
 991         //int burst;\r
 992         u8 bits = 0;\r
 993         u8 spi_dfs = 0;\r
 994         u8 cs_change = 0;\r
 995         u16 clk_div = 0;\r
 996         u32 speed = 0;\r
 997         u32 cr0 = 0;\r
 998         u32 dmacr = 0;\r
 999         \r
1000         DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);  \r
1001         \r
1002         if (acquire_dma(dws)) {\r
1003                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
1004                 goto err_out;\r
1005         }\r
1006 \r
1007         if (map_dma_buffers(dws)) {\r
1008                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
1009                 goto err_out;\r
1010         }\r
1011 \r
1012         /* Get current state information */\r
1013         message = dws->cur_msg;\r
1014         transfer = dws->cur_transfer;\r
1015         chip = dws->cur_chip;\r
1016         spi = message->spi;     \r
1017         if (unlikely(!chip->clk_div))\r
1018                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
1019         if (message->state == ERROR_STATE) {\r
1020                 message->status = -EIO;\r
1021                 goto err_out;\r
1022         }\r
1023 \r
1024         /* Handle end of message */\r
1025         if (message->state == DONE_STATE) {\r
1026                 message->status = 0;\r
1027                 goto err_out;\r
1028         }\r
1029 \r
1030         /* Delay if requested at end of transfer*/\r
1031         if (message->state == RUNNING_STATE) {\r
1032                 previous = list_entry(transfer->transfer_list.prev,\r
1033                                         struct spi_transfer,\r
1034                                         transfer_list);\r
1035                 if (previous->delay_usecs)\r
1036                         udelay(previous->delay_usecs);\r
1037         }\r
1038 \r
1039         dws->n_bytes = chip->n_bytes;\r
1040         dws->dma_width = chip->dma_width;\r
1041         dws->cs_control = chip->cs_control;\r
1042 \r
1043         //dws->rx_dma = transfer->rx_dma;\r
1044         //dws->tx_dma = transfer->tx_dma;\r
1045         dws->tx = (void *)transfer->tx_buf;\r
1046         dws->tx_end = dws->tx + transfer->len;\r
1047         dws->rx = (void *)transfer->rx_buf;\r
1048         dws->rx_end = dws->rx + transfer->len;\r
1049         dws->write = dws->tx ? chip->write : null_writer;\r
1050         dws->read = dws->rx ? chip->read : null_reader;\r
1051         dws->cs_change = transfer->cs_change;\r
1052         dws->len = dws->cur_transfer->len;\r
1053         if (chip != dws->prev_chip)\r
1054                 cs_change = 1;\r
1055 \r
1056         cr0 = chip->cr0;\r
1057         \r
1058         /* Handle per transfer options for bpw and speed */\r
1059         if (transfer->speed_hz) {\r
1060                 speed = chip->speed_hz;\r
1061                 if (transfer->speed_hz != speed) {\r
1062                         speed = transfer->speed_hz;\r
1063                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1064                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
1065                                         "freq: %dHz\n", speed);\r
1066                                 message->status = -EIO;\r
1067                                 goto err_out;\r
1068                         }\r
1069 \r
1070                         /* clk_div doesn't support odd number */\r
1071                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1072                         clk_div = (clk_div + 1) & 0xfffe;\r
1073 \r
1074                         chip->speed_hz = speed;\r
1075                         chip->clk_div = clk_div;\r
1076                 }\r
1077         }\r
1078 \r
1079         \r
1080         if (transfer->bits_per_word) {\r
1081                 bits = transfer->bits_per_word;\r
1082 \r
1083                 switch (bits) {\r
1084                 case 8:\r
1085                         dws->n_bytes = 1;\r
1086                         dws->dma_width = 1;\r
1087                         spi_dfs = SPI_DFS_8BIT;\r
1088                         break;\r
1089                 case 16:\r
1090                         dws->n_bytes = 2;\r
1091                         dws->dma_width = 2;\r
1092                         spi_dfs = SPI_DFS_16BIT;\r
1093                         break;\r
1094                 default:\r
1095                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1096                                 "%db\n", bits);\r
1097                         message->status = -EIO;\r
1098                         goto err_out;\r
1099                 }\r
1100 \r
1101                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1102                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1103                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1104                         | (chip->type << SPI_FRF_OFFSET)\r
1105                         | (spi->mode << SPI_MODE_OFFSET)\r
1106                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1107         }\r
1108         message->state = RUNNING_STATE;\r
1109  \r
1110         /*\r
1111          * Adjust transfer mode if necessary. Requires platform dependent\r
1112          * chipselect mechanism.\r
1113          */\r
1114         if (dws->cs_control) {\r
1115                 if (dws->rx && dws->tx)\r
1116                         chip->tmode = SPI_TMOD_TR;\r
1117                 else if (dws->rx)\r
1118                         chip->tmode = SPI_TMOD_RO;\r
1119                 else\r
1120                         chip->tmode = SPI_TMOD_TO;\r
1121 \r
1122                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1123                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
1124                 cr0 &= ~(0x1 << SPI_OPMOD_OFFSET);              \r
1125                 cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
1126                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1127                 cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);\r
1128         }\r
1129 \r
1130         /*\r
1131          * Reprogram registers only if\r
1132          *      1. chip select changes\r
1133          *      2. clk_div is changed\r
1134          *      3. control value changes\r
1135          */\r
1136         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div) {\r
1137                 spi_enable_chip(dws, 0);\r
1138                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0) {\r
1139                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1140                 }\r
1141                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1142                 spi_chip_sel(dws, spi->chip_select);\r
1143                 /* Set the interrupt mask, for poll mode just diable all int */\r
1144                 spi_mask_intr(dws, 0xff);\r
1145                 \r
1146                 if (transfer->tx_buf != NULL) {\r
1147                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1148                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1149                 }\r
1150                 if (transfer->rx_buf != NULL) {\r
1151                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1152                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1153                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);       \r
1154                 }\r
1155                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1156                 spi_enable_chip(dws, 1);\r
1157                 if (cs_change)\r
1158                         dws->prev_chip = chip;\r
1159         } \r
1160 \r
1161         //INIT_COMPLETION(dws->xfer_completion);\r
1162 \r
1163         //spi_dump_regs(dws);\r
1164         \r
1165         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, dws->tx_dma: 0x%x,dws->rx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)dws->tx_dma,(unsigned int)dws->rx_dma);  \r
1166         DBG("dws->buffer_tx_dma: 0x%p, dws->buffer_rx_dma: 0x%p,dws->dma_width=%d\n", dws->buffer_tx_dma, dws->buffer_rx_dma,dws->dma_width);   \r
1167 \r
1168         if (transfer->tx_buf != NULL)           \r
1169                 dws->state |= TXBUSY;   \r
1170         if (transfer->rx_buf != NULL) \r
1171                 dws->state |= RXBUSY;\r
1172 \r
1173         if (transfer->tx_buf != NULL) { \r
1174                 DBG("%s:start dma tx,dws->state=0x%x\n",__func__,dws->state);\r
1175                 #if defined(PRINT_TRANS_DATA)\r
1176                 printk("dma tx:");\r
1177                 printk_transfer_data(dws->buffer_tx_dma, dws->cur_transfer->len);\r
1178                 #endif\r
1179                 /*if (transfer->len & 0x3) {\r
1180                         burst = 1;\r
1181                 }\r
1182                 else {\r
1183                         burst = 4;\r
1184                 }\r
1185                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1186                 if (rk29_dma_config(dws->tx_dmach, dws->dma_width, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1187                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1188                         goto err_out;\r
1189                 }\r
1190                 \r
1191                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1192                 \r
1193                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1194                                         dws->tx_dma, transfer->len);\r
1195                 if (iRet) {\r
1196                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1197                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1198                         goto err_out;\r
1199                 }\r
1200                 \r
1201                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1202                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1203                         goto err_out;\r
1204                 }\r
1205         }\r
1206 \r
1207         //wait_till_not_busy(dws);\r
1208         \r
1209         if (transfer->rx_buf != NULL) {                 \r
1210                 DBG("%s:start dma rx,dws->state=0x%x\n",__func__,dws->state);\r
1211                 if (rk29_dma_config(dws->rx_dmach, dws->dma_width, 1)) {\r
1212                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1213                         goto err_out;\r
1214                 }\r
1215 \r
1216                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1217                 \r
1218                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1219                                         dws->rx_dma, transfer->len);\r
1220                 if (iRet) {\r
1221                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1222                         goto err_out;\r
1223                 }\r
1224                 \r
1225                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1226                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1227                         goto err_out;\r
1228                 }\r
1229         }\r
1230         \r
1231         //wait_till_not_busy(dws);\r
1232         \r
1233         return;\r
1234 \r
1235 err_out:\r
1236         giveback(dws);\r
1237         return;\r
1238 \r
1239 }\r
1240 \r
1241 static void pump_messages(struct work_struct *work)\r
1242 {\r
1243         struct rk29xx_spi *dws =\r
1244                 container_of(work, struct rk29xx_spi, pump_messages);\r
1245         unsigned long flags;\r
1246 \r
1247         DBG(KERN_INFO "pump_messages,line=%d\n",__LINE__);\r
1248         \r
1249         /* Lock queue and check for queue work */\r
1250         spin_lock_irqsave(&dws->lock, flags);\r
1251         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1252                 dws->busy = 0;\r
1253                 spin_unlock_irqrestore(&dws->lock, flags);\r
1254                 DBG("%s:line=%d,list_empty\n",__func__,__LINE__);\r
1255                 return;\r
1256         }\r
1257 \r
1258         /* Make sure we are not already running a message */\r
1259         if (dws->cur_msg) {\r
1260                 spin_unlock_irqrestore(&dws->lock, flags);              \r
1261                 DBG("%s:line=%d,dws->cur_msg\n",__func__,__LINE__);\r
1262                 return;\r
1263         }\r
1264 \r
1265         /* Extract head of queue */\r
1266         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1267         list_del_init(&dws->cur_msg->queue);\r
1268 \r
1269         /* Initial message state*/\r
1270         dws->cur_msg->state = START_STATE;\r
1271         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1272                                                 struct spi_transfer,\r
1273                                                 transfer_list);\r
1274         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1275         dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1276 \r
1277         \r
1278         /* Mark as busy and launch transfers */\r
1279         tasklet_schedule(&dws->pump_transfers);\r
1280         dws->busy = 1;\r
1281         spin_unlock_irqrestore(&dws->lock, flags);\r
1282         \r
1283 }\r
1284 \r
1285 #if defined(QUICK_TRANSFER)\r
1286 static void do_read(struct rk29xx_spi *dws)\r
1287 {\r
1288         int count = 0;\r
1289 \r
1290         spi_enable_chip(dws, 0);\r
1291         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1292         spi_enable_chip(dws, 1);                \r
1293         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1294         while (1) {\r
1295                 if (dws->read(dws))\r
1296                         break;\r
1297                 if (count++ == 0x20) {\r
1298                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1299                         break;\r
1300                 }\r
1301                 \r
1302         }\r
1303 }\r
1304 \r
1305 static void do_write(struct rk29xx_spi *dws)\r
1306 {\r
1307         while (dws->tx<dws->tx_end) {\r
1308                 dws->write(dws);\r
1309         }\r
1310 }\r
1311 \r
1312 /* Caller already set message->status; dma and pio irqs are blocked */\r
1313 static void msg_giveback(struct rk29xx_spi *dws)\r
1314 {\r
1315         struct spi_transfer *last_transfer;\r
1316         struct spi_message *msg;\r
1317 \r
1318         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1319 \r
1320         msg = dws->cur_msg;\r
1321         dws->cur_msg = NULL;\r
1322         dws->cur_transfer = NULL;\r
1323         dws->prev_chip = dws->cur_chip;\r
1324         dws->cur_chip = NULL;\r
1325         dws->dma_mapped = 0;\r
1326         dws->busy = 0;\r
1327 \r
1328         last_transfer = list_entry(msg->transfers.prev,\r
1329                                         struct spi_transfer,\r
1330                                         transfer_list);\r
1331 \r
1332         if (!last_transfer->cs_change && dws->cs_control)\r
1333                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1334 \r
1335         msg->state = NULL;      \r
1336 }\r
1337 \r
1338 /* Must be called inside pump_transfers() */\r
1339 static int do_full_transfer(struct rk29xx_spi *dws)\r
1340 {\r
1341         if ((dws->read(dws))) {\r
1342                 goto comple;\r
1343         }\r
1344         \r
1345         while (dws->tx<dws->tx_end){\r
1346                 dws->write(dws);                \r
1347                 dws->read(dws);\r
1348         }\r
1349         \r
1350         if (dws->rx < dws->rx_end) {\r
1351                 dws->read(dws);\r
1352         }\r
1353 \r
1354 comple:\r
1355         \r
1356         dws->cur_msg->actual_length += dws->len;\r
1357         \r
1358         /* Move to next transfer */\r
1359         dws->cur_msg->state = next_transfer(dws);\r
1360                                         \r
1361         if (dws->cur_msg->state == DONE_STATE) {\r
1362                 dws->cur_msg->status = 0;\r
1363                 //msg_giveback(dws);\r
1364                 return 0;\r
1365         }\r
1366         else {\r
1367                 return -1;\r
1368         }\r
1369         \r
1370 }\r
1371 \r
1372 \r
1373 /* Must be called inside pump_transfers() */\r
1374 static int do_half_transfer(struct rk29xx_spi *dws)\r
1375 {\r
1376         if (dws->rx) {\r
1377                 if (dws->tx) {\r
1378                         do_write(dws);\r
1379                 }\r
1380                 wait_till_tf_empty(dws);\r
1381                 wait_till_not_busy(dws);\r
1382                 do_read(dws);\r
1383         }\r
1384         else {\r
1385                 do_write(dws);\r
1386                 wait_till_tf_empty(dws);\r
1387                 wait_till_not_busy(dws);\r
1388         }\r
1389         \r
1390         dws->cur_msg->actual_length += dws->len;\r
1391         \r
1392         /* Move to next transfer */\r
1393         dws->cur_msg->state = next_transfer(dws);\r
1394                                         \r
1395         if (dws->cur_msg->state == DONE_STATE) {\r
1396                 dws->cur_msg->status = 0;\r
1397                 //msg_giveback(dws);\r
1398                 return 0;\r
1399         }\r
1400         else {\r
1401                 return -1;\r
1402         }\r
1403 }\r
1404 \r
1405 \r
1406 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1407 {\r
1408         struct spi_message *message = NULL;\r
1409         struct spi_transfer *transfer = NULL;\r
1410         struct spi_transfer *previous = NULL;\r
1411         struct spi_device *spi = NULL;\r
1412         struct chip_data *chip = NULL;\r
1413         u8 bits = 0;\r
1414         u8 spi_dfs = 0;\r
1415         u8 cs_change = 0;\r
1416         u16 clk_div = 0;\r
1417         u32 speed = 0;\r
1418         u32 cr0 = 0;\r
1419         u32 dmacr = 0;\r
1420         \r
1421         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1422 \r
1423         /* Get current state information */\r
1424         message = dws->cur_msg;\r
1425         transfer = dws->cur_transfer;\r
1426         chip = dws->cur_chip;\r
1427         spi = message->spi;     \r
1428 \r
1429         if (unlikely(!chip->clk_div))\r
1430                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1431         if (message->state == ERROR_STATE) {\r
1432                 message->status = -EIO;\r
1433                 goto early_exit;\r
1434         }\r
1435 \r
1436         /* Handle end of message */\r
1437         if (message->state == DONE_STATE) {\r
1438                 message->status = 0;\r
1439                 goto early_exit;\r
1440         }\r
1441 \r
1442         /* Delay if requested at end of transfer*/\r
1443         if (message->state == RUNNING_STATE) {\r
1444                 previous = list_entry(transfer->transfer_list.prev,\r
1445                                         struct spi_transfer,\r
1446                                         transfer_list);\r
1447                 if (previous->delay_usecs)\r
1448                         udelay(previous->delay_usecs);\r
1449         }\r
1450 \r
1451         dws->n_bytes = chip->n_bytes;\r
1452         dws->dma_width = chip->dma_width;\r
1453         dws->cs_control = chip->cs_control;\r
1454 \r
1455         dws->rx_dma = transfer->rx_dma;\r
1456         dws->tx_dma = transfer->tx_dma;\r
1457         dws->tx = (void *)transfer->tx_buf;\r
1458         dws->tx_end = dws->tx + transfer->len;\r
1459         dws->rx = transfer->rx_buf;\r
1460         dws->rx_end = dws->rx + transfer->len;\r
1461         dws->write = dws->tx ? chip->write : null_writer;\r
1462         dws->read = dws->rx ? chip->read : null_reader;\r
1463         if (dws->rx && dws->tx) {\r
1464                 int temp_len = transfer->len;\r
1465                 int len;\r
1466                 unsigned char *tx_buf;\r
1467                 for (len=0; *tx_buf++ != 0; len++);\r
1468                 dws->tx_end = dws->tx + len;\r
1469                 dws->rx_end = dws->rx + temp_len - len;\r
1470         }\r
1471         dws->cs_change = transfer->cs_change;\r
1472         dws->len = dws->cur_transfer->len;\r
1473         if (chip != dws->prev_chip)\r
1474                 cs_change = 1;\r
1475 \r
1476         cr0 = chip->cr0;\r
1477 \r
1478         /* Handle per transfer options for bpw and speed */\r
1479         if (transfer->speed_hz) {\r
1480                 speed = chip->speed_hz;\r
1481 \r
1482                 if (transfer->speed_hz != speed) {\r
1483                         speed = transfer->speed_hz;\r
1484                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1485                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1486                                         "freq: %dHz\n", speed);\r
1487                                 message->status = -EIO;\r
1488                                 goto early_exit;\r
1489                         }\r
1490 \r
1491                         /* clk_div doesn't support odd number */\r
1492                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1493                         clk_div = (clk_div + 1) & 0xfffe;\r
1494 \r
1495                         chip->speed_hz = speed;\r
1496                         chip->clk_div = clk_div;\r
1497                 }\r
1498         }\r
1499         if (transfer->bits_per_word) {\r
1500                 bits = transfer->bits_per_word;\r
1501 \r
1502                 switch (bits) {\r
1503                 case 8:\r
1504                         dws->n_bytes = 1;\r
1505                         dws->dma_width = 1;\r
1506                         dws->read = (dws->read != null_reader) ?\r
1507                                         u8_reader : null_reader;\r
1508                         dws->write = (dws->write != null_writer) ?\r
1509                                         u8_writer : null_writer;\r
1510                         spi_dfs = SPI_DFS_8BIT;\r
1511                         break;\r
1512                 case 16:\r
1513                         dws->n_bytes = 2;\r
1514                         dws->dma_width = 2;\r
1515                         dws->read = (dws->read != null_reader) ?\r
1516                                         u16_reader : null_reader;\r
1517                         dws->write = (dws->write != null_writer) ?\r
1518                                         u16_writer : null_writer;\r
1519                         spi_dfs = SPI_DFS_16BIT;\r
1520                         break;\r
1521                 default:\r
1522                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1523                                 "%db\n", bits);\r
1524                         message->status = -EIO;\r
1525                         goto early_exit;\r
1526                 }\r
1527 \r
1528                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1529                         | (chip->type << SPI_FRF_OFFSET)\r
1530                         | (spi->mode << SPI_MODE_OFFSET)\r
1531                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1532         }\r
1533         message->state = RUNNING_STATE;\r
1534  \r
1535         /*\r
1536          * Adjust transfer mode if necessary. Requires platform dependent\r
1537          * chipselect mechanism.\r
1538          */\r
1539         if (dws->cs_control) {\r
1540                 if (dws->rx && dws->tx)\r
1541                         chip->tmode = SPI_TMOD_TR;\r
1542                 else if (dws->rx)\r
1543                         chip->tmode = SPI_TMOD_RO;\r
1544                 else\r
1545                         chip->tmode = SPI_TMOD_TO;\r
1546 \r
1547                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1548                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
1549                 cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
1550                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1551         }\r
1552         \r
1553         /* Check if current transfer is a DMA transaction */\r
1554         dws->dma_mapped = map_dma_buffers(dws);\r
1555 \r
1556         /*\r
1557          * Reprogram registers only if\r
1558          *      1. chip select changes\r
1559          *      2. clk_div is changed\r
1560          *      3. control value changes\r
1561          */\r
1562         spi_enable_chip(dws, 0);\r
1563         if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
1564                 rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1565 \r
1566     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1567         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1568         spi_chip_sel(dws, spi->chip_select);            \r
1569         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1570         if(dws->dma_mapped ) {\r
1571                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1572                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1573                 if (mode) \r
1574                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1575                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1576         }\r
1577         spi_enable_chip(dws, 1);\r
1578         if (cs_change)\r
1579                 dws->prev_chip = chip;\r
1580         \r
1581         if (mode)\r
1582                 return do_full_transfer(dws);\r
1583         else\r
1584                 return do_half_transfer(dws);   \r
1585         \r
1586 early_exit:\r
1587         \r
1588         //msg_giveback(dws);\r
1589         \r
1590         return 0;\r
1591 }\r
1592 \r
1593 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1594 {\r
1595         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1596         \r
1597         while (!acquire_dma(dws))\r
1598                         msleep(10);\r
1599 \r
1600         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1601                 dws->busy = 0;\r
1602                 return;\r
1603         }\r
1604 \r
1605         /* Make sure we are not already running a message */\r
1606         if (dws->cur_msg) {\r
1607                 return;\r
1608         }\r
1609 \r
1610         /* Extract head of queue */\r
1611         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1612         list_del_init(&dws->cur_msg->queue);\r
1613 \r
1614         /* Initial message state*/\r
1615         dws->cur_msg->state = START_STATE;\r
1616         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1617                                                 struct spi_transfer,\r
1618                                                 transfer_list);\r
1619         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1620     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1621     \r
1622         /* Mark as busy and launch transfers */\r
1623         dws->busy = 1;\r
1624 \r
1625         while (rk29xx_pump_transfers(dws, mode)) ;\r
1626 }\r
1627 \r
1628 /* spi_device use this to queue in their spi_msg */\r
1629 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1630 {\r
1631         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1632         unsigned long flags;\r
1633         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1634         struct spi_message *mmsg;\r
1635         \r
1636         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1637         \r
1638         spin_lock_irqsave(&dws->lock, flags);\r
1639 \r
1640         if (dws->run == QUEUE_STOPPED) {\r
1641                 spin_unlock_irqrestore(&dws->lock, flags);\r
1642                 return -ESHUTDOWN;\r
1643         }\r
1644 \r
1645         msg->actual_length = 0;\r
1646         msg->status = -EINPROGRESS;\r
1647         msg->state = START_STATE;\r
1648 \r
1649         list_add_tail(&msg->queue, &dws->queue);\r
1650 \r
1651         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1652                 rk29xx_pump_messages(dws,1);\r
1653         }\r
1654         else {          \r
1655                 rk29xx_pump_messages(dws,0);\r
1656         }\r
1657 \r
1658         mmsg = dws->cur_msg;\r
1659         msg_giveback(dws);\r
1660         \r
1661         spin_unlock_irqrestore(&dws->lock, flags);\r
1662 \r
1663         if (mmsg->complete)\r
1664                 mmsg->complete(mmsg->context);\r
1665         \r
1666         return 0;\r
1667 }\r
1668 \r
1669 #else\r
1670 \r
1671 /* spi_device use this to queue in their spi_msg */\r
1672 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1673 {\r
1674         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1675         unsigned long flags;\r
1676 \r
1677         spin_lock_irqsave(&dws->lock, flags);\r
1678 \r
1679         if (dws->run == QUEUE_STOPPED) {\r
1680                 spin_unlock_irqrestore(&dws->lock, flags);\r
1681                 return -ESHUTDOWN;\r
1682         }\r
1683 \r
1684         msg->actual_length = 0;\r
1685         msg->status = -EINPROGRESS;\r
1686         msg->state = START_STATE;\r
1687 \r
1688         list_add_tail(&msg->queue, &dws->queue);\r
1689 \r
1690         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1691 \r
1692                 if (dws->cur_transfer || dws->cur_msg)\r
1693                         queue_work(dws->workqueue,\r
1694                                         &dws->pump_messages);\r
1695                 else {\r
1696                         /* If no other data transaction in air, just go */\r
1697                         spin_unlock_irqrestore(&dws->lock, flags);\r
1698                         pump_messages(&dws->pump_messages);                     \r
1699                         return 0;\r
1700                 }\r
1701         }\r
1702 \r
1703         spin_unlock_irqrestore(&dws->lock, flags);\r
1704         \r
1705         return 0;\r
1706 }\r
1707 \r
1708 #endif\r
1709 \r
1710 /* This may be called twice for each spi dev */\r
1711 static int rk29xx_spi_setup(struct spi_device *spi)\r
1712 {\r
1713         struct rk29xx_spi_chip *chip_info = NULL;\r
1714         struct chip_data *chip;\r
1715         u8 spi_dfs = 0;\r
1716 \r
1717         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1718                 return -EINVAL;\r
1719 \r
1720         /* Only alloc on first setup */\r
1721         chip = spi_get_ctldata(spi);\r
1722         if (!chip) {\r
1723                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1724                 if (!chip)\r
1725                         return -ENOMEM;\r
1726 \r
1727                 chip->cs_control = spi_cs_control;\r
1728                 chip->enable_dma = 0;  //0;\r
1729         }\r
1730 \r
1731         /*\r
1732          * Protocol drivers may change the chip settings, so...\r
1733          * if chip_info exists, use it\r
1734          */\r
1735         chip_info = spi->controller_data;\r
1736 \r
1737         /* chip_info doesn't always exist */\r
1738         if (chip_info) {\r
1739                 if (chip_info->cs_control)\r
1740                         chip->cs_control = chip_info->cs_control;\r
1741 \r
1742                 chip->poll_mode = chip_info->poll_mode;\r
1743                 chip->type = chip_info->type;\r
1744                 chip->slave_enable = chip_info->slave_enable;\r
1745                 chip->rx_threshold = 0;\r
1746                 chip->tx_threshold = 0;\r
1747 \r
1748                 chip->enable_dma = chip_info->enable_dma;\r
1749         }\r
1750 \r
1751         if (spi->bits_per_word == 8) {\r
1752                 chip->n_bytes = 1;\r
1753                 chip->dma_width = 1;\r
1754                 chip->read = u8_reader;\r
1755                 chip->write = u8_writer;\r
1756                 spi_dfs = SPI_DFS_8BIT;\r
1757         } else if (spi->bits_per_word == 16) {\r
1758                 chip->n_bytes = 2;\r
1759                 chip->dma_width = 2;\r
1760                 chip->read = u16_reader;\r
1761                 chip->write = u16_writer;\r
1762                 spi_dfs = SPI_DFS_16BIT;\r
1763         } else {\r
1764                 /* Never take >16b case for MRST SPIC */\r
1765                 dev_err(&spi->dev, "invalid wordsize\n");\r
1766                 return -EINVAL;\r
1767         }\r
1768         chip->bits_per_word = spi->bits_per_word;\r
1769 \r
1770         if (!spi->max_speed_hz) {\r
1771                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1772                 return -EINVAL;\r
1773         }\r
1774         chip->speed_hz = spi->max_speed_hz;\r
1775 \r
1776         chip->tmode = 0; /* Tx & Rx */\r
1777         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1778         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1779                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1780                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1781                         | (chip->type << SPI_FRF_OFFSET)\r
1782                         | (spi->mode  << SPI_MODE_OFFSET)\r
1783                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1784 \r
1785         spi_set_ctldata(spi, chip);\r
1786         return 0;\r
1787 }\r
1788 \r
1789 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1790 {\r
1791         struct chip_data *chip = spi_get_ctldata(spi);\r
1792         kfree(chip);\r
1793 }\r
1794 \r
1795 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1796 {\r
1797         INIT_LIST_HEAD(&dws->queue);\r
1798         spin_lock_init(&dws->lock);\r
1799 \r
1800         dws->run = QUEUE_STOPPED;\r
1801         dws->busy = 0;\r
1802 \r
1803         init_completion(&dws->xfer_completion);\r
1804 \r
1805         tasklet_init(&dws->pump_transfers,\r
1806                         pump_transfers, (unsigned long)dws);\r
1807 \r
1808         INIT_WORK(&dws->pump_messages, pump_messages);\r
1809         dws->workqueue = create_singlethread_workqueue(\r
1810                                         dev_name(dws->master->dev.parent));\r
1811         if (dws->workqueue == NULL)\r
1812                 return -EBUSY;\r
1813 \r
1814 \r
1815         return 0;\r
1816 }\r
1817 \r
1818 static int start_queue(struct rk29xx_spi *dws)\r
1819 {\r
1820         unsigned long flags;\r
1821 \r
1822         spin_lock_irqsave(&dws->lock, flags);\r
1823 \r
1824         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1825                 spin_unlock_irqrestore(&dws->lock, flags);\r
1826                 return -EBUSY;\r
1827         }\r
1828 \r
1829         dws->run = QUEUE_RUNNING;\r
1830         dws->cur_msg = NULL;\r
1831         dws->cur_transfer = NULL;\r
1832         dws->cur_chip = NULL;\r
1833         dws->prev_chip = NULL;\r
1834         spin_unlock_irqrestore(&dws->lock, flags);\r
1835 \r
1836         queue_work(dws->workqueue, &dws->pump_messages);\r
1837 \r
1838         return 0;\r
1839 }\r
1840 \r
1841 static int stop_queue(struct rk29xx_spi *dws)\r
1842 {\r
1843         unsigned long flags;\r
1844         unsigned limit = 50;\r
1845         int status = 0;\r
1846 \r
1847         spin_lock_irqsave(&dws->lock, flags);\r
1848         dws->run = QUEUE_STOPPED;\r
1849         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1850                 spin_unlock_irqrestore(&dws->lock, flags);\r
1851                 msleep(10);\r
1852                 spin_lock_irqsave(&dws->lock, flags);\r
1853         }\r
1854 \r
1855         if (!list_empty(&dws->queue) || dws->busy)\r
1856                 status = -EBUSY;\r
1857         spin_unlock_irqrestore(&dws->lock, flags);\r
1858 \r
1859         return status;\r
1860 }\r
1861 \r
1862 static int destroy_queue(struct rk29xx_spi *dws)\r
1863 {\r
1864         int status;\r
1865 \r
1866         status = stop_queue(dws);\r
1867         if (status != 0)\r
1868                 return status;\r
1869         destroy_workqueue(dws->workqueue);\r
1870         return 0;\r
1871 }\r
1872 \r
1873 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1874 static void spi_hw_init(struct rk29xx_spi *dws)\r
1875 {\r
1876         spi_enable_chip(dws, 0);\r
1877         spi_mask_intr(dws, 0xff);\r
1878         \r
1879         /*\r
1880          * Try to detect the FIFO depth if not set by interface driver,\r
1881          * the depth could be from 2 to 32 from HW spec\r
1882          */\r
1883         if (!dws->fifo_len) {\r
1884                 u32 fifo;\r
1885                 for (fifo = 2; fifo <= 31; fifo++) {\r
1886                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1887                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1888                                 break;\r
1889                 }\r
1890 \r
1891                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1892                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1893         }\r
1894         \r
1895         spi_enable_chip(dws, 1);\r
1896         //flush(dws);\r
1897 }\r
1898 \r
1899 /* cpufreq driver support */\r
1900 #ifdef CONFIG_CPU_FREQ\r
1901 \r
1902 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1903 {\r
1904         struct rk29xx_spi *info;\r
1905         unsigned long newclk;\r
1906 \r
1907         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1908         newclk = clk_get_rate(info->clock_spim);\r
1909 \r
1910         return 0;\r
1911 }\r
1912 \r
1913 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1914 {\r
1915         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1916 \r
1917         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1918 }\r
1919 \r
1920 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1921 {\r
1922         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1923 }\r
1924 \r
1925 #else\r
1926 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1927 {\r
1928         return 0;\r
1929 }\r
1930 \r
1931 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1932 {\r
1933 }\r
1934 #endif\r
1935 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1936 {\r
1937         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1938         struct rk29xx_spi   *dws;\r
1939         struct spi_master   *master;\r
1940         int                     irq; \r
1941         int ret;\r
1942         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1943 \r
1944         if (pdata && pdata->io_init) {\r
1945                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1946                 if (ret) {                      \r
1947                         return -ENXIO;  \r
1948                 }\r
1949         }\r
1950         \r
1951         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1952         if (!regs)\r
1953                 return -ENXIO;\r
1954         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1955         if (dmatx_res == NULL) {\r
1956                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1957                 return -ENXIO;\r
1958         }\r
1959 \r
1960         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1961         if (dmarx_res == NULL) {\r
1962                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1963                 return -ENXIO;\r
1964         }\r
1965         irq = platform_get_irq(pdev, 0);\r
1966         if (irq < 0)\r
1967                 return irq;                     \r
1968         /* setup spi core then atmel-specific driver state */\r
1969         ret = -ENOMEM;  \r
1970         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1971         if (!master) {\r
1972                 ret = -ENOMEM;\r
1973                 goto exit;\r
1974         }\r
1975 \r
1976         platform_set_drvdata(pdev, master);\r
1977         dws = spi_master_get_devdata(master);\r
1978         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1979         clk_enable(dws->clock_spim);\r
1980         if (IS_ERR(dws->clock_spim)) {\r
1981                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1982                 return PTR_ERR(dws->clock_spim);\r
1983         }\r
1984 \r
1985         dws->pclk = clk_get(&pdev->dev, "pclk_spi");\r
1986         clk_enable(dws->pclk);\r
1987         \r
1988         mutex_init(&dws->dma_lock);\r
1989         \r
1990         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1991         if (!dws->regs){\r
1992         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1993                 return -EBUSY;\r
1994         }\r
1995         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1996         dws->irq = irq;\r
1997         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1998         dws->master = master;\r
1999         dws->type = SSI_MOTO_SPI;\r
2000         dws->prev_chip = NULL;\r
2001         dws->sfr_start = regs->start;\r
2002         dws->tx_dmach = dmatx_res->start;\r
2003         dws->rx_dmach = dmarx_res->start;\r
2004         dws->dma_inited = 0;  ///0;\r
2005         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
2006         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
2007                         "rk29xx_spim", dws);\r
2008         if (ret < 0) {\r
2009                 dev_err(&master->dev, "can not get IRQ\n");\r
2010                 goto err_free_master;\r
2011         }\r
2012 \r
2013         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
2014         master->bus_num = pdev->id;\r
2015         master->num_chipselect = pdata->num_chipselect;\r
2016         master->dev.platform_data = pdata;\r
2017         master->cleanup = rk29xx_spi_cleanup;\r
2018         master->setup = rk29xx_spi_setup;\r
2019         #if defined(QUICK_TRANSFER)\r
2020         master->transfer = rk29xx_spi_quick_transfer;\r
2021         #else\r
2022         master->transfer = rk29xx_spi_transfer;\r
2023         #endif\r
2024         \r
2025         dws->pdev = pdev;\r
2026         /* Basic HW init */\r
2027         spi_hw_init(dws);\r
2028         flush(dws);\r
2029         /* Initial and start queue */\r
2030         ret = init_queue(dws);\r
2031         if (ret) {\r
2032                 dev_err(&master->dev, "problem initializing queue\n");\r
2033                 goto err_diable_hw;\r
2034         }\r
2035 \r
2036         ret = start_queue(dws);\r
2037         if (ret) {\r
2038                 dev_err(&master->dev, "problem starting queue\n");\r
2039                 goto err_diable_hw;\r
2040         }\r
2041 \r
2042         spi_master_set_devdata(master, dws);\r
2043         ret = spi_register_master(master);\r
2044         if (ret) {\r
2045                 dev_err(&master->dev, "problem registering spi master\n");\r
2046                 goto err_queue_alloc;\r
2047         }\r
2048 \r
2049     ret =rk29xx_spim_cpufreq_register(dws);\r
2050     if (ret < 0) {\r
2051         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
2052         goto err_queue_alloc;\r
2053     }\r
2054         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
2055         mrst_spi_debugfs_init(dws);\r
2056         return 0;\r
2057 \r
2058 err_queue_alloc:\r
2059         destroy_queue(dws);\r
2060 err_diable_hw:\r
2061         spi_enable_chip(dws, 0);\r
2062         free_irq(dws->irq, dws);\r
2063 err_free_master:\r
2064         spi_master_put(master);\r
2065         iounmap(dws->regs);\r
2066 exit:\r
2067         return ret;\r
2068 }\r
2069 \r
2070 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
2071 {\r
2072         struct spi_master *master = platform_get_drvdata(pdev);\r
2073         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2074         int status = 0;\r
2075 \r
2076         if (!dws)\r
2077                 return;\r
2078         rk29xx_spim_cpufreq_deregister(dws);\r
2079         mrst_spi_debugfs_remove(dws);\r
2080 \r
2081         if(dws->buffer_tx_dma)\r
2082         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);\r
2083         if(dws->buffer_rx_dma)\r
2084         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);\r
2085         release_dma(dws);\r
2086 \r
2087         /* Remove the queue */\r
2088         status = destroy_queue(dws);\r
2089         if (status != 0)\r
2090                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
2091                         "complete, message memory not freed\n");\r
2092         \r
2093         clk_disable(dws->clock_spim);\r
2094         clk_put(dws->clock_spim);\r
2095         clk_disable(dws->pclk);\r
2096         clk_put(dws->pclk);\r
2097         spi_enable_chip(dws, 0);\r
2098         /* Disable clk */\r
2099         spi_set_clk(dws, 0);\r
2100         free_irq(dws->irq, dws);\r
2101 \r
2102         /* Disconnect from the SPI framework */\r
2103         spi_unregister_master(dws->master);\r
2104         iounmap(dws->regs);\r
2105 }\r
2106 \r
2107 \r
2108 #ifdef  CONFIG_PM\r
2109 \r
2110 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2111 {\r
2112         struct spi_master *master = platform_get_drvdata(pdev);\r
2113         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2114         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2115         int status;\r
2116         \r
2117         flush(dws);\r
2118         status = stop_queue(dws);\r
2119         if (status != 0)\r
2120                 return status;\r
2121         clk_disable(dws->clock_spim);\r
2122         if (pdata && pdata->io_fix_leakage_bug)\r
2123         {\r
2124                 pdata->io_fix_leakage_bug( );\r
2125         }\r
2126         clk_disable(dws->pclk);\r
2127         return 0;\r
2128 }\r
2129 \r
2130 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2131 {\r
2132         struct spi_master *master = platform_get_drvdata(pdev);\r
2133         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2134         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2135         int ret;\r
2136 \r
2137         clk_enable(dws->pclk);\r
2138         clk_enable(dws->clock_spim);    \r
2139         spi_hw_init(dws);\r
2140         ret = start_queue(dws);\r
2141         if (ret)\r
2142                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2143         if (pdata && pdata->io_resume_leakage_bug)\r
2144         {\r
2145                 pdata->io_resume_leakage_bug( ); \r
2146         }\r
2147         return ret;\r
2148 }\r
2149 \r
2150 #else\r
2151 #define rk29xx_spim_suspend     NULL\r
2152 #define rk29xx_spim_resume      NULL\r
2153 #endif\r
2154 \r
2155 static struct platform_driver rk29xx_platform_spim_driver = {\r
2156         .remove         = __exit_p(rk29xx_spim_remove),\r
2157         .driver         = {\r
2158                 .name   = "rk29xx_spim",\r
2159                 .owner  = THIS_MODULE,\r
2160         },\r
2161         .suspend        = rk29xx_spim_suspend,\r
2162         .resume         = rk29xx_spim_resume,\r
2163 };\r
2164 \r
2165 static int __init rk29xx_spim_init(void)\r
2166 {\r
2167         int ret;\r
2168         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2169         return ret;\r
2170 }\r
2171 \r
2172 static void __exit rk29xx_spim_exit(void)\r
2173 {\r
2174         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2175 }\r
2176 \r
2177 arch_initcall_sync(rk29xx_spim_init);\r
2178 module_exit(rk29xx_spim_exit);\r
2179 \r
2180 MODULE_AUTHOR("www.rock-chips.com");\r
2181 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2182 MODULE_LICENSE("GPL");;\r
2183 \r