2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/interrupt.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi_bitbang.h>
31 #include <linux/slab.h>
34 #include <mach/edma.h>
36 #define SPI_NO_RESOURCE ((resource_size_t)-1)
38 #define SPI_MAX_CHIPSELECT 2
40 #define CS_DEFAULT 0xFF
42 #define SPIFMT_PHASE_MASK BIT(16)
43 #define SPIFMT_POLARITY_MASK BIT(17)
44 #define SPIFMT_DISTIMER_MASK BIT(18)
45 #define SPIFMT_SHIFTDIR_MASK BIT(20)
46 #define SPIFMT_WAITENA_MASK BIT(21)
47 #define SPIFMT_PARITYENA_MASK BIT(22)
48 #define SPIFMT_ODD_PARITY_MASK BIT(23)
49 #define SPIFMT_WDELAY_MASK 0x3f000000u
50 #define SPIFMT_WDELAY_SHIFT 24
51 #define SPIFMT_PRESCALE_SHIFT 8
54 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
55 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
56 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
57 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
59 #define SPIINT_MASKALL 0x0101035F
60 #define SPIINT_MASKINT 0x0000015F
61 #define SPI_INTLVL_1 0x000001FF
62 #define SPI_INTLVL_0 0x00000000
64 /* SPIDAT1 (upper 16 bit defines) */
65 #define SPIDAT1_CSHOLD_MASK BIT(12)
68 #define SPIGCR1_CLKMOD_MASK BIT(1)
69 #define SPIGCR1_MASTER_MASK BIT(0)
70 #define SPIGCR1_POWERDOWN_MASK BIT(8)
71 #define SPIGCR1_LOOPBACK_MASK BIT(16)
72 #define SPIGCR1_SPIENA_MASK BIT(24)
75 #define SPIBUF_TXFULL_MASK BIT(29)
76 #define SPIBUF_RXEMPTY_MASK BIT(31)
79 #define SPIDELAY_C2TDELAY_SHIFT 24
80 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
81 #define SPIDELAY_T2CDELAY_SHIFT 16
82 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
83 #define SPIDELAY_T2EDELAY_SHIFT 8
84 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
85 #define SPIDELAY_C2EDELAY_SHIFT 0
86 #define SPIDELAY_C2EDELAY_MASK 0xFF
89 #define SPIFLG_DLEN_ERR_MASK BIT(0)
90 #define SPIFLG_TIMEOUT_MASK BIT(1)
91 #define SPIFLG_PARERR_MASK BIT(2)
92 #define SPIFLG_DESYNC_MASK BIT(3)
93 #define SPIFLG_BITERR_MASK BIT(4)
94 #define SPIFLG_OVRRUN_MASK BIT(6)
95 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
96 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
97 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
98 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
101 #define SPIINT_DMA_REQ_EN BIT(16)
103 /* SPI Controller registers */
112 #define SPIDELAY 0x48
116 /* We have 2 DMA channels per CS, one for RX and one for TX */
117 struct davinci_spi_dma {
120 int dummy_param_slot;
121 enum dma_event_q eventq;
124 /* SPI Controller driver's private data. */
126 struct spi_bitbang bitbang;
130 resource_size_t pbase;
133 struct completion done;
137 #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1)
138 u8 rx_tmp_buf[SPI_TMP_BUFSZ];
141 struct davinci_spi_dma dma;
142 struct davinci_spi_platform_data *pdata;
144 void (*get_rx)(u32 rx_data, struct davinci_spi *);
145 u32 (*get_tx)(struct davinci_spi *);
147 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
150 static struct davinci_spi_config davinci_spi_default_cfg;
152 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
161 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
170 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
174 const u8 *tx = dspi->tx;
181 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
185 const u16 *tx = dspi->tx;
192 static inline void set_io_bits(void __iomem *addr, u32 bits)
194 u32 v = ioread32(addr);
200 static inline void clear_io_bits(void __iomem *addr, u32 bits)
202 u32 v = ioread32(addr);
209 * Interface to control the chip select signal
211 static void davinci_spi_chipselect(struct spi_device *spi, int value)
213 struct davinci_spi *dspi;
214 struct davinci_spi_platform_data *pdata;
215 u8 chip_sel = spi->chip_select;
216 u16 spidat1 = CS_DEFAULT;
217 bool gpio_chipsel = false;
219 dspi = spi_master_get_devdata(spi->master);
222 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
223 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
227 * Board specific chip select logic decides the polarity and cs
228 * line for the controller
231 if (value == BITBANG_CS_ACTIVE)
232 gpio_set_value(pdata->chip_sel[chip_sel], 0);
234 gpio_set_value(pdata->chip_sel[chip_sel], 1);
236 if (value == BITBANG_CS_ACTIVE) {
237 spidat1 |= SPIDAT1_CSHOLD_MASK;
238 spidat1 &= ~(0x1 << chip_sel);
241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
246 * davinci_spi_get_prescale - Calculates the correct prescale value
247 * @maxspeed_hz: the maximum rate the SPI clock can run at
249 * This function calculates the prescale value that generates a clock rate
250 * less than or equal to the specified maximum.
252 * Returns: calculated prescale - 1 for easy programming into SPI registers
253 * or negative error number if valid prescalar cannot be updated.
255 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
260 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
262 if (ret < 3 || ret > 256)
269 * davinci_spi_setup_transfer - This functions will determine transfer method
270 * @spi: spi device on which data transfer to be done
271 * @t: spi transfer in which transfer info is filled
273 * This function determines data transfer method (8/16/32 bit transfer).
274 * It will also set the SPI Clock Control register according to
275 * SPI slave device freq.
277 static int davinci_spi_setup_transfer(struct spi_device *spi,
278 struct spi_transfer *t)
281 struct davinci_spi *dspi;
282 struct davinci_spi_config *spicfg;
283 u8 bits_per_word = 0;
284 u32 hz = 0, spifmt = 0, prescale = 0;
286 dspi = spi_master_get_devdata(spi->master);
287 spicfg = (struct davinci_spi_config *)spi->controller_data;
289 spicfg = &davinci_spi_default_cfg;
292 bits_per_word = t->bits_per_word;
296 /* if bits_per_word is not set then set it default */
298 bits_per_word = spi->bits_per_word;
301 * Assign function pointer to appropriate transfer method
302 * 8bit, 16bit or 32bit transfer
304 if (bits_per_word <= 8 && bits_per_word >= 2) {
305 dspi->get_rx = davinci_spi_rx_buf_u8;
306 dspi->get_tx = davinci_spi_tx_buf_u8;
307 dspi->bytes_per_word[spi->chip_select] = 1;
308 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
309 dspi->get_rx = davinci_spi_rx_buf_u16;
310 dspi->get_tx = davinci_spi_tx_buf_u16;
311 dspi->bytes_per_word[spi->chip_select] = 2;
316 hz = spi->max_speed_hz;
318 /* Set up SPIFMTn register, unique to this chipselect. */
320 prescale = davinci_spi_get_prescale(dspi, hz);
324 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
326 if (spi->mode & SPI_LSB_FIRST)
327 spifmt |= SPIFMT_SHIFTDIR_MASK;
329 if (spi->mode & SPI_CPOL)
330 spifmt |= SPIFMT_POLARITY_MASK;
332 if (!(spi->mode & SPI_CPHA))
333 spifmt |= SPIFMT_PHASE_MASK;
336 * Version 1 hardware supports two basic SPI modes:
337 * - Standard SPI mode uses 4 pins, with chipselect
338 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
339 * (distinct from SPI_3WIRE, with just one data wire;
340 * or similar variants without MOSI or without MISO)
342 * Version 2 hardware supports an optional handshaking signal,
343 * so it can support two more modes:
344 * - 5 pin SPI variant is standard SPI plus SPI_READY
345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
348 if (dspi->version == SPI_VERSION_2) {
352 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
353 & SPIFMT_WDELAY_MASK);
355 if (spicfg->odd_parity)
356 spifmt |= SPIFMT_ODD_PARITY_MASK;
358 if (spicfg->parity_enable)
359 spifmt |= SPIFMT_PARITYENA_MASK;
361 if (spicfg->timer_disable) {
362 spifmt |= SPIFMT_DISTIMER_MASK;
364 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
365 & SPIDELAY_C2TDELAY_MASK;
366 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
367 & SPIDELAY_T2CDELAY_MASK;
370 if (spi->mode & SPI_READY) {
371 spifmt |= SPIFMT_WAITENA_MASK;
372 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
373 & SPIDELAY_T2EDELAY_MASK;
374 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
375 & SPIDELAY_C2EDELAY_MASK;
378 iowrite32(delay, dspi->base + SPIDELAY);
381 iowrite32(spifmt, dspi->base + SPIFMT0);
387 * davinci_spi_setup - This functions will set default transfer method
388 * @spi: spi device on which data transfer to be done
390 * This functions sets the default transfer method.
392 static int davinci_spi_setup(struct spi_device *spi)
395 struct davinci_spi *dspi;
396 struct davinci_spi_platform_data *pdata;
398 dspi = spi_master_get_devdata(spi->master);
401 /* if bits per word length is zero then set it default 8 */
402 if (!spi->bits_per_word)
403 spi->bits_per_word = 8;
405 if (!(spi->mode & SPI_NO_CS)) {
406 if ((pdata->chip_sel == NULL) ||
407 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
408 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
412 if (spi->mode & SPI_READY)
413 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
415 if (spi->mode & SPI_LOOP)
416 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
418 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
423 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
425 struct device *sdev = dspi->bitbang.master->dev.parent;
427 if (int_status & SPIFLG_TIMEOUT_MASK) {
428 dev_dbg(sdev, "SPI Time-out Error\n");
431 if (int_status & SPIFLG_DESYNC_MASK) {
432 dev_dbg(sdev, "SPI Desynchronization Error\n");
435 if (int_status & SPIFLG_BITERR_MASK) {
436 dev_dbg(sdev, "SPI Bit error\n");
440 if (dspi->version == SPI_VERSION_2) {
441 if (int_status & SPIFLG_DLEN_ERR_MASK) {
442 dev_dbg(sdev, "SPI Data Length Error\n");
445 if (int_status & SPIFLG_PARERR_MASK) {
446 dev_dbg(sdev, "SPI Parity Error\n");
449 if (int_status & SPIFLG_OVRRUN_MASK) {
450 dev_dbg(sdev, "SPI Data Overrun error\n");
453 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
454 dev_dbg(sdev, "SPI Buffer Init Active\n");
463 * davinci_spi_process_events - check for and handle any SPI controller events
464 * @dspi: the controller data
466 * This function will check the SPIFLG register and handle any events that are
469 static int davinci_spi_process_events(struct davinci_spi *dspi)
471 u32 buf, status, errors = 0, spidat1;
473 buf = ioread32(dspi->base + SPIBUF);
475 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
476 dspi->get_rx(buf & 0xFFFF, dspi);
480 status = ioread32(dspi->base + SPIFLG);
482 if (unlikely(status & SPIFLG_ERROR_MASK)) {
483 errors = status & SPIFLG_ERROR_MASK;
487 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
488 spidat1 = ioread32(dspi->base + SPIDAT1);
491 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
492 iowrite32(spidat1, dspi->base + SPIDAT1);
499 static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
501 struct davinci_spi *dspi = data;
502 struct davinci_spi_dma *dma = &dspi->dma;
506 if (status == DMA_COMPLETE) {
507 if (lch == dma->rx_channel)
509 if (lch == dma->tx_channel)
513 if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
514 complete(&dspi->done);
518 * davinci_spi_bufs - functions which will handle transfer data
519 * @spi: spi device on which data transfer to be done
520 * @t: spi transfer in which transfer info is filled
522 * This function will put data to be transferred into data register
523 * of SPI controller and then wait until the completion will be marked
524 * by the IRQ Handler.
526 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
528 struct davinci_spi *dspi;
530 u32 tx_data, spidat1;
532 struct davinci_spi_config *spicfg;
533 struct davinci_spi_platform_data *pdata;
534 unsigned uninitialized_var(rx_buf_count);
537 dspi = spi_master_get_devdata(spi->master);
539 spicfg = (struct davinci_spi_config *)spi->controller_data;
541 spicfg = &davinci_spi_default_cfg;
542 sdev = dspi->bitbang.master->dev.parent;
544 /* convert len to words based on bits_per_word */
545 data_type = dspi->bytes_per_word[spi->chip_select];
547 dspi->tx = t->tx_buf;
548 dspi->rx = t->rx_buf;
549 dspi->wcount = t->len / data_type;
550 dspi->rcount = dspi->wcount;
552 spidat1 = ioread32(dspi->base + SPIDAT1);
554 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
555 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
557 INIT_COMPLETION(dspi->done);
559 if (spicfg->io_type == SPI_IO_TYPE_INTR)
560 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
562 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
563 /* start the transfer */
565 tx_data = dspi->get_tx(dspi);
566 spidat1 &= 0xFFFF0000;
567 spidat1 |= tx_data & 0xFFFF;
568 iowrite32(spidat1, dspi->base + SPIDAT1);
570 struct davinci_spi_dma *dma;
571 unsigned long tx_reg, rx_reg;
572 struct edmacc_param param;
577 tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
578 rx_reg = (unsigned long)dspi->pbase + SPIBUF;
583 * If there is transmit data, map the transmit buffer, set it
584 * as the source of data and set the source B index to data
585 * size. If there is no transmit data, set the transmit register
586 * as the source of data, and set the source B index to zero.
588 * The destination is always the transmit register itself. And
589 * the destination never increments.
593 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
594 dspi->wcount, DMA_TO_DEVICE);
595 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
596 dev_dbg(sdev, "Unable to DMA map %d bytes"
597 "TX buffer\n", dspi->wcount);
602 param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
603 param.src = t->tx_buf ? t->tx_dma : tx_reg;
604 param.a_b_cnt = dspi->wcount << 16 | data_type;
606 param.src_dst_bidx = t->tx_buf ? data_type : 0;
607 param.link_bcntrld = 0xffff;
608 param.src_dst_cidx = 0;
610 edma_write_slot(dma->tx_channel, ¶m);
611 edma_link(dma->tx_channel, dma->dummy_param_slot);
616 * If there is receive buffer, use it to receive data. If there
617 * is none provided, use a temporary receive buffer. Set the
618 * destination B index to 0 so effectively only one byte is used
619 * in the temporary buffer (address does not increment).
621 * The source of receive data is the receive data register. The
622 * source address never increments.
627 rx_buf_count = dspi->rcount;
629 rx_buf = dspi->rx_tmp_buf;
630 rx_buf_count = sizeof(dspi->rx_tmp_buf);
633 t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
635 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
636 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
639 dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
644 param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
646 param.a_b_cnt = dspi->rcount << 16 | data_type;
647 param.dst = t->rx_dma;
648 param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
649 param.link_bcntrld = 0xffff;
650 param.src_dst_cidx = 0;
652 edma_write_slot(dma->rx_channel, ¶m);
654 if (pdata->cshold_bug)
655 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
657 edma_start(dma->rx_channel);
658 edma_start(dma->tx_channel);
659 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
662 /* Wait for the transfer to complete */
663 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
664 wait_for_completion_interruptible(&(dspi->done));
666 while (dspi->rcount > 0 || dspi->wcount > 0) {
667 errors = davinci_spi_process_events(dspi);
674 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
675 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
678 dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
681 dma_unmap_single(NULL, t->rx_dma, rx_buf_count,
684 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
687 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
688 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
691 * Check for bit error, desync error,parity error,timeout error and
692 * receive overflow errors
695 ret = davinci_spi_check_error(dspi, errors);
696 WARN(!ret, "%s: error reported but no error found!\n",
697 dev_name(&spi->dev));
701 if (dspi->rcount != 0 || dspi->wcount != 0) {
702 dev_err(sdev, "SPI data transfer error\n");
710 * davinci_spi_irq - Interrupt handler for SPI Master Controller
711 * @irq: IRQ number for this SPI Master
712 * @context_data: structure for SPI Master controller davinci_spi
714 * ISR will determine that interrupt arrives either for READ or WRITE command.
715 * According to command it will do the appropriate action. It will check
716 * transfer length and if it is not zero then dispatch transfer command again.
717 * If transfer length is zero then it will indicate the COMPLETION so that
718 * davinci_spi_bufs function can go ahead.
720 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
722 struct davinci_spi *dspi = data;
725 status = davinci_spi_process_events(dspi);
726 if (unlikely(status != 0))
727 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
729 if ((!dspi->rcount && !dspi->wcount) || status)
730 complete(&dspi->done);
735 static int davinci_spi_request_dma(struct davinci_spi *dspi)
738 struct davinci_spi_dma *dma = &dspi->dma;
740 r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
743 pr_err("Unable to request DMA channel for SPI RX\n");
748 r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
751 pr_err("Unable to request DMA channel for SPI TX\n");
756 r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
758 pr_err("Unable to request SPI TX DMA param slot\n");
762 dma->dummy_param_slot = r;
763 edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
767 edma_free_channel(dma->tx_channel);
769 edma_free_channel(dma->rx_channel);
775 * davinci_spi_probe - probe function for SPI Master Controller
776 * @pdev: platform_device structure which contains plateform specific data
778 * According to Linux Device Model this function will be invoked by Linux
779 * with platform_device struct which contains the device specific info.
780 * This function will map the SPI controller's memory, register IRQ,
781 * Reset SPI controller and setting its registers to default value.
782 * It will invoke spi_bitbang_start to create work queue so that client driver
783 * can register transfer method to work queue.
785 static int davinci_spi_probe(struct platform_device *pdev)
787 struct spi_master *master;
788 struct davinci_spi *dspi;
789 struct davinci_spi_platform_data *pdata;
790 struct resource *r, *mem;
791 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
792 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
796 pdata = pdev->dev.platform_data;
802 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
803 if (master == NULL) {
808 dev_set_drvdata(&pdev->dev, master);
810 dspi = spi_master_get_devdata(master);
816 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
822 dspi->pbase = r->start;
825 mem = request_mem_region(r->start, resource_size(r), pdev->name);
831 dspi->base = ioremap(r->start, resource_size(r));
832 if (dspi->base == NULL) {
837 dspi->irq = platform_get_irq(pdev, 0);
838 if (dspi->irq <= 0) {
843 ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
848 dspi->bitbang.master = spi_master_get(master);
849 if (dspi->bitbang.master == NULL) {
854 dspi->clk = clk_get(&pdev->dev, NULL);
855 if (IS_ERR(dspi->clk)) {
859 clk_enable(dspi->clk);
861 master->bus_num = pdev->id;
862 master->num_chipselect = pdata->num_chipselect;
863 master->setup = davinci_spi_setup;
865 dspi->bitbang.chipselect = davinci_spi_chipselect;
866 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
868 dspi->version = pdata->version;
870 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
871 if (dspi->version == SPI_VERSION_2)
872 dspi->bitbang.flags |= SPI_READY;
874 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
876 dma_rx_chan = r->start;
877 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
879 dma_tx_chan = r->start;
881 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
882 if (dma_rx_chan != SPI_NO_RESOURCE &&
883 dma_tx_chan != SPI_NO_RESOURCE) {
884 dspi->dma.rx_channel = dma_rx_chan;
885 dspi->dma.tx_channel = dma_tx_chan;
886 dspi->dma.eventq = pdata->dma_event_q;
888 ret = davinci_spi_request_dma(dspi);
892 dev_info(&pdev->dev, "DMA: supported\n");
893 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
894 "event queue: %d\n", dma_rx_chan, dma_tx_chan,
898 dspi->get_rx = davinci_spi_rx_buf_u8;
899 dspi->get_tx = davinci_spi_tx_buf_u8;
901 init_completion(&dspi->done);
903 /* Reset In/OUT SPI module */
904 iowrite32(0, dspi->base + SPIGCR0);
906 iowrite32(1, dspi->base + SPIGCR0);
908 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
909 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
910 iowrite32(spipc0, dspi->base + SPIPC0);
912 /* initialize chip selects */
913 if (pdata->chip_sel) {
914 for (i = 0; i < pdata->num_chipselect; i++) {
915 if (pdata->chip_sel[i] != SPI_INTERN_CS)
916 gpio_direction_output(pdata->chip_sel[i], 1);
920 if (pdata->intr_line)
921 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
923 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
925 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
927 /* master mode default */
928 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
929 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
930 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
932 ret = spi_bitbang_start(&dspi->bitbang);
936 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
941 edma_free_channel(dspi->dma.tx_channel);
942 edma_free_channel(dspi->dma.rx_channel);
943 edma_free_slot(dspi->dma.dummy_param_slot);
945 clk_disable(dspi->clk);
948 spi_master_put(master);
950 free_irq(dspi->irq, dspi);
954 release_mem_region(dspi->pbase, resource_size(r));
962 * davinci_spi_remove - remove function for SPI Master Controller
963 * @pdev: platform_device structure which contains plateform specific data
965 * This function will do the reverse action of davinci_spi_probe function
966 * It will free the IRQ and SPI controller's memory region.
967 * It will also call spi_bitbang_stop to destroy the work queue which was
968 * created by spi_bitbang_start.
970 static int __exit davinci_spi_remove(struct platform_device *pdev)
972 struct davinci_spi *dspi;
973 struct spi_master *master;
976 master = dev_get_drvdata(&pdev->dev);
977 dspi = spi_master_get_devdata(master);
979 spi_bitbang_stop(&dspi->bitbang);
981 clk_disable(dspi->clk);
983 spi_master_put(master);
984 free_irq(dspi->irq, dspi);
986 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
987 release_mem_region(dspi->pbase, resource_size(r));
992 static struct platform_driver davinci_spi_driver = {
994 .name = "spi_davinci",
995 .owner = THIS_MODULE,
997 .remove = __exit_p(davinci_spi_remove),
1000 static int __init davinci_spi_init(void)
1002 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1004 module_init(davinci_spi_init);
1006 static void __exit davinci_spi_exit(void)
1008 platform_driver_unregister(&davinci_spi_driver);
1010 module_exit(davinci_spi_exit);
1012 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1013 MODULE_LICENSE("GPL");