drivers/soc/rockchip/rk_fiq_debugger.c

   1 /*
   2  * drivers/soc/rockchip/rk_fiq_debugger.c
   3  *
   4  * Serial Debugger Interface for Rockchip
   5  *
   6  * Copyright (C) 2012 ROCKCHIP, Inc.
   7  * Copyright (C) 2008 Google, Inc.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <stdarg.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/irq.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/slab.h>
  31 #include <linux/stacktrace.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/kfifo.h>
  34 #include <linux/kthread.h>
  35 #include <linux/sched/rt.h>
  36 #include <../drivers/staging/android/fiq_debugger/fiq_debugger.h>
  37 #include <linux/irqchip/arm-gic.h>
  38 #include <linux/clk.h>
  39 #include <linux/soc/rockchip/rk_fiq_debugger.h>
  40
  41 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
  42 #include "linux/rockchip/psci.h"
  43 #endif
  44
  45 #define UART_USR        0x1f    /* In: UART Status Register */
  46 #define UART_USR_RX_FIFO_FULL           0x10 /* Receive FIFO full */
  47 #define UART_USR_RX_FIFO_NOT_EMPTY      0x08 /* Receive FIFO not empty */
  48 #define UART_USR_TX_FIFO_EMPTY          0x04 /* Transmit FIFO empty */
  49 #define UART_USR_TX_FIFO_NOT_FULL       0x02 /* Transmit FIFO not full */
  50 #define UART_USR_BUSY                   0x01 /* UART busy indicator */
  51
  52 struct rk_fiq_debugger {
  53         int irq;
  54         int baudrate;
  55         struct fiq_debugger_pdata pdata;
  56         void __iomem *debug_port_base;
  57         bool break_seen;
  58 #ifdef CONFIG_RK_CONSOLE_THREAD
  59         struct task_struct *console_task;
  60 #endif
  61 };
  62
  63 static inline void rk_fiq_write(struct rk_fiq_debugger *t,
  64         unsigned int val, unsigned int off)
  65 {
  66         __raw_writel(val, t->debug_port_base + off * 4);
  67 }
  68
  69 static inline unsigned int rk_fiq_read(struct rk_fiq_debugger *t,
  70         unsigned int off)
  71 {
  72         return __raw_readl(t->debug_port_base + off * 4);
  73 }
  74
  75 static inline unsigned int rk_fiq_read_lsr(struct rk_fiq_debugger *t)
  76 {
  77         unsigned int lsr;
  78
  79         lsr = rk_fiq_read(t, UART_LSR);
  80         if (lsr & UART_LSR_BI)
  81                 t->break_seen = true;
  82
  83         return lsr;
  84 }
  85
  86 static int debug_port_init(struct platform_device *pdev)
  87 {
  88         int dll = 0, dlm = 0;
  89         struct rk_fiq_debugger *t;
  90
  91         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
  92
  93         if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
  94                 (void)rk_fiq_read(t, UART_RX);
  95
  96         switch (t->baudrate) {
  97         case 1500000:
  98                 dll = 0x1;
  99                 break;
 100         case 115200:
 101         default:
 102                 dll = 0xd;
 103                 break;
 104         }
 105
 106         rk_fiq_write(t, 0x83, UART_LCR);
 107         /* set baud rate */
 108         rk_fiq_write(t, dll, UART_DLL);
 109         rk_fiq_write(t, dlm, UART_DLM);
 110         rk_fiq_write(t, 0x03, UART_LCR);
 111
 112         /* enable rx and lsr interrupt */
 113         rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
 114         /* interrupt on every character when receive,but we can enable fifo for TX
 115         I found that if we enable the RX fifo, some problem may vanish such as when
 116         you continuously input characters in the command line the uart irq may be disable
 117         because of the uart irq is served when CPU is at IRQ exception,but it is
 118         found unregistered, so it is disable.
 119         hhb@rock-chips.com */
 120         rk_fiq_write(t, 0xc1, UART_FCR);
 121
 122         return 0;
 123 }
 124
 125 static int debug_getc(struct platform_device *pdev)
 126 {
 127         unsigned int lsr;
 128         struct rk_fiq_debugger *t;
 129         unsigned int temp;
 130         static unsigned int n;
 131         static char buf[32];
 132
 133         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 134
 135         lsr = rk_fiq_read_lsr(t);
 136
 137         if (lsr & UART_LSR_BI || t->break_seen) {
 138                 t->break_seen = false;
 139                 return FIQ_DEBUGGER_NO_CHAR;
 140         }
 141
 142         if (lsr & UART_LSR_DR) {
 143                 temp = rk_fiq_read(t, UART_RX);
 144                 buf[n & 0x1f] = temp;
 145                 n++;
 146                 if (temp == 'q' && n > 2) {
 147                         if ((buf[(n - 2) & 0x1f] == 'i') &&
 148                             (buf[(n - 3) & 0x1f] == 'f'))
 149                                 return FIQ_DEBUGGER_BREAK;
 150                         else
 151                                 return temp;
 152                 } else {
 153                         return temp;
 154                 }
 155         }
 156
 157         return FIQ_DEBUGGER_NO_CHAR;
 158 }
 159
 160 static void debug_putc(struct platform_device *pdev, unsigned int c)
 161 {
 162         struct rk_fiq_debugger *t;
 163
 164         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 165
 166         while (!(rk_fiq_read(t, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))
 167                 cpu_relax();
 168         rk_fiq_write(t, c, UART_TX);
 169 }
 170
 171 static void debug_flush(struct platform_device *pdev)
 172 {
 173         struct rk_fiq_debugger *t;
 174         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 175
 176         while (!(rk_fiq_read_lsr(t) & UART_LSR_TEMT))
 177                 cpu_relax();
 178 }
 179
 180 static int uart_dev_resume(struct platform_device *pdev)
 181 {
 182         debug_port_init(pdev);
 183         return 0;
 184 }
 185
 186 #ifdef CONFIG_RK_CONSOLE_THREAD
 187 #define FIFO_SIZE SZ_64K
 188 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);
 189 static bool console_thread_stop;
 190
 191 static int console_thread(void *data)
 192 {
 193         struct platform_device *pdev = data;
 194         struct rk_fiq_debugger *t;
 195         unsigned char c;
 196         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 197
 198         while (1) {
 199                 set_current_state(TASK_INTERRUPTIBLE);
 200                 schedule();
 201                 if (kthread_should_stop())
 202                         break;
 203                 set_current_state(TASK_RUNNING);
 204                 while (!console_thread_stop && kfifo_get(&fifo, &c))
 205                         debug_putc(pdev, c);
 206                 if (!console_thread_stop)
 207                         debug_flush(pdev);
 208         }
 209
 210         return 0;
 211 }
 212
 213 static void console_write(struct platform_device *pdev, const char *s, unsigned int count)
 214 {
 215         unsigned int fifo_count = FIFO_SIZE;
 216         unsigned char c, r = '\r';
 217         struct rk_fiq_debugger *t;
 218         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 219
 220         if (console_thread_stop ||
 221             oops_in_progress ||
 222             system_state == SYSTEM_HALT ||
 223             system_state == SYSTEM_POWER_OFF ||
 224             system_state == SYSTEM_RESTART) {
 225                 if (!console_thread_stop) {
 226                         console_thread_stop = true;
 227                         smp_wmb();
 228                         debug_flush(pdev);
 229                         while (fifo_count-- && kfifo_get(&fifo, &c))
 230                                 debug_putc(pdev, c);
 231                 }
 232                 while (count--) {
 233                         if (*s == '\n') {
 234                                 debug_putc(pdev, r);
 235                         }
 236                         debug_putc(pdev, *s++);
 237                 }
 238                 debug_flush(pdev);
 239         } else {
 240                 while (count--) {
 241                         if (*s == '\n') {
 242                                 kfifo_put(&fifo, r);
 243                         }
 244                         kfifo_put(&fifo, *s++);
 245                 }
 246                 wake_up_process(t->console_task);
 247         }
 248 }
 249 #endif
 250
 251
 252 static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
 253 {
 254         if (on)
 255                 enable_irq(irq);
 256         else
 257                 disable_irq(irq);
 258 }
 259
 260 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 261 static struct pt_regs fiq_pt_regs;
 262
 263 static void rk_fiq_debugger_switch_cpu(struct platform_device *pdev,
 264                                        unsigned int cpu)
 265 {
 266         psci_fiq_debugger_switch_cpu(cpu);
 267 }
 268
 269 static void rk_fiq_debugger_enable_debug(struct platform_device *pdev, bool val)
 270 {
 271         psci_fiq_debugger_enable_debug(val);
 272 }
 273
 274 static void fiq_debugger_uart_irq_tf(void *reg_base, u64 sp_el1)
 275 {
 276         memcpy(&fiq_pt_regs, reg_base, 8*31);
 277
 278         memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
 279         if (fiq_pt_regs.pstate & 0x10)
 280                 memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8);
 281         else
 282                 fiq_pt_regs.sp = sp_el1;
 283
 284         memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
 285
 286         fiq_debugger_fiq(&fiq_pt_regs);
 287 }
 288
 289 static int fiq_debugger_uart_dev_resume(struct platform_device *pdev)
 290 {
 291         struct rk_fiq_debugger *t;
 292
 293         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 294         psci_fiq_debugger_uart_irq_tf_init(t->irq, fiq_debugger_uart_irq_tf);
 295         return 0;
 296 }
 297 #endif
 298
 299 static int rk_fiq_debugger_id;
 300
 301 void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq,
 302                           int wakeup_irq, unsigned int baudrate)
 303 {
 304         struct rk_fiq_debugger *t = NULL;
 305         struct platform_device *pdev = NULL;
 306         struct resource *res = NULL;
 307         int res_count = 0;
 308 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 309         /* tf means trust firmware*/
 310         int tf_ver = 0;
 311         bool tf_fiq_sup = false;
 312 #endif
 313
 314         if (!base) {
 315                 pr_err("Invalid fiq debugger uart base\n");
 316                 return;
 317         }
 318
 319         t = kzalloc(sizeof(struct rk_fiq_debugger), GFP_KERNEL);
 320         if (!t) {
 321                 pr_err("Failed to allocate for fiq debugger\n");
 322                 return;
 323         }
 324
 325         t->irq = irq;
 326         t->baudrate = baudrate;
 327         t->pdata.uart_init = debug_port_init;
 328         t->pdata.uart_getc = debug_getc;
 329         t->pdata.uart_putc = debug_putc;
 330         t->pdata.uart_dev_resume = uart_dev_resume;
 331 #ifndef CONFIG_RK_CONSOLE_THREAD
 332         t->pdata.uart_flush = debug_flush;
 333 #endif
 334         t->pdata.fiq_enable = fiq_enable;
 335         t->pdata.force_irq = NULL;  //force_irq;
 336         t->debug_port_base = base;
 337
 338         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
 339         if (!res) {
 340                 pr_err("Failed to alloc fiq debugger resources\n");
 341                 goto out2;
 342         }
 343
 344         pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
 345         if (!pdev) {
 346                 pr_err("Failed to alloc fiq debugger platform device\n");
 347                 goto out3;
 348         };
 349
 350 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 351         tf_ver = rockchip_psci_smc_get_tf_ver();
 352
 353         if (tf_ver >= 0x00010005)
 354                 tf_fiq_sup = true;
 355         else
 356                 tf_fiq_sup = false;
 357
 358         if (tf_fiq_sup && (signal_irq > 0)) {
 359                 t->pdata.switch_cpu = rk_fiq_debugger_switch_cpu;
 360                 t->pdata.enable_debug = rk_fiq_debugger_enable_debug;
 361                 t->pdata.uart_dev_resume = fiq_debugger_uart_dev_resume;
 362                 psci_fiq_debugger_uart_irq_tf_init(irq,
 363                                                    fiq_debugger_uart_irq_tf);
 364         } else {
 365                 t->pdata.switch_cpu = NULL;
 366                 t->pdata.enable_debug = NULL;
 367         }
 368 #endif
 369
 370         if (irq > 0) {
 371                 res[0].flags = IORESOURCE_IRQ;
 372                 res[0].start = irq;
 373                 res[0].end = irq;
 374 #if defined(CONFIG_FIQ_GLUE)
 375                 if (signal_irq > 0)
 376                         res[0].name = "fiq";
 377                 else
 378                         res[0].name = "uart_irq";
 379 #elif defined(CONFIG_FIQ_DEBUGGER_EL3_TO_EL1)
 380                 if (tf_fiq_sup && (signal_irq > 0))
 381                         res[0].name = "fiq";
 382                 else
 383                         res[0].name = "uart_irq";
 384 #else
 385                 res[0].name = "uart_irq";
 386 #endif
 387                 res_count++;
 388         }
 389
 390         if (signal_irq > 0) {
 391                 res[1].flags = IORESOURCE_IRQ;
 392                 res[1].start = signal_irq;
 393                 res[1].end = signal_irq;
 394                 res[1].name = "signal";
 395                 res_count++;
 396         }
 397
 398         if (wakeup_irq > 0) {
 399                 res[2].flags = IORESOURCE_IRQ;
 400                 res[2].start = wakeup_irq;
 401                 res[2].end = wakeup_irq;
 402                 res[2].name = "wakeup";
 403                 res_count++;
 404         }
 405
 406 #ifdef CONFIG_RK_CONSOLE_THREAD
 407         t->console_task = kthread_create(console_thread, pdev, "kconsole");
 408         if (!IS_ERR(t->console_task))
 409                 t->pdata.console_write = console_write;
 410 #endif
 411
 412         pdev->name = "fiq_debugger";
 413         pdev->id = rk_fiq_debugger_id++;
 414         pdev->dev.platform_data = &t->pdata;
 415         pdev->resource = res;
 416         pdev->num_resources = res_count;
 417         if (platform_device_register(pdev)) {
 418                 pr_err("Failed to register fiq debugger\n");
 419                 goto out4;
 420         }
 421         return;
 422
 423 out4:
 424         kfree(pdev);
 425 out3:
 426         kfree(res);
 427 out2:
 428         kfree(t);
 429 }
 430
 431 static const struct of_device_id ids[] __initconst = {
 432         { .compatible = "rockchip,fiq-debugger" },
 433         {}
 434 };
 435
 436 static int __init rk_fiq_debugger_init(void) {
 437
 438         void __iomem *base;
 439         struct device_node *np;
 440         unsigned int id, serial_id, ok = 0;
 441         unsigned int irq, signal_irq = 0, wake_irq = 0;
 442         unsigned int baudrate = 0, irq_mode = 0;
 443         struct clk *clk;
 444         struct clk *pclk;
 445
 446         np = of_find_matching_node(NULL, ids);
 447
 448         if (!np) {
 449                 pr_err("fiq-debugger is missing in device tree!\n");
 450                 return -ENODEV;
 451         }
 452
 453         if (!of_device_is_available(np)) {
 454                 pr_err("fiq-debugger is disabled in device tree\n");
 455                 return -ENODEV;
 456         }
 457
 458         if (of_property_read_u32(np, "rockchip,serial-id", &serial_id))
 459                 return -EINVAL;
 460
 461         if (of_property_read_u32(np, "rockchip,irq-mode-enable", &irq_mode))
 462                 irq_mode = -1;
 463
 464         if (irq_mode == 1)
 465                 signal_irq = -1;
 466         else if (of_property_read_u32(np, "rockchip,signal-irq", &signal_irq))
 467                         signal_irq = -1;
 468
 469         if (of_property_read_u32(np, "rockchip,wake-irq", &wake_irq))
 470                 wake_irq = -1;
 471
 472         if (of_property_read_u32(np, "rockchip,baudrate", &baudrate))
 473                 baudrate = -1;
 474
 475         np = NULL;
 476
 477         do {
 478                 np = of_find_node_by_name(np, "serial");
 479                 if (np) {
 480                         id = of_alias_get_id(np, "serial");
 481                         if (id == serial_id) {
 482                                 ok = 1;
 483                                 break;
 484                         }
 485                 }
 486         } while(np);
 487
 488         if (!ok)
 489                 return -EINVAL;
 490
 491         pclk = of_clk_get_by_name(np, "apb_pclk");
 492         clk = of_clk_get_by_name(np, "baudclk");
 493         if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) {
 494                 pr_err("fiq-debugger get clock fail\n");
 495                 return -EINVAL;
 496         }
 497
 498         clk_prepare_enable(clk);
 499         clk_prepare_enable(pclk);
 500
 501         irq = irq_of_parse_and_map(np, 0);
 502         if (!irq)
 503                 return -EINVAL;
 504
 505         base = of_iomap(np, 0);
 506         if (base)
 507                 rk_serial_debug_init(base, irq, signal_irq, wake_irq, baudrate);
 508
 509         return 0;
 510 }
 511 #ifdef CONFIG_FIQ_GLUE
 512 postcore_initcall_sync(rk_fiq_debugger_init);
 513 #else
 514 arch_initcall_sync(rk_fiq_debugger_init);
 515 #endif