2 * drivers/soc/rockchip/rk_fiq_debugger.c
4 * Serial Debugger Interface for Rockchip
6 * Copyright (C) 2012 ROCKCHIP, Inc.
7 * Copyright (C) 2008 Google, Inc.
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/platform_device.h>
28 #include <linux/irq.h>
29 #include <linux/serial_reg.h>
30 #include <linux/slab.h>
31 #include <linux/stacktrace.h>
32 #include <linux/uaccess.h>
33 #include <linux/kfifo.h>
34 #include <linux/kthread.h>
35 #include <linux/sched/rt.h>
36 #include <../drivers/staging/android/fiq_debugger/fiq_debugger.h>
37 #include <linux/irqchip/arm-gic.h>
38 #include <linux/clk.h>
39 #include <linux/delay.h>
40 #include <linux/soc/rockchip/rk_fiq_debugger.h>
42 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
43 #include "linux/rockchip/psci.h"
46 #define UART_USR 0x1f /* In: UART Status Register */
47 #define UART_USR_RX_FIFO_FULL 0x10 /* Receive FIFO full */
48 #define UART_USR_RX_FIFO_NOT_EMPTY 0x08 /* Receive FIFO not empty */
49 #define UART_USR_TX_FIFO_EMPTY 0x04 /* Transmit FIFO empty */
50 #define UART_USR_TX_FIFO_NOT_FULL 0x02 /* Transmit FIFO not full */
51 #define UART_USR_BUSY 0x01 /* UART busy indicator */
52 #define UART_SRR 0x22 /* software reset register */
54 struct rk_fiq_debugger {
57 struct fiq_debugger_pdata pdata;
58 void __iomem *debug_port_base;
60 #ifdef CONFIG_RK_CONSOLE_THREAD
61 struct task_struct *console_task;
65 static inline void rk_fiq_write(struct rk_fiq_debugger *t,
66 unsigned int val, unsigned int off)
68 __raw_writel(val, t->debug_port_base + off * 4);
71 static inline unsigned int rk_fiq_read(struct rk_fiq_debugger *t,
74 return __raw_readl(t->debug_port_base + off * 4);
77 static inline unsigned int rk_fiq_read_lsr(struct rk_fiq_debugger *t)
81 lsr = rk_fiq_read(t, UART_LSR);
82 if (lsr & UART_LSR_BI)
88 static int debug_port_init(struct platform_device *pdev)
91 struct rk_fiq_debugger *t;
93 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
95 if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
96 (void)rk_fiq_read(t, UART_RX);
98 switch (t->baudrate) {
108 rk_fiq_write(t, 0x07, UART_SRR);
110 /* set uart to loop back mode */
111 rk_fiq_write(t, 0x10, UART_MCR);
113 rk_fiq_write(t, 0x83, UART_LCR);
115 rk_fiq_write(t, dll, UART_DLL);
116 rk_fiq_write(t, dlm, UART_DLM);
117 rk_fiq_write(t, 0x03, UART_LCR);
119 /* enable rx and lsr interrupt */
120 rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
121 /* interrupt on every character when receive,but we can enable fifo for TX
122 I found that if we enable the RX fifo, some problem may vanish such as when
123 you continuously input characters in the command line the uart irq may be disable
124 because of the uart irq is served when CPU is at IRQ exception,but it is
125 found unregistered, so it is disable.
126 hhb@rock-chips.com */
127 rk_fiq_write(t, 0xc1, UART_FCR);
128 rk_fiq_write(t, 0x0, UART_MCR);
133 static int debug_getc(struct platform_device *pdev)
136 struct rk_fiq_debugger *t;
138 static unsigned int n;
141 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
143 lsr = rk_fiq_read_lsr(t);
145 if (lsr & UART_LSR_BI || t->break_seen) {
146 t->break_seen = false;
147 return FIQ_DEBUGGER_NO_CHAR;
150 if (lsr & UART_LSR_DR) {
151 temp = rk_fiq_read(t, UART_RX);
152 buf[n & 0x1f] = temp;
154 if (temp == 'q' && n > 2) {
155 if ((buf[(n - 2) & 0x1f] == 'i') &&
156 (buf[(n - 3) & 0x1f] == 'f'))
157 return FIQ_DEBUGGER_BREAK;
165 return FIQ_DEBUGGER_NO_CHAR;
168 static void debug_putc(struct platform_device *pdev, unsigned int c)
170 struct rk_fiq_debugger *t;
172 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
174 while (!(rk_fiq_read(t, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))
176 rk_fiq_write(t, c, UART_TX);
179 static void debug_flush(struct platform_device *pdev)
181 struct rk_fiq_debugger *t;
182 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
184 while (!(rk_fiq_read_lsr(t) & UART_LSR_TEMT))
188 static int uart_dev_resume(struct platform_device *pdev)
190 debug_port_init(pdev);
194 #ifdef CONFIG_RK_CONSOLE_THREAD
195 #define FIFO_SIZE SZ_64K
196 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);
197 static bool console_thread_stop;
199 static int console_thread(void *data)
201 struct platform_device *pdev = data;
202 struct rk_fiq_debugger *t;
204 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
207 set_current_state(TASK_INTERRUPTIBLE);
209 if (kthread_should_stop())
211 set_current_state(TASK_RUNNING);
212 while (!console_thread_stop && kfifo_get(&fifo, &c))
214 if (!console_thread_stop)
221 static void console_write(struct platform_device *pdev, const char *s, unsigned int count)
223 unsigned int fifo_count = FIFO_SIZE;
224 unsigned char c, r = '\r';
225 struct rk_fiq_debugger *t;
226 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
228 if (console_thread_stop ||
230 system_state == SYSTEM_HALT ||
231 system_state == SYSTEM_POWER_OFF ||
232 system_state == SYSTEM_RESTART) {
233 if (!console_thread_stop) {
234 console_thread_stop = true;
237 while (fifo_count-- && kfifo_get(&fifo, &c))
244 debug_putc(pdev, *s++);
252 kfifo_put(&fifo, *s++);
254 wake_up_process(t->console_task);
260 static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
268 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
269 static struct pt_regs fiq_pt_regs;
271 static void rk_fiq_debugger_switch_cpu(struct platform_device *pdev,
274 psci_fiq_debugger_switch_cpu(cpu);
277 static void rk_fiq_debugger_enable_debug(struct platform_device *pdev, bool val)
279 psci_fiq_debugger_enable_debug(val);
282 static void fiq_debugger_uart_irq_tf(void *reg_base, u64 sp_el1)
284 memcpy(&fiq_pt_regs, reg_base, 8*31);
286 memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
287 if (fiq_pt_regs.pstate & 0x10)
288 memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8);
290 fiq_pt_regs.sp = sp_el1;
292 memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
294 fiq_debugger_fiq(&fiq_pt_regs);
297 static int fiq_debugger_uart_dev_resume(struct platform_device *pdev)
299 struct rk_fiq_debugger *t;
301 t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
302 psci_fiq_debugger_uart_irq_tf_init(t->irq, fiq_debugger_uart_irq_tf);
307 static int rk_fiq_debugger_id;
309 void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq,
310 int wakeup_irq, unsigned int baudrate)
312 struct rk_fiq_debugger *t = NULL;
313 struct platform_device *pdev = NULL;
314 struct resource *res = NULL;
316 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
317 /* tf means trust firmware*/
319 bool tf_fiq_sup = false;
323 pr_err("Invalid fiq debugger uart base\n");
327 t = kzalloc(sizeof(struct rk_fiq_debugger), GFP_KERNEL);
329 pr_err("Failed to allocate for fiq debugger\n");
334 t->baudrate = baudrate;
335 t->pdata.uart_init = debug_port_init;
336 t->pdata.uart_getc = debug_getc;
337 t->pdata.uart_putc = debug_putc;
338 t->pdata.uart_dev_resume = uart_dev_resume;
339 #ifndef CONFIG_RK_CONSOLE_THREAD
340 t->pdata.uart_flush = debug_flush;
342 t->pdata.fiq_enable = fiq_enable;
343 t->pdata.force_irq = NULL; //force_irq;
344 t->debug_port_base = base;
346 res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
348 pr_err("Failed to alloc fiq debugger resources\n");
352 pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
354 pr_err("Failed to alloc fiq debugger platform device\n");
358 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
359 tf_ver = rockchip_psci_smc_get_tf_ver();
361 if (tf_ver >= 0x00010005)
366 if (tf_fiq_sup && (signal_irq > 0)) {
367 t->pdata.switch_cpu = rk_fiq_debugger_switch_cpu;
368 t->pdata.enable_debug = rk_fiq_debugger_enable_debug;
369 t->pdata.uart_dev_resume = fiq_debugger_uart_dev_resume;
370 psci_fiq_debugger_uart_irq_tf_init(irq,
371 fiq_debugger_uart_irq_tf);
373 t->pdata.switch_cpu = NULL;
374 t->pdata.enable_debug = NULL;
379 res[0].flags = IORESOURCE_IRQ;
382 #if defined(CONFIG_FIQ_GLUE)
386 res[0].name = "uart_irq";
387 #elif defined(CONFIG_FIQ_DEBUGGER_EL3_TO_EL1)
388 if (tf_fiq_sup && (signal_irq > 0))
391 res[0].name = "uart_irq";
393 res[0].name = "uart_irq";
398 if (signal_irq > 0) {
399 res[1].flags = IORESOURCE_IRQ;
400 res[1].start = signal_irq;
401 res[1].end = signal_irq;
402 res[1].name = "signal";
406 if (wakeup_irq > 0) {
407 res[2].flags = IORESOURCE_IRQ;
408 res[2].start = wakeup_irq;
409 res[2].end = wakeup_irq;
410 res[2].name = "wakeup";
414 #ifdef CONFIG_RK_CONSOLE_THREAD
415 t->console_task = kthread_create(console_thread, pdev, "kconsole");
416 if (!IS_ERR(t->console_task))
417 t->pdata.console_write = console_write;
420 pdev->name = "fiq_debugger";
421 pdev->id = rk_fiq_debugger_id++;
422 pdev->dev.platform_data = &t->pdata;
423 pdev->resource = res;
424 pdev->num_resources = res_count;
425 if (platform_device_register(pdev)) {
426 pr_err("Failed to register fiq debugger\n");
439 static const struct of_device_id ids[] __initconst = {
440 { .compatible = "rockchip,fiq-debugger" },
444 static int __init rk_fiq_debugger_init(void) {
447 struct device_node *np;
448 unsigned int id, serial_id, ok = 0;
449 unsigned int irq, signal_irq = 0, wake_irq = 0;
450 unsigned int baudrate = 0, irq_mode = 0;
454 np = of_find_matching_node(NULL, ids);
457 pr_err("fiq-debugger is missing in device tree!\n");
461 if (!of_device_is_available(np)) {
462 pr_err("fiq-debugger is disabled in device tree\n");
466 if (of_property_read_u32(np, "rockchip,serial-id", &serial_id))
469 if (of_property_read_u32(np, "rockchip,irq-mode-enable", &irq_mode))
474 else if (of_property_read_u32(np, "rockchip,signal-irq", &signal_irq))
477 if (of_property_read_u32(np, "rockchip,wake-irq", &wake_irq))
480 if (of_property_read_u32(np, "rockchip,baudrate", &baudrate))
486 np = of_find_node_by_name(np, "serial");
488 id = of_alias_get_id(np, "serial");
489 if (id == serial_id) {
499 pclk = of_clk_get_by_name(np, "apb_pclk");
500 clk = of_clk_get_by_name(np, "baudclk");
501 if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) {
502 pr_err("fiq-debugger get clock fail\n");
506 clk_prepare_enable(clk);
507 clk_prepare_enable(pclk);
509 irq = irq_of_parse_and_map(np, 0);
513 base = of_iomap(np, 0);
515 rk_serial_debug_init(base, irq, signal_irq, wake_irq, baudrate);
519 #ifdef CONFIG_FIQ_GLUE
520 postcore_initcall_sync(rk_fiq_debugger_init);
522 arch_initcall_sync(rk_fiq_debugger_init);