drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/err.h>
  14 #include <linux/pm_clock.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/clk.h>
  19 #include <linux/regmap.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <dt-bindings/power/rk3288-power.h>
  22 #include <dt-bindings/power/rk3366-power.h>
  23 #include <dt-bindings/power/rk3368-power.h>
  24 #include <dt-bindings/power/rk3399-power.h>
  25
  26 struct rockchip_domain_info {
  27         int pwr_mask;
  28         int status_mask;
  29         int req_mask;
  30         int idle_mask;
  31         int ack_mask;
  32         bool active_wakeup;
  33 };
  34
  35 struct rockchip_pmu_info {
  36         u32 pwr_offset;
  37         u32 status_offset;
  38         u32 req_offset;
  39         u32 idle_offset;
  40         u32 ack_offset;
  41
  42         u32 core_pwrcnt_offset;
  43         u32 gpu_pwrcnt_offset;
  44
  45         unsigned int core_power_transition_time;
  46         unsigned int gpu_power_transition_time;
  47
  48         int num_domains;
  49         const struct rockchip_domain_info *domain_info;
  50 };
  51
  52 #define MAX_QOS_REGS_NUM        5
  53 #define QOS_PRIORITY            0x08
  54 #define QOS_MODE                0x0c
  55 #define QOS_BANDWIDTH           0x10
  56 #define QOS_SATURATION          0x14
  57 #define QOS_EXTCONTROL          0x18
  58
  59 struct rockchip_pm_domain {
  60         struct generic_pm_domain genpd;
  61         const struct rockchip_domain_info *info;
  62         struct rockchip_pmu *pmu;
  63         int num_qos;
  64         struct regmap **qos_regmap;
  65         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  66         int num_clks;
  67         struct clk *clks[];
  68 };
  69
  70 struct rockchip_pmu {
  71         struct device *dev;
  72         struct regmap *regmap;
  73         const struct rockchip_pmu_info *info;
  74         struct mutex mutex; /* mutex lock for pmu */
  75         struct genpd_onecell_data genpd_data;
  76         struct generic_pm_domain *domains[];
  77 };
  78
  79 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  80
  81 #define DOMAIN(pwr, status, req, idle, ack, wakeup)     \
  82 {                                               \
  83         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  84         .status_mask = (status >= 0) ? BIT(status) : 0, \
  85         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  86         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  87         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  88         .active_wakeup = wakeup,                        \
  89 }
  90
  91 #define DOMAIN_RK3288(pwr, status, req, wakeup)         \
  92         DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
  93
  94 #define DOMAIN_RK3368(pwr, status, req, wakeup)         \
  95         DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
  96
  97 #define DOMAIN_RK3399(pwr, status, req, wakeup)         \
  98         DOMAIN(pwr, status, req, req, req, wakeup)
  99
 100 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 101 {
 102         struct rockchip_pmu *pmu = pd->pmu;
 103         const struct rockchip_domain_info *pd_info = pd->info;
 104         unsigned int val;
 105
 106         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 107         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 108 }
 109
 110 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
 111 {
 112         unsigned int val;
 113
 114         regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 115         return val;
 116 }
 117
 118 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 119                                          bool idle)
 120 {
 121         const struct rockchip_domain_info *pd_info = pd->info;
 122         struct generic_pm_domain *genpd = &pd->genpd;
 123         struct rockchip_pmu *pmu = pd->pmu;
 124         unsigned int target_ack;
 125         unsigned int val;
 126         bool is_idle;
 127         int ret;
 128
 129         if (pd_info->req_mask == 0)
 130                 return 0;
 131
 132         regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 133                            pd_info->req_mask, idle ? -1U : 0);
 134
 135         dsb(sy);
 136
 137         /* Wait util idle_ack = 1 */
 138         target_ack = idle ? pd_info->ack_mask : 0;
 139         ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
 140                                         (val & pd_info->ack_mask) == target_ack,
 141                                         0, 10000);
 142         if (ret) {
 143                 dev_err(pmu->dev,
 144                         "failed to get ack on domain '%s', val=0x%x\n",
 145                         genpd->name, val);
 146                 return ret;
 147         }
 148
 149         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
 150                                         is_idle, is_idle == idle, 0, 10000);
 151         if (ret) {
 152                 dev_err(pmu->dev,
 153                         "failed to set idle on domain '%s', val=%d\n",
 154                         genpd->name, is_idle);
 155                 return ret;
 156         }
 157
 158         return 0;
 159 }
 160
 161 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 162 {
 163         int i;
 164
 165         for (i = 0; i < pd->num_qos; i++) {
 166                 regmap_read(pd->qos_regmap[i],
 167                             QOS_PRIORITY,
 168                             &pd->qos_save_regs[0][i]);
 169                 regmap_read(pd->qos_regmap[i],
 170                             QOS_MODE,
 171                             &pd->qos_save_regs[1][i]);
 172                 regmap_read(pd->qos_regmap[i],
 173                             QOS_BANDWIDTH,
 174                             &pd->qos_save_regs[2][i]);
 175                 regmap_read(pd->qos_regmap[i],
 176                             QOS_SATURATION,
 177                             &pd->qos_save_regs[3][i]);
 178                 regmap_read(pd->qos_regmap[i],
 179                             QOS_EXTCONTROL,
 180                             &pd->qos_save_regs[4][i]);
 181         }
 182         return 0;
 183 }
 184
 185 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 186 {
 187         int i;
 188
 189         for (i = 0; i < pd->num_qos; i++) {
 190                 regmap_write(pd->qos_regmap[i],
 191                              QOS_PRIORITY,
 192                              pd->qos_save_regs[0][i]);
 193                 regmap_write(pd->qos_regmap[i],
 194                              QOS_MODE,
 195                              pd->qos_save_regs[1][i]);
 196                 regmap_write(pd->qos_regmap[i],
 197                              QOS_BANDWIDTH,
 198                              pd->qos_save_regs[2][i]);
 199                 regmap_write(pd->qos_regmap[i],
 200                              QOS_SATURATION,
 201                              pd->qos_save_regs[3][i]);
 202                 regmap_write(pd->qos_regmap[i],
 203                              QOS_EXTCONTROL,
 204                              pd->qos_save_regs[4][i]);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 211 {
 212         struct rockchip_pmu *pmu = pd->pmu;
 213         unsigned int val;
 214
 215         /* check idle status for idle-only domains */
 216         if (pd->info->status_mask == 0)
 217                 return !rockchip_pmu_domain_is_idle(pd);
 218
 219         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 220
 221         /* 1'b0: power on, 1'b1: power off */
 222         return !(val & pd->info->status_mask);
 223 }
 224
 225 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 226                                              bool on)
 227 {
 228         struct rockchip_pmu *pmu = pd->pmu;
 229         struct generic_pm_domain *genpd = &pd->genpd;
 230         bool is_on;
 231
 232         if (pd->info->pwr_mask == 0)
 233                 return;
 234
 235         regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 236                            pd->info->pwr_mask, on ? 0 : -1U);
 237
 238         dsb(sy);
 239
 240         if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
 241                                       is_on == on, 0, 10000)) {
 242                 dev_err(pmu->dev,
 243                         "failed to set domain '%s', val=%d\n",
 244                         genpd->name, is_on);
 245                 return;
 246         }
 247 }
 248
 249 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 250 {
 251         int i;
 252
 253         mutex_lock(&pd->pmu->mutex);
 254
 255         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 256                 for (i = 0; i < pd->num_clks; i++)
 257                         clk_enable(pd->clks[i]);
 258
 259                 if (!power_on) {
 260                         rockchip_pmu_save_qos(pd);
 261
 262                         /* if powering down, idle request to NIU first */
 263                         rockchip_pmu_set_idle_request(pd, true);
 264                 }
 265
 266                 rockchip_do_pmu_set_power_domain(pd, power_on);
 267
 268                 if (power_on) {
 269                         /* if powering up, leave idle mode */
 270                         rockchip_pmu_set_idle_request(pd, false);
 271
 272                         rockchip_pmu_restore_qos(pd);
 273                 }
 274
 275                 for (i = pd->num_clks - 1; i >= 0; i--)
 276                         clk_disable(pd->clks[i]);
 277         }
 278
 279         mutex_unlock(&pd->pmu->mutex);
 280         return 0;
 281 }
 282
 283 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 284 {
 285         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 286
 287         return rockchip_pd_power(pd, true);
 288 }
 289
 290 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 291 {
 292         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 293
 294         return rockchip_pd_power(pd, false);
 295 }
 296
 297 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 298                                   struct device *dev)
 299 {
 300         struct clk *clk;
 301         int i;
 302         int error;
 303
 304         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 305
 306         error = pm_clk_create(dev);
 307         if (error) {
 308                 dev_err(dev, "pm_clk_create failed %d\n", error);
 309                 return error;
 310         }
 311
 312         i = 0;
 313         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 314                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 315                 error = pm_clk_add_clk(dev, clk);
 316                 if (error) {
 317                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 318                         clk_put(clk);
 319                         pm_clk_destroy(dev);
 320                         return error;
 321                 }
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 328                                    struct device *dev)
 329 {
 330         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 331
 332         pm_clk_destroy(dev);
 333 }
 334
 335 static bool rockchip_active_wakeup(struct device *dev)
 336 {
 337         struct generic_pm_domain *genpd;
 338         struct rockchip_pm_domain *pd;
 339
 340         genpd = pd_to_genpd(dev->pm_domain);
 341         pd = container_of(genpd, struct rockchip_pm_domain, genpd);
 342
 343         return pd->info->active_wakeup;
 344 }
 345
 346 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 347                                       struct device_node *node)
 348 {
 349         const struct rockchip_domain_info *pd_info;
 350         struct rockchip_pm_domain *pd;
 351         struct device_node *qos_node;
 352         struct clk *clk;
 353         int clk_cnt;
 354         int i, j;
 355         u32 id;
 356         int error;
 357
 358         error = of_property_read_u32(node, "reg", &id);
 359         if (error) {
 360                 dev_err(pmu->dev,
 361                         "%s: failed to retrieve domain id (reg): %d\n",
 362                         node->name, error);
 363                 return -EINVAL;
 364         }
 365
 366         if (id >= pmu->info->num_domains) {
 367                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 368                         node->name, id);
 369                 return -EINVAL;
 370         }
 371
 372         pd_info = &pmu->info->domain_info[id];
 373         if (!pd_info) {
 374                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 375                         node->name, id);
 376                 return -EINVAL;
 377         }
 378
 379         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 380         pd = devm_kzalloc(pmu->dev,
 381                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 382                           GFP_KERNEL);
 383         if (!pd)
 384                 return -ENOMEM;
 385
 386         pd->info = pd_info;
 387         pd->pmu = pmu;
 388
 389         for (i = 0; i < clk_cnt; i++) {
 390                 clk = of_clk_get(node, i);
 391                 if (IS_ERR(clk)) {
 392                         error = PTR_ERR(clk);
 393                         dev_err(pmu->dev,
 394                                 "%s: failed to get clk at index %d: %d\n",
 395                                 node->name, i, error);
 396                         goto err_out;
 397                 }
 398
 399                 error = clk_prepare(clk);
 400                 if (error) {
 401                         dev_err(pmu->dev,
 402                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 403                                 node->name, clk, i, error);
 404                         clk_put(clk);
 405                         goto err_out;
 406                 }
 407
 408                 pd->clks[pd->num_clks++] = clk;
 409
 410                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 411                         clk, node->name);
 412         }
 413
 414         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 415                                                  NULL);
 416
 417         if (pd->num_qos > 0) {
 418                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 419                                               sizeof(*pd->qos_regmap),
 420                                               GFP_KERNEL);
 421                 if (!pd->qos_regmap) {
 422                         error = -ENOMEM;
 423                         goto err_out;
 424                 }
 425
 426                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 427                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 428                                                             pd->num_qos,
 429                                                             sizeof(u32),
 430                                                             GFP_KERNEL);
 431                         if (!pd->qos_save_regs[j]) {
 432                                 error = -ENOMEM;
 433                                 goto err_out;
 434                         }
 435                 }
 436
 437                 for (j = 0; j < pd->num_qos; j++) {
 438                         qos_node = of_parse_phandle(node, "pm_qos", j);
 439                         if (!qos_node) {
 440                                 error = -ENODEV;
 441                                 goto err_out;
 442                         }
 443                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 444                         if (IS_ERR(pd->qos_regmap[j])) {
 445                                 error = -ENODEV;
 446                                 of_node_put(qos_node);
 447                                 goto err_out;
 448                         }
 449                         of_node_put(qos_node);
 450                 }
 451         }
 452
 453         error = rockchip_pd_power(pd, true);
 454         if (error) {
 455                 dev_err(pmu->dev,
 456                         "failed to power on domain '%s': %d\n",
 457                         node->name, error);
 458                 goto err_out;
 459         }
 460
 461         pd->genpd.name = node->name;
 462         pd->genpd.power_off = rockchip_pd_power_off;
 463         pd->genpd.power_on = rockchip_pd_power_on;
 464         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 465         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 466         pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
 467         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 468         pm_genpd_init(&pd->genpd, NULL, false);
 469
 470         pmu->genpd_data.domains[id] = &pd->genpd;
 471         return 0;
 472
 473 err_out:
 474         while (--i >= 0) {
 475                 clk_unprepare(pd->clks[i]);
 476                 clk_put(pd->clks[i]);
 477         }
 478         return error;
 479 }
 480
 481 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 482 {
 483         int i;
 484
 485         for (i = 0; i < pd->num_clks; i++) {
 486                 clk_unprepare(pd->clks[i]);
 487                 clk_put(pd->clks[i]);
 488         }
 489
 490         /* protect the zeroing of pm->num_clks */
 491         mutex_lock(&pd->pmu->mutex);
 492         pd->num_clks = 0;
 493         mutex_unlock(&pd->pmu->mutex);
 494
 495         /* devm will free our memory */
 496 }
 497
 498 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 499 {
 500         struct generic_pm_domain *genpd;
 501         struct rockchip_pm_domain *pd;
 502         int i;
 503
 504         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 505                 genpd = pmu->genpd_data.domains[i];
 506                 if (genpd) {
 507                         pd = to_rockchip_pd(genpd);
 508                         rockchip_pm_remove_one_domain(pd);
 509                 }
 510         }
 511
 512         /* devm will free our memory */
 513 }
 514
 515 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 516                                       u32 domain_reg_offset,
 517                                       unsigned int count)
 518 {
 519         /* First configure domain power down transition count ... */
 520         regmap_write(pmu->regmap, domain_reg_offset, count);
 521         /* ... and then power up count. */
 522         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 523 }
 524
 525 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 526                                      struct device_node *parent)
 527 {
 528         struct device_node *np;
 529         struct generic_pm_domain *child_domain, *parent_domain;
 530         int error;
 531
 532         for_each_child_of_node(parent, np) {
 533                 u32 idx;
 534
 535                 error = of_property_read_u32(parent, "reg", &idx);
 536                 if (error) {
 537                         dev_err(pmu->dev,
 538                                 "%s: failed to retrieve domain id (reg): %d\n",
 539                                 parent->name, error);
 540                         goto err_out;
 541                 }
 542                 parent_domain = pmu->genpd_data.domains[idx];
 543
 544                 error = rockchip_pm_add_one_domain(pmu, np);
 545                 if (error) {
 546                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 547                                 np->name, error);
 548                         goto err_out;
 549                 }
 550
 551                 error = of_property_read_u32(np, "reg", &idx);
 552                 if (error) {
 553                         dev_err(pmu->dev,
 554                                 "%s: failed to retrieve domain id (reg): %d\n",
 555                                 np->name, error);
 556                         goto err_out;
 557                 }
 558                 child_domain = pmu->genpd_data.domains[idx];
 559
 560                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 561                 if (error) {
 562                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 563                                 parent_domain->name, child_domain->name, error);
 564                         goto err_out;
 565                 } else {
 566                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 567                                 parent_domain->name, child_domain->name);
 568                 }
 569
 570                 rockchip_pm_add_subdomain(pmu, np);
 571         }
 572
 573         return 0;
 574
 575 err_out:
 576         of_node_put(np);
 577         return error;
 578 }
 579
 580 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 581 {
 582         struct device *dev = &pdev->dev;
 583         struct device_node *np = dev->of_node;
 584         struct device_node *node;
 585         struct device *parent;
 586         struct rockchip_pmu *pmu;
 587         const struct of_device_id *match;
 588         const struct rockchip_pmu_info *pmu_info;
 589         int error;
 590
 591         if (!np) {
 592                 dev_err(dev, "device tree node not found\n");
 593                 return -ENODEV;
 594         }
 595
 596         match = of_match_device(dev->driver->of_match_table, dev);
 597         if (!match || !match->data) {
 598                 dev_err(dev, "missing pmu data\n");
 599                 return -EINVAL;
 600         }
 601
 602         pmu_info = match->data;
 603
 604         pmu = devm_kzalloc(dev,
 605                            sizeof(*pmu) +
 606                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 607                            GFP_KERNEL);
 608         if (!pmu)
 609                 return -ENOMEM;
 610
 611         pmu->dev = &pdev->dev;
 612         mutex_init(&pmu->mutex);
 613
 614         pmu->info = pmu_info;
 615
 616         pmu->genpd_data.domains = pmu->domains;
 617         pmu->genpd_data.num_domains = pmu_info->num_domains;
 618
 619         parent = dev->parent;
 620         if (!parent) {
 621                 dev_err(dev, "no parent for syscon devices\n");
 622                 return -ENODEV;
 623         }
 624
 625         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 626         if (IS_ERR(pmu->regmap)) {
 627                 dev_err(dev, "no regmap available\n");
 628                 return PTR_ERR(pmu->regmap);
 629         }
 630
 631         /*
 632          * Configure power up and down transition delays for CORE
 633          * and GPU domains.
 634          */
 635         rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 636                                   pmu_info->core_power_transition_time);
 637         rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 638                                   pmu_info->gpu_power_transition_time);
 639
 640         error = -ENODEV;
 641
 642         for_each_available_child_of_node(np, node) {
 643                 error = rockchip_pm_add_one_domain(pmu, node);
 644                 if (error) {
 645                         dev_err(dev, "failed to handle node %s: %d\n",
 646                                 node->name, error);
 647                         of_node_put(node);
 648                         goto err_out;
 649                 }
 650
 651                 error = rockchip_pm_add_subdomain(pmu, node);
 652                 if (error < 0) {
 653                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 654                                 node->name, error);
 655                         of_node_put(node);
 656                         goto err_out;
 657                 }
 658         }
 659
 660         if (error) {
 661                 dev_dbg(dev, "no power domains defined\n");
 662                 goto err_out;
 663         }
 664
 665         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 666
 667         return 0;
 668
 669 err_out:
 670         rockchip_pm_domain_cleanup(pmu);
 671         return error;
 672 }
 673
 674 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 675         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4, false),
 676         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9, false),
 677         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3, false),
 678         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2, false),
 679 };
 680
 681 static const struct rockchip_domain_info rk3366_pm_domains[] = {
 682         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6, true),
 683         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8, false),
 684         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7, false),
 685         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7, false),
 686         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9, false),
 687         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7, false),
 688         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2, false),
 689 };
 690
 691 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 692         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6, true),
 693         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8, false),
 694         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7, false),
 695         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2, false),
 696         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2, false),
 697 };
 698
 699 static const struct rockchip_domain_info rk3399_pm_domains[] = {
 700         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1, false),
 701         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1, false),
 702         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1, true),
 703         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15, true),
 704         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16, true),
 705         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1, true),
 706         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2, true),
 707         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14, true),
 708         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17, false),
 709         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0, false),
 710         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3, false),
 711         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4, false),
 712         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5, false),
 713         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6, false),
 714         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1, false),
 715         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7, false),
 716         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8, false),
 717         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9, false),
 718         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10, false),
 719         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11, false),
 720         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23, true),
 721         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24, true),
 722         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12, true),
 723         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22, false),
 724         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27, true),
 725         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28, true),
 726         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29, true),
 727 };
 728
 729 static const struct rockchip_pmu_info rk3288_pmu = {
 730         .pwr_offset = 0x08,
 731         .status_offset = 0x0c,
 732         .req_offset = 0x10,
 733         .idle_offset = 0x14,
 734         .ack_offset = 0x14,
 735
 736         .core_pwrcnt_offset = 0x34,
 737         .gpu_pwrcnt_offset = 0x3c,
 738
 739         .core_power_transition_time = 24, /* 1us */
 740         .gpu_power_transition_time = 24, /* 1us */
 741
 742         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 743         .domain_info = rk3288_pm_domains,
 744 };
 745
 746 static const struct rockchip_pmu_info rk3366_pmu = {
 747         .pwr_offset = 0x0c,
 748         .status_offset = 0x10,
 749         .req_offset = 0x3c,
 750         .idle_offset = 0x40,
 751         .ack_offset = 0x40,
 752
 753         .core_pwrcnt_offset = 0x48,
 754         .gpu_pwrcnt_offset = 0x50,
 755
 756         .core_power_transition_time = 24,
 757         .gpu_power_transition_time = 24,
 758
 759         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
 760         .domain_info = rk3366_pm_domains,
 761 };
 762
 763 static const struct rockchip_pmu_info rk3368_pmu = {
 764         .pwr_offset = 0x0c,
 765         .status_offset = 0x10,
 766         .req_offset = 0x3c,
 767         .idle_offset = 0x40,
 768         .ack_offset = 0x40,
 769
 770         .core_pwrcnt_offset = 0x48,
 771         .gpu_pwrcnt_offset = 0x50,
 772
 773         .core_power_transition_time = 24,
 774         .gpu_power_transition_time = 24,
 775
 776         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 777         .domain_info = rk3368_pm_domains,
 778 };
 779
 780 static const struct rockchip_pmu_info rk3399_pmu = {
 781         .pwr_offset = 0x14,
 782         .status_offset = 0x18,
 783         .req_offset = 0x60,
 784         .idle_offset = 0x64,
 785         .ack_offset = 0x68,
 786
 787         .core_pwrcnt_offset = 0xac,
 788         .gpu_pwrcnt_offset = 0xac,
 789
 790         .core_power_transition_time = 6, /* 0.25us */
 791         .gpu_power_transition_time = 6, /* 0.25us */
 792
 793         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
 794         .domain_info = rk3399_pm_domains,
 795 };
 796
 797 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 798         {
 799                 .compatible = "rockchip,rk3288-power-controller",
 800                 .data = (void *)&rk3288_pmu,
 801         },
 802         {
 803                 .compatible = "rockchip,rk3366-power-controller",
 804                 .data = (void *)&rk3366_pmu,
 805         },
 806         {
 807                 .compatible = "rockchip,rk3368-power-controller",
 808                 .data = (void *)&rk3368_pmu,
 809         },
 810         {
 811                 .compatible = "rockchip,rk3399-power-controller",
 812                 .data = (void *)&rk3399_pmu,
 813         },
 814         { /* sentinel */ },
 815 };
 816
 817 static struct platform_driver rockchip_pm_domain_driver = {
 818         .probe = rockchip_pm_domain_probe,
 819         .driver = {
 820                 .name   = "rockchip-pm-domain",
 821                 .of_match_table = rockchip_pm_domain_dt_match,
 822                 /*
 823                  * We can't forcibly eject devices form power domain,
 824                  * so we can't really remove power domains once they
 825                  * were added.
 826                  */
 827                 .suppress_bind_attrs = true,
 828         },
 829 };
 830
 831 static int __init rockchip_pm_domain_drv_register(void)
 832 {
 833         return platform_driver_register(&rockchip_pm_domain_driver);
 834 }
 835 postcore_initcall(rockchip_pm_domain_drv_register);