2 * Rockchip Generic power domain support.
4 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/iopoll.h>
13 #include <linux/err.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/clk.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/syscon.h>
21 #include <dt-bindings/power/rk3288-power.h>
22 #include <dt-bindings/power/rk3328-power.h>
23 #include <dt-bindings/power/rk3366-power.h>
24 #include <dt-bindings/power/rk3368-power.h>
25 #include <dt-bindings/power/rk3399-power.h>
27 struct rockchip_domain_info {
38 struct rockchip_pmu_info {
45 u32 core_pwrcnt_offset;
46 u32 gpu_pwrcnt_offset;
48 unsigned int core_power_transition_time;
49 unsigned int gpu_power_transition_time;
52 const struct rockchip_domain_info *domain_info;
55 #define MAX_QOS_REGS_NUM 5
56 #define QOS_PRIORITY 0x08
58 #define QOS_BANDWIDTH 0x10
59 #define QOS_SATURATION 0x14
60 #define QOS_EXTCONTROL 0x18
62 struct rockchip_pm_domain {
63 struct generic_pm_domain genpd;
64 const struct rockchip_domain_info *info;
65 struct rockchip_pmu *pmu;
67 struct regmap **qos_regmap;
68 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
75 struct regmap *regmap;
76 const struct rockchip_pmu_info *info;
77 struct mutex mutex; /* mutex lock for pmu */
78 struct genpd_onecell_data genpd_data;
79 struct generic_pm_domain *domains[];
82 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
84 #define DOMAIN(pwr, status, req, idle, ack, wakeup) \
86 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
87 .status_mask = (status >= 0) ? BIT(status) : 0, \
88 .req_mask = (req >= 0) ? BIT(req) : 0, \
89 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
90 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
91 .active_wakeup = wakeup, \
94 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
96 .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0, \
97 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
98 .status_mask = (status >= 0) ? BIT(status) : 0, \
99 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
100 .req_mask = (req >= 0) ? BIT(req) : 0, \
101 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
102 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
103 .active_wakeup = wakeup, \
106 #define DOMAIN_RK3288(pwr, status, req, wakeup) \
107 DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
109 #define DOMAIN_RK3328(pwr, status, req, wakeup) \
110 DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
112 #define DOMAIN_RK3368(pwr, status, req, wakeup) \
113 DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
115 #define DOMAIN_RK3399(pwr, status, req, wakeup) \
116 DOMAIN(pwr, status, req, req, req, wakeup)
118 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
120 struct rockchip_pmu *pmu = pd->pmu;
121 const struct rockchip_domain_info *pd_info = pd->info;
124 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
125 return (val & pd_info->idle_mask) == pd_info->idle_mask;
128 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
132 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
136 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
139 const struct rockchip_domain_info *pd_info = pd->info;
140 struct generic_pm_domain *genpd = &pd->genpd;
141 struct rockchip_pmu *pmu = pd->pmu;
142 unsigned int target_ack;
147 if (pd_info->req_mask == 0)
149 else if (pd_info->req_w_mask)
150 regmap_write(pmu->regmap, pmu->info->req_offset,
151 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
152 pd_info->req_w_mask);
154 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
155 pd_info->req_mask, idle ? -1U : 0);
159 /* Wait util idle_ack = 1 */
160 target_ack = idle ? pd_info->ack_mask : 0;
161 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
162 (val & pd_info->ack_mask) == target_ack,
166 "failed to get ack on domain '%s', val=0x%x\n",
171 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
172 is_idle, is_idle == idle, 0, 10000);
175 "failed to set idle on domain '%s', val=%d\n",
176 genpd->name, is_idle);
183 int rockchip_pmu_idle_request(struct device *dev, bool idle)
185 struct generic_pm_domain *genpd;
186 struct rockchip_pm_domain *pd;
189 if (IS_ERR_OR_NULL(dev))
192 if (IS_ERR_OR_NULL(dev->pm_domain))
195 genpd = pd_to_genpd(dev->pm_domain);
196 pd = to_rockchip_pd(genpd);
198 mutex_lock(&pd->pmu->mutex);
199 ret = rockchip_pmu_set_idle_request(pd, idle);
200 mutex_unlock(&pd->pmu->mutex);
204 EXPORT_SYMBOL(rockchip_pmu_idle_request);
206 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
210 for (i = 0; i < pd->num_qos; i++) {
211 regmap_read(pd->qos_regmap[i],
213 &pd->qos_save_regs[0][i]);
214 regmap_read(pd->qos_regmap[i],
216 &pd->qos_save_regs[1][i]);
217 regmap_read(pd->qos_regmap[i],
219 &pd->qos_save_regs[2][i]);
220 regmap_read(pd->qos_regmap[i],
222 &pd->qos_save_regs[3][i]);
223 regmap_read(pd->qos_regmap[i],
225 &pd->qos_save_regs[4][i]);
230 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
234 for (i = 0; i < pd->num_qos; i++) {
235 regmap_write(pd->qos_regmap[i],
237 pd->qos_save_regs[0][i]);
238 regmap_write(pd->qos_regmap[i],
240 pd->qos_save_regs[1][i]);
241 regmap_write(pd->qos_regmap[i],
243 pd->qos_save_regs[2][i]);
244 regmap_write(pd->qos_regmap[i],
246 pd->qos_save_regs[3][i]);
247 regmap_write(pd->qos_regmap[i],
249 pd->qos_save_regs[4][i]);
255 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
257 struct rockchip_pmu *pmu = pd->pmu;
260 /* check idle status for idle-only domains */
261 if (pd->info->status_mask == 0)
262 return !rockchip_pmu_domain_is_idle(pd);
264 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
266 /* 1'b0: power on, 1'b1: power off */
267 return !(val & pd->info->status_mask);
270 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
273 struct rockchip_pmu *pmu = pd->pmu;
274 struct generic_pm_domain *genpd = &pd->genpd;
277 if (pd->info->pwr_mask == 0)
279 else if (pd->info->pwr_w_mask)
280 regmap_write(pmu->regmap, pmu->info->pwr_offset,
281 on ? pd->info->pwr_mask :
282 (pd->info->pwr_mask | pd->info->pwr_w_mask));
284 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
285 pd->info->pwr_mask, on ? 0 : -1U);
289 if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
290 is_on == on, 0, 10000)) {
292 "failed to set domain '%s', val=%d\n",
298 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
302 mutex_lock(&pd->pmu->mutex);
304 if (rockchip_pmu_domain_is_on(pd) != power_on) {
305 for (i = 0; i < pd->num_clks; i++)
306 clk_enable(pd->clks[i]);
309 rockchip_pmu_save_qos(pd);
311 /* if powering down, idle request to NIU first */
312 rockchip_pmu_set_idle_request(pd, true);
315 rockchip_do_pmu_set_power_domain(pd, power_on);
318 /* if powering up, leave idle mode */
319 rockchip_pmu_set_idle_request(pd, false);
321 rockchip_pmu_restore_qos(pd);
324 for (i = pd->num_clks - 1; i >= 0; i--)
325 clk_disable(pd->clks[i]);
328 mutex_unlock(&pd->pmu->mutex);
332 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
334 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
336 return rockchip_pd_power(pd, true);
339 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
341 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
343 return rockchip_pd_power(pd, false);
346 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
353 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
355 error = pm_clk_create(dev);
357 dev_err(dev, "pm_clk_create failed %d\n", error);
362 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
363 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
364 error = pm_clk_add_clk(dev, clk);
366 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
376 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
379 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
384 static bool rockchip_active_wakeup(struct device *dev)
386 struct generic_pm_domain *genpd;
387 struct rockchip_pm_domain *pd;
389 genpd = pd_to_genpd(dev->pm_domain);
390 pd = container_of(genpd, struct rockchip_pm_domain, genpd);
392 return pd->info->active_wakeup;
395 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
396 struct device_node *node)
398 const struct rockchip_domain_info *pd_info;
399 struct rockchip_pm_domain *pd;
400 struct device_node *qos_node;
407 error = of_property_read_u32(node, "reg", &id);
410 "%s: failed to retrieve domain id (reg): %d\n",
415 if (id >= pmu->info->num_domains) {
416 dev_err(pmu->dev, "%s: invalid domain id %d\n",
421 pd_info = &pmu->info->domain_info[id];
423 dev_err(pmu->dev, "%s: undefined domain id %d\n",
428 clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
429 pd = devm_kzalloc(pmu->dev,
430 sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
438 for (i = 0; i < clk_cnt; i++) {
439 clk = of_clk_get(node, i);
441 error = PTR_ERR(clk);
443 "%s: failed to get clk at index %d: %d\n",
444 node->name, i, error);
448 error = clk_prepare(clk);
451 "%s: failed to prepare clk %pC (index %d): %d\n",
452 node->name, clk, i, error);
457 pd->clks[pd->num_clks++] = clk;
459 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
463 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
466 if (pd->num_qos > 0) {
467 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
468 sizeof(*pd->qos_regmap),
470 if (!pd->qos_regmap) {
475 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
476 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
480 if (!pd->qos_save_regs[j]) {
486 for (j = 0; j < pd->num_qos; j++) {
487 qos_node = of_parse_phandle(node, "pm_qos", j);
492 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
493 if (IS_ERR(pd->qos_regmap[j])) {
495 of_node_put(qos_node);
498 of_node_put(qos_node);
502 error = rockchip_pd_power(pd, true);
505 "failed to power on domain '%s': %d\n",
510 pd->genpd.name = node->name;
511 pd->genpd.power_off = rockchip_pd_power_off;
512 pd->genpd.power_on = rockchip_pd_power_on;
513 pd->genpd.attach_dev = rockchip_pd_attach_dev;
514 pd->genpd.detach_dev = rockchip_pd_detach_dev;
515 pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
516 pd->genpd.flags = GENPD_FLAG_PM_CLK;
517 pm_genpd_init(&pd->genpd, NULL, false);
519 pmu->genpd_data.domains[id] = &pd->genpd;
524 clk_unprepare(pd->clks[i]);
525 clk_put(pd->clks[i]);
530 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
534 for (i = 0; i < pd->num_clks; i++) {
535 clk_unprepare(pd->clks[i]);
536 clk_put(pd->clks[i]);
539 /* protect the zeroing of pm->num_clks */
540 mutex_lock(&pd->pmu->mutex);
542 mutex_unlock(&pd->pmu->mutex);
544 /* devm will free our memory */
547 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
549 struct generic_pm_domain *genpd;
550 struct rockchip_pm_domain *pd;
553 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
554 genpd = pmu->genpd_data.domains[i];
556 pd = to_rockchip_pd(genpd);
557 rockchip_pm_remove_one_domain(pd);
561 /* devm will free our memory */
564 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
565 u32 domain_reg_offset,
568 /* First configure domain power down transition count ... */
569 regmap_write(pmu->regmap, domain_reg_offset, count);
570 /* ... and then power up count. */
571 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
574 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
575 struct device_node *parent)
577 struct device_node *np;
578 struct generic_pm_domain *child_domain, *parent_domain;
581 for_each_child_of_node(parent, np) {
584 error = of_property_read_u32(parent, "reg", &idx);
587 "%s: failed to retrieve domain id (reg): %d\n",
588 parent->name, error);
591 parent_domain = pmu->genpd_data.domains[idx];
593 error = rockchip_pm_add_one_domain(pmu, np);
595 dev_err(pmu->dev, "failed to handle node %s: %d\n",
600 error = of_property_read_u32(np, "reg", &idx);
603 "%s: failed to retrieve domain id (reg): %d\n",
607 child_domain = pmu->genpd_data.domains[idx];
609 error = pm_genpd_add_subdomain(parent_domain, child_domain);
611 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
612 parent_domain->name, child_domain->name, error);
615 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
616 parent_domain->name, child_domain->name);
619 rockchip_pm_add_subdomain(pmu, np);
629 static int rockchip_pm_domain_probe(struct platform_device *pdev)
631 struct device *dev = &pdev->dev;
632 struct device_node *np = dev->of_node;
633 struct device_node *node;
634 struct device *parent;
635 struct rockchip_pmu *pmu;
636 const struct of_device_id *match;
637 const struct rockchip_pmu_info *pmu_info;
641 dev_err(dev, "device tree node not found\n");
645 match = of_match_device(dev->driver->of_match_table, dev);
646 if (!match || !match->data) {
647 dev_err(dev, "missing pmu data\n");
651 pmu_info = match->data;
653 pmu = devm_kzalloc(dev,
655 pmu_info->num_domains * sizeof(pmu->domains[0]),
660 pmu->dev = &pdev->dev;
661 mutex_init(&pmu->mutex);
663 pmu->info = pmu_info;
665 pmu->genpd_data.domains = pmu->domains;
666 pmu->genpd_data.num_domains = pmu_info->num_domains;
668 parent = dev->parent;
670 dev_err(dev, "no parent for syscon devices\n");
674 pmu->regmap = syscon_node_to_regmap(parent->of_node);
675 if (IS_ERR(pmu->regmap)) {
676 dev_err(dev, "no regmap available\n");
677 return PTR_ERR(pmu->regmap);
681 * Configure power up and down transition delays for CORE
684 if (pmu_info->core_pwrcnt_offset)
685 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
686 pmu_info->core_power_transition_time);
687 if (pmu_info->gpu_pwrcnt_offset)
688 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
689 pmu_info->gpu_power_transition_time);
693 for_each_available_child_of_node(np, node) {
694 error = rockchip_pm_add_one_domain(pmu, node);
696 dev_err(dev, "failed to handle node %s: %d\n",
702 error = rockchip_pm_add_subdomain(pmu, node);
704 dev_err(dev, "failed to handle subdomain node %s: %d\n",
712 dev_dbg(dev, "no power domains defined\n");
716 of_genpd_add_provider_onecell(np, &pmu->genpd_data);
721 rockchip_pm_domain_cleanup(pmu);
725 static const struct rockchip_domain_info rk3288_pm_domains[] = {
726 [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4, false),
727 [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9, false),
728 [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3, false),
729 [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false),
732 static const struct rockchip_domain_info rk3328_pm_domains[] = {
733 [RK3328_PD_CORE] = DOMAIN_RK3328(-1, 0, 0, false),
734 [RK3328_PD_GPU] = DOMAIN_RK3328(-1, 1, 1, false),
735 [RK3328_PD_BUS] = DOMAIN_RK3328(-1, 2, 2, true),
736 [RK3328_PD_MSCH] = DOMAIN_RK3328(-1, 3, 3, true),
737 [RK3328_PD_PERI] = DOMAIN_RK3328(-1, 4, 4, true),
738 [RK3328_PD_VIDEO] = DOMAIN_RK3328(-1, 5, 5, false),
739 [RK3328_PD_HEVC] = DOMAIN_RK3328(-1, 6, 6, false),
740 [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false),
741 [RK3328_PD_VPU] = DOMAIN_RK3328(-1, 9, 9, false),
744 static const struct rockchip_domain_info rk3366_pm_domains[] = {
745 [RK3366_PD_PERI] = DOMAIN_RK3368(10, 10, 6, true),
746 [RK3366_PD_VIO] = DOMAIN_RK3368(14, 14, 8, false),
747 [RK3366_PD_VIDEO] = DOMAIN_RK3368(13, 13, 7, false),
748 [RK3366_PD_RKVDEC] = DOMAIN_RK3368(11, 11, 7, false),
749 [RK3366_PD_WIFIBT] = DOMAIN_RK3368(8, 8, 9, false),
750 [RK3366_PD_VPU] = DOMAIN_RK3368(12, 12, 7, false),
751 [RK3366_PD_GPU] = DOMAIN_RK3368(15, 15, 2, false),
754 static const struct rockchip_domain_info rk3368_pm_domains[] = {
755 [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true),
756 [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false),
757 [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7, false),
758 [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2, false),
759 [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2, false),
762 static const struct rockchip_domain_info rk3399_pm_domains[] = {
763 [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1, false),
764 [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1, false),
765 [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1, true),
766 [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15, true),
767 [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16, true),
768 [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1, true),
769 [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2, true),
770 [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14, true),
771 [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17, false),
772 [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0, false),
773 [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3, false),
774 [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4, false),
775 [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5, false),
776 [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6, false),
777 [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1, false),
778 [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7, false),
779 [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8, false),
780 [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9, false),
781 [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10, false),
782 [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11, false),
783 [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23, true),
784 [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24, true),
785 [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12, true),
786 [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22, false),
787 [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27, true),
788 [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28, true),
789 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29, true),
792 static const struct rockchip_pmu_info rk3288_pmu = {
794 .status_offset = 0x0c,
799 .core_pwrcnt_offset = 0x34,
800 .gpu_pwrcnt_offset = 0x3c,
802 .core_power_transition_time = 24, /* 1us */
803 .gpu_power_transition_time = 24, /* 1us */
805 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
806 .domain_info = rk3288_pm_domains,
809 static const struct rockchip_pmu_info rk3328_pmu = {
811 .idle_offset = 0x484,
814 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
815 .domain_info = rk3328_pm_domains,
818 static const struct rockchip_pmu_info rk3366_pmu = {
820 .status_offset = 0x10,
825 .core_pwrcnt_offset = 0x48,
826 .gpu_pwrcnt_offset = 0x50,
828 .core_power_transition_time = 24,
829 .gpu_power_transition_time = 24,
831 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
832 .domain_info = rk3366_pm_domains,
835 static const struct rockchip_pmu_info rk3368_pmu = {
837 .status_offset = 0x10,
842 .core_pwrcnt_offset = 0x48,
843 .gpu_pwrcnt_offset = 0x50,
845 .core_power_transition_time = 24,
846 .gpu_power_transition_time = 24,
848 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
849 .domain_info = rk3368_pm_domains,
852 static const struct rockchip_pmu_info rk3399_pmu = {
854 .status_offset = 0x18,
859 .core_pwrcnt_offset = 0xac,
860 .gpu_pwrcnt_offset = 0xac,
862 .core_power_transition_time = 6, /* 0.25us */
863 .gpu_power_transition_time = 6, /* 0.25us */
865 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
866 .domain_info = rk3399_pm_domains,
869 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
871 .compatible = "rockchip,rk3288-power-controller",
872 .data = (void *)&rk3288_pmu,
875 .compatible = "rockchip,rk3328-power-controller",
876 .data = (void *)&rk3328_pmu,
879 .compatible = "rockchip,rk3366-power-controller",
880 .data = (void *)&rk3366_pmu,
883 .compatible = "rockchip,rk3368-power-controller",
884 .data = (void *)&rk3368_pmu,
887 .compatible = "rockchip,rk3399-power-controller",
888 .data = (void *)&rk3399_pmu,
893 static struct platform_driver rockchip_pm_domain_driver = {
894 .probe = rockchip_pm_domain_probe,
896 .name = "rockchip-pm-domain",
897 .of_match_table = rockchip_pm_domain_dt_match,
899 * We can't forcibly eject devices form power domain,
900 * so we can't really remove power domains once they
903 .suppress_bind_attrs = true,
907 static int __init rockchip_pm_domain_drv_register(void)
909 return platform_driver_register(&rockchip_pm_domain_driver);
911 postcore_initcall(rockchip_pm_domain_drv_register);