drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/err.h>
  14 #include <linux/pm_clock.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/clk.h>
  19 #include <linux/regmap.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <dt-bindings/power/rk3288-power.h>
  22 #include <dt-bindings/power/rk3366-power.h>
  23 #include <dt-bindings/power/rk3368-power.h>
  24 #include <dt-bindings/power/rk3399-power.h>
  25
  26 struct rockchip_domain_info {
  27         int pwr_mask;
  28         int status_mask;
  29         int req_mask;
  30         int idle_mask;
  31         int ack_mask;
  32         bool active_wakeup;
  33 };
  34
  35 struct rockchip_pmu_info {
  36         u32 pwr_offset;
  37         u32 status_offset;
  38         u32 req_offset;
  39         u32 idle_offset;
  40         u32 ack_offset;
  41
  42         u32 core_pwrcnt_offset;
  43         u32 gpu_pwrcnt_offset;
  44
  45         unsigned int core_power_transition_time;
  46         unsigned int gpu_power_transition_time;
  47
  48         int num_domains;
  49         const struct rockchip_domain_info *domain_info;
  50 };
  51
  52 #define MAX_QOS_REGS_NUM        5
  53 #define QOS_PRIORITY            0x08
  54 #define QOS_MODE                0x0c
  55 #define QOS_BANDWIDTH           0x10
  56 #define QOS_SATURATION          0x14
  57 #define QOS_EXTCONTROL          0x18
  58
  59 struct rockchip_pm_domain {
  60         struct generic_pm_domain genpd;
  61         const struct rockchip_domain_info *info;
  62         struct rockchip_pmu *pmu;
  63         int num_qos;
  64         struct regmap **qos_regmap;
  65         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  66         int num_clks;
  67         struct clk *clks[];
  68 };
  69
  70 struct rockchip_pmu {
  71         struct device *dev;
  72         struct regmap *regmap;
  73         const struct rockchip_pmu_info *info;
  74         struct mutex mutex; /* mutex lock for pmu */
  75         struct genpd_onecell_data genpd_data;
  76         struct generic_pm_domain *domains[];
  77 };
  78
  79 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  80
  81 #define DOMAIN(pwr, status, req, idle, ack, wakeup)     \
  82 {                                               \
  83         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  84         .status_mask = (status >= 0) ? BIT(status) : 0, \
  85         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  86         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  87         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  88         .active_wakeup = wakeup,                        \
  89 }
  90
  91 #define DOMAIN_RK3288(pwr, status, req, wakeup)         \
  92         DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
  93
  94 #define DOMAIN_RK3368(pwr, status, req, wakeup)         \
  95         DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
  96
  97 #define DOMAIN_RK3399(pwr, status, req, wakeup)         \
  98         DOMAIN(pwr, status, req, req, req, wakeup)
  99
 100 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 101 {
 102         struct rockchip_pmu *pmu = pd->pmu;
 103         const struct rockchip_domain_info *pd_info = pd->info;
 104         unsigned int val;
 105
 106         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 107         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 108 }
 109
 110 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
 111 {
 112         unsigned int val;
 113
 114         regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 115         return val;
 116 }
 117
 118 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 119                                          bool idle)
 120 {
 121         const struct rockchip_domain_info *pd_info = pd->info;
 122         struct generic_pm_domain *genpd = &pd->genpd;
 123         struct rockchip_pmu *pmu = pd->pmu;
 124         unsigned int target_ack;
 125         unsigned int val;
 126         bool is_idle;
 127         int ret;
 128
 129         if (pd_info->req_mask == 0)
 130                 return 0;
 131
 132         regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 133                            pd_info->req_mask, idle ? -1U : 0);
 134
 135         dsb(sy);
 136
 137         /* Wait util idle_ack = 1 */
 138         target_ack = idle ? pd_info->ack_mask : 0;
 139         ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
 140                                         (val & pd_info->ack_mask) == target_ack,
 141                                         0, 10000);
 142         if (ret) {
 143                 dev_err(pmu->dev,
 144                         "failed to get ack on domain '%s', val=0x%x\n",
 145                         genpd->name, val);
 146                 return ret;
 147         }
 148
 149         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
 150                                         is_idle, is_idle == idle, 0, 10000);
 151         if (ret) {
 152                 dev_err(pmu->dev,
 153                         "failed to set idle on domain '%s', val=%d\n",
 154                         genpd->name, is_idle);
 155                 return ret;
 156         }
 157
 158         return 0;
 159 }
 160
 161 int rockchip_pmu_idle_request(struct device *dev, bool idle)
 162 {
 163         struct generic_pm_domain *genpd;
 164         struct rockchip_pm_domain *pd;
 165         int ret;
 166
 167         if (IS_ERR_OR_NULL(dev))
 168                 return -EINVAL;
 169
 170         if (IS_ERR_OR_NULL(dev->pm_domain))
 171                 return -EINVAL;
 172
 173         genpd = pd_to_genpd(dev->pm_domain);
 174         pd = to_rockchip_pd(genpd);
 175
 176         mutex_lock(&pd->pmu->mutex);
 177         ret = rockchip_pmu_set_idle_request(pd, idle);
 178         mutex_unlock(&pd->pmu->mutex);
 179
 180         return ret;
 181 }
 182 EXPORT_SYMBOL(rockchip_pmu_idle_request);
 183
 184 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 185 {
 186         int i;
 187
 188         for (i = 0; i < pd->num_qos; i++) {
 189                 regmap_read(pd->qos_regmap[i],
 190                             QOS_PRIORITY,
 191                             &pd->qos_save_regs[0][i]);
 192                 regmap_read(pd->qos_regmap[i],
 193                             QOS_MODE,
 194                             &pd->qos_save_regs[1][i]);
 195                 regmap_read(pd->qos_regmap[i],
 196                             QOS_BANDWIDTH,
 197                             &pd->qos_save_regs[2][i]);
 198                 regmap_read(pd->qos_regmap[i],
 199                             QOS_SATURATION,
 200                             &pd->qos_save_regs[3][i]);
 201                 regmap_read(pd->qos_regmap[i],
 202                             QOS_EXTCONTROL,
 203                             &pd->qos_save_regs[4][i]);
 204         }
 205         return 0;
 206 }
 207
 208 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 209 {
 210         int i;
 211
 212         for (i = 0; i < pd->num_qos; i++) {
 213                 regmap_write(pd->qos_regmap[i],
 214                              QOS_PRIORITY,
 215                              pd->qos_save_regs[0][i]);
 216                 regmap_write(pd->qos_regmap[i],
 217                              QOS_MODE,
 218                              pd->qos_save_regs[1][i]);
 219                 regmap_write(pd->qos_regmap[i],
 220                              QOS_BANDWIDTH,
 221                              pd->qos_save_regs[2][i]);
 222                 regmap_write(pd->qos_regmap[i],
 223                              QOS_SATURATION,
 224                              pd->qos_save_regs[3][i]);
 225                 regmap_write(pd->qos_regmap[i],
 226                              QOS_EXTCONTROL,
 227                              pd->qos_save_regs[4][i]);
 228         }
 229
 230         return 0;
 231 }
 232
 233 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 234 {
 235         struct rockchip_pmu *pmu = pd->pmu;
 236         unsigned int val;
 237
 238         /* check idle status for idle-only domains */
 239         if (pd->info->status_mask == 0)
 240                 return !rockchip_pmu_domain_is_idle(pd);
 241
 242         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 243
 244         /* 1'b0: power on, 1'b1: power off */
 245         return !(val & pd->info->status_mask);
 246 }
 247
 248 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 249                                              bool on)
 250 {
 251         struct rockchip_pmu *pmu = pd->pmu;
 252         struct generic_pm_domain *genpd = &pd->genpd;
 253         bool is_on;
 254
 255         if (pd->info->pwr_mask == 0)
 256                 return;
 257
 258         regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 259                            pd->info->pwr_mask, on ? 0 : -1U);
 260
 261         dsb(sy);
 262
 263         if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
 264                                       is_on == on, 0, 10000)) {
 265                 dev_err(pmu->dev,
 266                         "failed to set domain '%s', val=%d\n",
 267                         genpd->name, is_on);
 268                 return;
 269         }
 270 }
 271
 272 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 273 {
 274         int i;
 275
 276         mutex_lock(&pd->pmu->mutex);
 277
 278         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 279                 for (i = 0; i < pd->num_clks; i++)
 280                         clk_enable(pd->clks[i]);
 281
 282                 if (!power_on) {
 283                         rockchip_pmu_save_qos(pd);
 284
 285                         /* if powering down, idle request to NIU first */
 286                         rockchip_pmu_set_idle_request(pd, true);
 287                 }
 288
 289                 rockchip_do_pmu_set_power_domain(pd, power_on);
 290
 291                 if (power_on) {
 292                         /* if powering up, leave idle mode */
 293                         rockchip_pmu_set_idle_request(pd, false);
 294
 295                         rockchip_pmu_restore_qos(pd);
 296                 }
 297
 298                 for (i = pd->num_clks - 1; i >= 0; i--)
 299                         clk_disable(pd->clks[i]);
 300         }
 301
 302         mutex_unlock(&pd->pmu->mutex);
 303         return 0;
 304 }
 305
 306 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 307 {
 308         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 309
 310         return rockchip_pd_power(pd, true);
 311 }
 312
 313 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 314 {
 315         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 316
 317         return rockchip_pd_power(pd, false);
 318 }
 319
 320 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 321                                   struct device *dev)
 322 {
 323         struct clk *clk;
 324         int i;
 325         int error;
 326
 327         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 328
 329         error = pm_clk_create(dev);
 330         if (error) {
 331                 dev_err(dev, "pm_clk_create failed %d\n", error);
 332                 return error;
 333         }
 334
 335         i = 0;
 336         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 337                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 338                 error = pm_clk_add_clk(dev, clk);
 339                 if (error) {
 340                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 341                         clk_put(clk);
 342                         pm_clk_destroy(dev);
 343                         return error;
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 351                                    struct device *dev)
 352 {
 353         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 354
 355         pm_clk_destroy(dev);
 356 }
 357
 358 static bool rockchip_active_wakeup(struct device *dev)
 359 {
 360         struct generic_pm_domain *genpd;
 361         struct rockchip_pm_domain *pd;
 362
 363         genpd = pd_to_genpd(dev->pm_domain);
 364         pd = container_of(genpd, struct rockchip_pm_domain, genpd);
 365
 366         return pd->info->active_wakeup;
 367 }
 368
 369 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 370                                       struct device_node *node)
 371 {
 372         const struct rockchip_domain_info *pd_info;
 373         struct rockchip_pm_domain *pd;
 374         struct device_node *qos_node;
 375         struct clk *clk;
 376         int clk_cnt;
 377         int i, j;
 378         u32 id;
 379         int error;
 380
 381         error = of_property_read_u32(node, "reg", &id);
 382         if (error) {
 383                 dev_err(pmu->dev,
 384                         "%s: failed to retrieve domain id (reg): %d\n",
 385                         node->name, error);
 386                 return -EINVAL;
 387         }
 388
 389         if (id >= pmu->info->num_domains) {
 390                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 391                         node->name, id);
 392                 return -EINVAL;
 393         }
 394
 395         pd_info = &pmu->info->domain_info[id];
 396         if (!pd_info) {
 397                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 398                         node->name, id);
 399                 return -EINVAL;
 400         }
 401
 402         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 403         pd = devm_kzalloc(pmu->dev,
 404                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 405                           GFP_KERNEL);
 406         if (!pd)
 407                 return -ENOMEM;
 408
 409         pd->info = pd_info;
 410         pd->pmu = pmu;
 411
 412         for (i = 0; i < clk_cnt; i++) {
 413                 clk = of_clk_get(node, i);
 414                 if (IS_ERR(clk)) {
 415                         error = PTR_ERR(clk);
 416                         dev_err(pmu->dev,
 417                                 "%s: failed to get clk at index %d: %d\n",
 418                                 node->name, i, error);
 419                         goto err_out;
 420                 }
 421
 422                 error = clk_prepare(clk);
 423                 if (error) {
 424                         dev_err(pmu->dev,
 425                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 426                                 node->name, clk, i, error);
 427                         clk_put(clk);
 428                         goto err_out;
 429                 }
 430
 431                 pd->clks[pd->num_clks++] = clk;
 432
 433                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 434                         clk, node->name);
 435         }
 436
 437         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 438                                                  NULL);
 439
 440         if (pd->num_qos > 0) {
 441                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 442                                               sizeof(*pd->qos_regmap),
 443                                               GFP_KERNEL);
 444                 if (!pd->qos_regmap) {
 445                         error = -ENOMEM;
 446                         goto err_out;
 447                 }
 448
 449                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 450                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 451                                                             pd->num_qos,
 452                                                             sizeof(u32),
 453                                                             GFP_KERNEL);
 454                         if (!pd->qos_save_regs[j]) {
 455                                 error = -ENOMEM;
 456                                 goto err_out;
 457                         }
 458                 }
 459
 460                 for (j = 0; j < pd->num_qos; j++) {
 461                         qos_node = of_parse_phandle(node, "pm_qos", j);
 462                         if (!qos_node) {
 463                                 error = -ENODEV;
 464                                 goto err_out;
 465                         }
 466                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 467                         if (IS_ERR(pd->qos_regmap[j])) {
 468                                 error = -ENODEV;
 469                                 of_node_put(qos_node);
 470                                 goto err_out;
 471                         }
 472                         of_node_put(qos_node);
 473                 }
 474         }
 475
 476         error = rockchip_pd_power(pd, true);
 477         if (error) {
 478                 dev_err(pmu->dev,
 479                         "failed to power on domain '%s': %d\n",
 480                         node->name, error);
 481                 goto err_out;
 482         }
 483
 484         pd->genpd.name = node->name;
 485         pd->genpd.power_off = rockchip_pd_power_off;
 486         pd->genpd.power_on = rockchip_pd_power_on;
 487         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 488         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 489         pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
 490         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 491         pm_genpd_init(&pd->genpd, NULL, false);
 492
 493         pmu->genpd_data.domains[id] = &pd->genpd;
 494         return 0;
 495
 496 err_out:
 497         while (--i >= 0) {
 498                 clk_unprepare(pd->clks[i]);
 499                 clk_put(pd->clks[i]);
 500         }
 501         return error;
 502 }
 503
 504 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 505 {
 506         int i;
 507
 508         for (i = 0; i < pd->num_clks; i++) {
 509                 clk_unprepare(pd->clks[i]);
 510                 clk_put(pd->clks[i]);
 511         }
 512
 513         /* protect the zeroing of pm->num_clks */
 514         mutex_lock(&pd->pmu->mutex);
 515         pd->num_clks = 0;
 516         mutex_unlock(&pd->pmu->mutex);
 517
 518         /* devm will free our memory */
 519 }
 520
 521 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 522 {
 523         struct generic_pm_domain *genpd;
 524         struct rockchip_pm_domain *pd;
 525         int i;
 526
 527         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 528                 genpd = pmu->genpd_data.domains[i];
 529                 if (genpd) {
 530                         pd = to_rockchip_pd(genpd);
 531                         rockchip_pm_remove_one_domain(pd);
 532                 }
 533         }
 534
 535         /* devm will free our memory */
 536 }
 537
 538 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 539                                       u32 domain_reg_offset,
 540                                       unsigned int count)
 541 {
 542         /* First configure domain power down transition count ... */
 543         regmap_write(pmu->regmap, domain_reg_offset, count);
 544         /* ... and then power up count. */
 545         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 546 }
 547
 548 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 549                                      struct device_node *parent)
 550 {
 551         struct device_node *np;
 552         struct generic_pm_domain *child_domain, *parent_domain;
 553         int error;
 554
 555         for_each_child_of_node(parent, np) {
 556                 u32 idx;
 557
 558                 error = of_property_read_u32(parent, "reg", &idx);
 559                 if (error) {
 560                         dev_err(pmu->dev,
 561                                 "%s: failed to retrieve domain id (reg): %d\n",
 562                                 parent->name, error);
 563                         goto err_out;
 564                 }
 565                 parent_domain = pmu->genpd_data.domains[idx];
 566
 567                 error = rockchip_pm_add_one_domain(pmu, np);
 568                 if (error) {
 569                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 570                                 np->name, error);
 571                         goto err_out;
 572                 }
 573
 574                 error = of_property_read_u32(np, "reg", &idx);
 575                 if (error) {
 576                         dev_err(pmu->dev,
 577                                 "%s: failed to retrieve domain id (reg): %d\n",
 578                                 np->name, error);
 579                         goto err_out;
 580                 }
 581                 child_domain = pmu->genpd_data.domains[idx];
 582
 583                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 584                 if (error) {
 585                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 586                                 parent_domain->name, child_domain->name, error);
 587                         goto err_out;
 588                 } else {
 589                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 590                                 parent_domain->name, child_domain->name);
 591                 }
 592
 593                 rockchip_pm_add_subdomain(pmu, np);
 594         }
 595
 596         return 0;
 597
 598 err_out:
 599         of_node_put(np);
 600         return error;
 601 }
 602
 603 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 604 {
 605         struct device *dev = &pdev->dev;
 606         struct device_node *np = dev->of_node;
 607         struct device_node *node;
 608         struct device *parent;
 609         struct rockchip_pmu *pmu;
 610         const struct of_device_id *match;
 611         const struct rockchip_pmu_info *pmu_info;
 612         int error;
 613
 614         if (!np) {
 615                 dev_err(dev, "device tree node not found\n");
 616                 return -ENODEV;
 617         }
 618
 619         match = of_match_device(dev->driver->of_match_table, dev);
 620         if (!match || !match->data) {
 621                 dev_err(dev, "missing pmu data\n");
 622                 return -EINVAL;
 623         }
 624
 625         pmu_info = match->data;
 626
 627         pmu = devm_kzalloc(dev,
 628                            sizeof(*pmu) +
 629                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 630                            GFP_KERNEL);
 631         if (!pmu)
 632                 return -ENOMEM;
 633
 634         pmu->dev = &pdev->dev;
 635         mutex_init(&pmu->mutex);
 636
 637         pmu->info = pmu_info;
 638
 639         pmu->genpd_data.domains = pmu->domains;
 640         pmu->genpd_data.num_domains = pmu_info->num_domains;
 641
 642         parent = dev->parent;
 643         if (!parent) {
 644                 dev_err(dev, "no parent for syscon devices\n");
 645                 return -ENODEV;
 646         }
 647
 648         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 649         if (IS_ERR(pmu->regmap)) {
 650                 dev_err(dev, "no regmap available\n");
 651                 return PTR_ERR(pmu->regmap);
 652         }
 653
 654         /*
 655          * Configure power up and down transition delays for CORE
 656          * and GPU domains.
 657          */
 658         rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 659                                   pmu_info->core_power_transition_time);
 660         rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 661                                   pmu_info->gpu_power_transition_time);
 662
 663         error = -ENODEV;
 664
 665         for_each_available_child_of_node(np, node) {
 666                 error = rockchip_pm_add_one_domain(pmu, node);
 667                 if (error) {
 668                         dev_err(dev, "failed to handle node %s: %d\n",
 669                                 node->name, error);
 670                         of_node_put(node);
 671                         goto err_out;
 672                 }
 673
 674                 error = rockchip_pm_add_subdomain(pmu, node);
 675                 if (error < 0) {
 676                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 677                                 node->name, error);
 678                         of_node_put(node);
 679                         goto err_out;
 680                 }
 681         }
 682
 683         if (error) {
 684                 dev_dbg(dev, "no power domains defined\n");
 685                 goto err_out;
 686         }
 687
 688         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 689
 690         return 0;
 691
 692 err_out:
 693         rockchip_pm_domain_cleanup(pmu);
 694         return error;
 695 }
 696
 697 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 698         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4, false),
 699         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9, false),
 700         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3, false),
 701         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2, false),
 702 };
 703
 704 static const struct rockchip_domain_info rk3366_pm_domains[] = {
 705         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6, true),
 706         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8, false),
 707         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7, false),
 708         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7, false),
 709         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9, false),
 710         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7, false),
 711         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2, false),
 712 };
 713
 714 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 715         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6, true),
 716         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8, false),
 717         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7, false),
 718         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2, false),
 719         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2, false),
 720 };
 721
 722 static const struct rockchip_domain_info rk3399_pm_domains[] = {
 723         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1, false),
 724         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1, false),
 725         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1, true),
 726         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15, true),
 727         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16, true),
 728         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1, true),
 729         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2, true),
 730         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14, true),
 731         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17, false),
 732         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0, false),
 733         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3, false),
 734         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4, false),
 735         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5, false),
 736         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6, false),
 737         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1, false),
 738         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7, false),
 739         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8, false),
 740         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9, false),
 741         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10, false),
 742         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11, false),
 743         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23, true),
 744         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24, true),
 745         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12, true),
 746         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22, false),
 747         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27, true),
 748         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28, true),
 749         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29, true),
 750 };
 751
 752 static const struct rockchip_pmu_info rk3288_pmu = {
 753         .pwr_offset = 0x08,
 754         .status_offset = 0x0c,
 755         .req_offset = 0x10,
 756         .idle_offset = 0x14,
 757         .ack_offset = 0x14,
 758
 759         .core_pwrcnt_offset = 0x34,
 760         .gpu_pwrcnt_offset = 0x3c,
 761
 762         .core_power_transition_time = 24, /* 1us */
 763         .gpu_power_transition_time = 24, /* 1us */
 764
 765         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 766         .domain_info = rk3288_pm_domains,
 767 };
 768
 769 static const struct rockchip_pmu_info rk3366_pmu = {
 770         .pwr_offset = 0x0c,
 771         .status_offset = 0x10,
 772         .req_offset = 0x3c,
 773         .idle_offset = 0x40,
 774         .ack_offset = 0x40,
 775
 776         .core_pwrcnt_offset = 0x48,
 777         .gpu_pwrcnt_offset = 0x50,
 778
 779         .core_power_transition_time = 24,
 780         .gpu_power_transition_time = 24,
 781
 782         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
 783         .domain_info = rk3366_pm_domains,
 784 };
 785
 786 static const struct rockchip_pmu_info rk3368_pmu = {
 787         .pwr_offset = 0x0c,
 788         .status_offset = 0x10,
 789         .req_offset = 0x3c,
 790         .idle_offset = 0x40,
 791         .ack_offset = 0x40,
 792
 793         .core_pwrcnt_offset = 0x48,
 794         .gpu_pwrcnt_offset = 0x50,
 795
 796         .core_power_transition_time = 24,
 797         .gpu_power_transition_time = 24,
 798
 799         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 800         .domain_info = rk3368_pm_domains,
 801 };
 802
 803 static const struct rockchip_pmu_info rk3399_pmu = {
 804         .pwr_offset = 0x14,
 805         .status_offset = 0x18,
 806         .req_offset = 0x60,
 807         .idle_offset = 0x64,
 808         .ack_offset = 0x68,
 809
 810         .core_pwrcnt_offset = 0xac,
 811         .gpu_pwrcnt_offset = 0xac,
 812
 813         .core_power_transition_time = 6, /* 0.25us */
 814         .gpu_power_transition_time = 6, /* 0.25us */
 815
 816         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
 817         .domain_info = rk3399_pm_domains,
 818 };
 819
 820 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 821         {
 822                 .compatible = "rockchip,rk3288-power-controller",
 823                 .data = (void *)&rk3288_pmu,
 824         },
 825         {
 826                 .compatible = "rockchip,rk3366-power-controller",
 827                 .data = (void *)&rk3366_pmu,
 828         },
 829         {
 830                 .compatible = "rockchip,rk3368-power-controller",
 831                 .data = (void *)&rk3368_pmu,
 832         },
 833         {
 834                 .compatible = "rockchip,rk3399-power-controller",
 835                 .data = (void *)&rk3399_pmu,
 836         },
 837         { /* sentinel */ },
 838 };
 839
 840 static struct platform_driver rockchip_pm_domain_driver = {
 841         .probe = rockchip_pm_domain_probe,
 842         .driver = {
 843                 .name   = "rockchip-pm-domain",
 844                 .of_match_table = rockchip_pm_domain_dt_match,
 845                 /*
 846                  * We can't forcibly eject devices form power domain,
 847                  * so we can't really remove power domains once they
 848                  * were added.
 849                  */
 850                 .suppress_bind_attrs = true,
 851         },
 852 };
 853
 854 static int __init rockchip_pm_domain_drv_register(void)
 855 {
 856         return platform_driver_register(&rockchip_pm_domain_driver);
 857 }
 858 postcore_initcall(rockchip_pm_domain_drv_register);