drivers/smc/rk29_smc.c

   1 #include <linux/module.h>\r
   2 #include <linux/kernel.h>\r
   3 #include <linux/errno.h>\r
   4 #include <linux/string.h>\r
   5 #include <linux/mm.h>\r
   6 #include <linux/slab.h>\r
   7 #include <linux/delay.h>\r
   8 #include <linux/device.h>\r
   9 #include <linux/init.h>\r
  10 #include <linux/dma-mapping.h>\r
  11 #include <linux/interrupt.h>\r
  12 #include <linux/platform_device.h>\r
  13 #include <linux/clk.h>\r
  14 #include <linux/backlight.h>\r
  15 #include <linux/timer.h>\r
  16 #include <linux/time.h>\r
  17 #include <linux/wait.h>\r
  18 #include <linux/earlysuspend.h>\r
  19 #include <linux/cpufreq.h>\r
  20 #include <linux/wakelock.h>\r
  21 \r
  22 #include <asm/io.h>\r
  23 #include <asm/div64.h>\r
  24 #include <asm/uaccess.h>\r
  25 \r
  26 \r
  27 #include <mach/iomux.h>\r
  28 #include <mach/gpio.h>\r
  29 #include <mach/board.h>\r
  30 #include <mach/rk29_iomap.h>\r
  31 #include <mach/pmu.h>\r
  32 \r
  33 void __iomem *rank0_vir_base;  // virtual basic address of lcdc register\r
  34 struct clk      *smc_clk = NULL;\r
  35 struct clk      *smc_axi_clk = NULL;\r
  36 void __iomem *reg_vir_base;  // virtual basic address of lcdc register\r
  37 \r
  38 int smc0_enable(int enable)\r
  39 {\r
  40     if(enable){\r
  41         clk_enable(smc_axi_clk);\r
  42         clk_enable(smc_clk);\r
  43         __raw_writel(__raw_readl(RK29_GRF_BASE+0xbc) | 0x2000 , (RK29_GRF_BASE+0xbc));\r
  44 \r
  45         __raw_writel((0x801), (reg_vir_base+0x18));\r
  46         __raw_writel(0x00400000, (reg_vir_base+0x10));\r
  47         __raw_writel((15 | (14<<8) | (15<<4) | (5<<11) ), (reg_vir_base+0x14));\r
  48         //__raw_writel((15 | (10<<8) | (15<<4) | (7<<11) ), (reg_vir_base+0x14));\r
  49 \r
  50         __raw_writel(0x00400000, (reg_vir_base+0x10));\r
  51     }   else    {\r
  52         clk_disable(smc_axi_clk);\r
  53         clk_disable(smc_clk);\r
  54     }\r
  55     return 0;\r
  56 }\r
  57 \r
  58 int smc0_init(u8 **base_addr)\r
  59 {\r
  60     u32 reg_phy_base;       // physical basic address of lcdc register\r
  61         u32 len;               // physical map length of lcdc register\r
  62     struct resource *mem;\r
  63 \r
  64     u32 rank0_phy_base;       // physical basic address of lcdc register\r
  65         u32 rank0_len;               // physical map length of lcdc register\r
  66     struct resource *rank0_mem;\r
  67 \r
  68     printk(" %s %d \n",__FUNCTION__, __LINE__);\r
  69 \r
  70     if(smc_axi_clk == NULL)smc_axi_clk = clk_get(NULL, "aclk_smc");\r
  71     if(smc_clk == NULL)smc_clk = clk_get(NULL, "smc");\r
  72 \r
  73     rank0_phy_base = 0x11000000;  //0x12000000;//\r
  74     rank0_len = SZ_4K;\r
  75     rank0_mem = request_mem_region(rank0_phy_base, rank0_len, "smc_rank0");\r
  76     if (rank0_mem == NULL)\r
  77     {\r
  78         printk("failed to get rank0 memory region [%d]\n",__LINE__);\r
  79     }\r
  80 \r
  81     rank0_vir_base = ioremap(rank0_phy_base, rank0_len);\r
  82     if (rank0_vir_base == NULL)\r
  83     {\r
  84         printk("ioremap() of rank0 failed\n");\r
  85     }\r
  86 \r
  87     //*base_addr = rank0_vir_base;\r
  88 \r
  89     reg_phy_base = RK29_SMC_PHYS;\r
  90     len = SZ_16K;\r
  91     mem = request_mem_region(reg_phy_base, len, "smc reg");\r
  92     if (mem == NULL)\r
  93     {\r
  94         printk("failed to get memory region [%d]\n",__LINE__);\r
  95     }\r
  96 \r
  97     reg_vir_base = ioremap(reg_phy_base, len);\r
  98     if (reg_vir_base == NULL)\r
  99     {\r
 100         printk("ioremap() of registers failed\n");\r
 101     }\r
 102 \r
 103     smc0_enable(1);\r
 104 \r
 105     rk29_mux_api_set(GPIO0B7_EBCGDOE_SMCOEN_NAME, GPIO0L_SMC_OE_N);\r
 106     rk29_mux_api_set(GPIO0B6_EBCSDSHR_SMCBLSN1_HOSTINT_NAME, GPIO0L_SMC_BLS_N_1 );\r
 107     rk29_mux_api_set(GPIO0B5_EBCVCOM_SMCBLSN0_NAME, GPIO0L_SMC_BLS_N_0 );\r
 108     rk29_mux_api_set(GPIO0B4_EBCBORDER1_SMCWEN_NAME, GPIO0L_SMC_WE_N);\r
 109 \r
 110     rk29_mux_api_set(GPIO0B3_EBCBORDER0_SMCADDR3_HOSTDATA3_NAME, GPIO0L_SMC_ADDR3);\r
 111     rk29_mux_api_set(GPIO0B2_EBCSDCE2_SMCADDR2_HOSTDATA2_NAME, GPIO0L_SMC_ADDR2);\r
 112     rk29_mux_api_set(GPIO0B1_EBCSDCE1_SMCADDR1_HOSTDATA1_NAME, GPIO0L_SMC_ADDR1);\r
 113     rk29_mux_api_set(GPIO0B0_EBCSDCE0_SMCADDR0_HOSTDATA0_NAME, GPIO0L_SMC_ADDR0);\r
 114 \r
 115     rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_SMC_CSN0);\r
 116   //  rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_GPIO1A1);\r
 117 \r
 118   //  if(gpio_request(RK29_PIN1_PA1, NULL) != 0)\r
 119     {\r
 120   //      gpio_free(RK29_PIN1_PA1);\r
 121  //       printk(">>>>>> RK29_PIN1_PA1 gpio_request err \n ");\r
 122     }\r
 123   //  gpio_direction_output(RK29_PIN1_PA1, GPIO_LOW);\r
 124 \r
 125     rk29_mux_api_set(GPIO1A2_SMCCSN1_NAME, GPIO1L_SMC_CSN1);\r
 126     rk29_mux_api_set(GPIO0D0_EBCSDOE_SMCADVN_NAME, GPIO0H_SMC_ADV_N);\r
 127 \r
 128     rk29_mux_api_set(GPIO5C0_EBCSDDO0_SMCDATA0_NAME, GPIO5H_SMC_DATA0);\r
 129     rk29_mux_api_set(GPIO5C1_EBCSDDO1_SMCDATA1_NAME, GPIO5H_SMC_DATA1);\r
 130     rk29_mux_api_set(GPIO5C2_EBCSDDO2_SMCDATA2_NAME, GPIO5H_SMC_DATA2);\r
 131     rk29_mux_api_set(GPIO5C3_EBCSDDO3_SMCDATA3_NAME, GPIO5H_SMC_DATA3);\r
 132     rk29_mux_api_set(GPIO5C4_EBCSDDO4_SMCDATA4_NAME, GPIO5H_SMC_DATA4);\r
 133     rk29_mux_api_set(GPIO5C5_EBCSDDO5_SMCDATA5_NAME, GPIO5H_SMC_DATA5);\r
 134     rk29_mux_api_set(GPIO5C6_EBCSDDO6_SMCDATA6_NAME, GPIO5H_SMC_DATA6);\r
 135     rk29_mux_api_set(GPIO5C7_EBCSDDO7_SMCDATA7_NAME, GPIO5H_SMC_DATA7);\r
 136 \r
 137     rk29_mux_api_set(GPIO0C0_EBCGDSP_SMCDATA8_NAME, GPIO0H_SMC_DATA8);\r
 138     rk29_mux_api_set(GPIO0C1_EBCGDR1_SMCDATA9_NAME, GPIO0H_SMC_DATA9);\r
 139     rk29_mux_api_set(GPIO0C2_EBCSDCE0_SMCDATA10_NAME, GPIO0H_SMC_DATA10);\r
 140     rk29_mux_api_set(GPIO0C3_EBCSDCE1_SMCDATA11_NAME, GPIO0H_SMC_DATA11);\r
 141     rk29_mux_api_set(GPIO0C4_EBCSDCE2_SMCDATA12_NAME, GPIO0H_SMC_DATA12);\r
 142     rk29_mux_api_set(GPIO0C5_EBCSDCE3_SMCDATA13_NAME, GPIO0H_SMC_DATA13);\r
 143     rk29_mux_api_set(GPIO0C6_EBCSDCE4_SMCDATA14_NAME, GPIO0H_SMC_DATA14);\r
 144     rk29_mux_api_set(GPIO0C7_EBCSDCE5_SMCDATA15_NAME, GPIO0H_SMC_DATA15);\r
 145 \r
 146     return 0;\r
 147 \r
 148 }\r
 149 \r
 150 \r
 151 \r
 152 int smc0_write(u32 addr, u16 data)\r
 153 {\r
 154   //  __raw_writel(data, rank0_vir_base + addr);\r
 155     u16 *p = rank0_vir_base + addr;\r
 156         int readdata;\r
 157     *p = data;\r
 158         udelay(2);\r
 159         //readdata = *p;\r
 160         //mdelay(5);\r
 161         //mdelay(10);\r
 162     //printk("%s addr=%x, data = %x, read date = %x\n",__FUNCTION__,addr,data,readdata);\r
 163     return 0;\r
 164 }\r
 165 \r
 166 int smc0_read(u32 addr)\r
 167 {\r
 168     u16 * p = rank0_vir_base + addr;\r
 169         int readdata = *p; \r
 170         //mdelay(5);\r
 171         //printk("%s addr=%x, read date = %x\n",__FUNCTION__,addr,readdata);\r
 172     return readdata;//__raw_readl(rank0_vir_base + addr);\r
 173 }\r
 174 \r
 175 void  smc0_exit(void)\r
 176 {\r
 177      smc0_enable(0);\r
 178 }\r
 179 \r
 180 \r
 181 \r