2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
93 CRQB_FLAG_READ = (1 << 0),
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
99 CRPB_FLAG_STATUS_SHIFT = 8,
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
103 /* PCI interface registers */
105 PCI_COMMAND_OFS = 0xc00,
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
145 /* SATAHC registers */
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
153 /* Shadow block registers */
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
166 SATA_INTERFACE_CTL = 0x050,
168 MV_M2_PREAMP_MASK = 0x7e0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
222 EDMA_IORDY_TMOUT = 0x34,
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
233 /* Port private flags (pp_flags) */
234 MV_PP_FLAG_EDMA_EN = (1 << 0),
235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
238 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
245 MV_DMA_BOUNDARY = 0xffffU,
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
260 /* Command ReQuest Block: 32B */
268 /* Command ResPonse Block: 8B */
275 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
283 struct mv_port_priv {
284 struct mv_crqb *crqb;
286 struct mv_crpb *crpb;
288 struct mv_sg *sg_tbl;
289 dma_addr_t sg_tbl_dma;
291 unsigned req_producer; /* cp of req_in_ptr */
292 unsigned rsp_consumer; /* cp of rsp_out_ptr */
296 struct mv_port_signal {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
314 struct mv_host_priv {
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
320 static void mv_irq_clear(struct ata_port *ap);
321 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
325 static void mv_phy_reset(struct ata_port *ap);
326 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
327 static void mv_host_stop(struct ata_host_set *host_set);
328 static int mv_port_start(struct ata_port *ap);
329 static void mv_port_stop(struct ata_port *ap);
330 static void mv_qc_prep(struct ata_queued_cmd *qc);
331 static int mv_qc_issue(struct ata_queued_cmd *qc);
332 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334 static void mv_eng_timeout(struct ata_port *ap);
335 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
337 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
339 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
342 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
344 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
347 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
349 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
352 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
354 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358 static void mv_stop_and_reset(struct ata_port *ap);
360 static struct scsi_host_template mv_sht = {
361 .module = THIS_MODULE,
363 .ioctl = ata_scsi_ioctl,
364 .queuecommand = ata_scsi_queuecmd,
365 .eh_strategy_handler = ata_scsi_error,
366 .can_queue = MV_USE_Q_DEPTH,
367 .this_id = ATA_SHT_THIS_ID,
368 .sg_tablesize = MV_MAX_SG_CT / 2,
369 .max_sectors = ATA_MAX_SECTORS,
370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
371 .emulated = ATA_SHT_EMULATED,
372 .use_clustering = ATA_SHT_USE_CLUSTERING,
373 .proc_name = DRV_NAME,
374 .dma_boundary = MV_DMA_BOUNDARY,
375 .slave_configure = ata_scsi_slave_config,
376 .bios_param = ata_std_bios_param,
379 static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
388 .phy_reset = mv_phy_reset,
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
393 .eng_timeout = mv_eng_timeout,
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
406 static const struct ata_port_operations mv6_ops = {
407 .port_disable = ata_port_disable,
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
415 .phy_reset = mv_phy_reset,
417 .qc_prep = mv_qc_prep,
418 .qc_issue = mv_qc_issue,
420 .eng_timeout = mv_eng_timeout,
422 .irq_handler = mv_interrupt,
423 .irq_clear = mv_irq_clear,
425 .scr_read = mv_scr_read,
426 .scr_write = mv_scr_write,
428 .port_start = mv_port_start,
429 .port_stop = mv_port_stop,
430 .host_stop = mv_host_stop,
433 static const struct ata_port_info mv_port_info[] = {
436 .host_flags = MV_COMMON_FLAGS,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .udma_mask = 0x7f, /* udma0-6 */
439 .port_ops = &mv5_ops,
443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
444 .pio_mask = 0x1f, /* pio0-4 */
445 .udma_mask = 0x7f, /* udma0-6 */
446 .port_ops = &mv5_ops,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .udma_mask = 0x7f, /* udma0-6 */
460 .port_ops = &mv6_ops,
464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
466 .pio_mask = 0x1f, /* pio0-4 */
467 .udma_mask = 0x7f, /* udma0-6 */
468 .port_ops = &mv6_ops,
472 static const struct pci_device_id mv_pci_tbl[] = {
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
483 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
484 {} /* terminate list */
487 static struct pci_driver mv_pci_driver = {
489 .id_table = mv_pci_tbl,
490 .probe = mv_init_one,
491 .remove = ata_pci_remove_one,
494 static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
503 static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
515 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
522 static inline void writelfl(unsigned long data, void __iomem *addr)
525 (void) readl(addr); /* flush to avoid PCI posted write */
528 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
530 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
533 static inline unsigned int mv_hc_from_port(unsigned int port)
535 return port >> MV_PORT_HC_SHIFT;
538 static inline unsigned int mv_hardport_from_port(unsigned int port)
540 return port & MV_PORT_MASK;
543 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
546 return mv_hc_base(base, mv_hc_from_port(port));
549 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
551 return mv_hc_base_from_port(base, port) +
552 MV_SATAHC_ARBTR_REG_SZ +
553 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
556 static inline void __iomem *mv_ap_base(struct ata_port *ap)
558 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
561 static inline int mv_get_hc_count(unsigned long host_flags)
563 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
566 static void mv_irq_clear(struct ata_port *ap)
571 * mv_start_dma - Enable eDMA engine
572 * @base: port base address
573 * @pp: port private data
575 * Verify the local cache of the eDMA state is accurate with an
579 * Inherited from caller.
581 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
583 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
584 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
585 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
587 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
591 * mv_stop_dma - Disable eDMA engine
592 * @ap: ATA channel to manipulate
594 * Verify the local cache of the eDMA state is accurate with an
598 * Inherited from caller.
600 static void mv_stop_dma(struct ata_port *ap)
602 void __iomem *port_mmio = mv_ap_base(ap);
603 struct mv_port_priv *pp = ap->private_data;
607 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
608 /* Disable EDMA if active. The disable bit auto clears.
610 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
611 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
613 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
616 /* now properly wait for the eDMA to stop */
617 for (i = 1000; i > 0; i--) {
618 reg = readl(port_mmio + EDMA_CMD_OFS);
619 if (!(EDMA_EN & reg)) {
626 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
627 /* FIXME: Consider doing a reset here to recover */
632 static void mv_dump_mem(void __iomem *start, unsigned bytes)
635 for (b = 0; b < bytes; ) {
636 DPRINTK("%p: ", start + b);
637 for (w = 0; b < bytes && w < 4; w++) {
638 printk("%08x ",readl(start + b));
646 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
651 for (b = 0; b < bytes; ) {
652 DPRINTK("%02x: ", b);
653 for (w = 0; b < bytes && w < 4; w++) {
654 (void) pci_read_config_dword(pdev,b,&dw);
662 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
663 struct pci_dev *pdev)
666 void __iomem *hc_base = mv_hc_base(mmio_base,
667 port >> MV_PORT_HC_SHIFT);
668 void __iomem *port_base;
669 int start_port, num_ports, p, start_hc, num_hcs, hc;
672 start_hc = start_port = 0;
673 num_ports = 8; /* shld be benign for 4 port devs */
676 start_hc = port >> MV_PORT_HC_SHIFT;
678 num_ports = num_hcs = 1;
680 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
681 num_ports > 1 ? num_ports - 1 : start_port);
684 DPRINTK("PCI config space regs:\n");
685 mv_dump_pci_cfg(pdev, 0x68);
687 DPRINTK("PCI regs:\n");
688 mv_dump_mem(mmio_base+0xc00, 0x3c);
689 mv_dump_mem(mmio_base+0xd00, 0x34);
690 mv_dump_mem(mmio_base+0xf00, 0x4);
691 mv_dump_mem(mmio_base+0x1d00, 0x6c);
692 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
693 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
694 DPRINTK("HC regs (HC %i):\n", hc);
695 mv_dump_mem(hc_base, 0x1c);
697 for (p = start_port; p < start_port + num_ports; p++) {
698 port_base = mv_port_base(mmio_base, p);
699 DPRINTK("EDMA regs (port %i):\n",p);
700 mv_dump_mem(port_base, 0x54);
701 DPRINTK("SATA regs (port %i):\n",p);
702 mv_dump_mem(port_base+0x300, 0x60);
707 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
715 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
718 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
727 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
729 unsigned int ofs = mv_scr_offset(sc_reg_in);
731 if (0xffffffffU != ofs) {
732 return readl(mv_ap_base(ap) + ofs);
738 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
740 unsigned int ofs = mv_scr_offset(sc_reg_in);
742 if (0xffffffffU != ofs) {
743 writelfl(val, mv_ap_base(ap) + ofs);
748 * mv_host_stop - Host specific cleanup/stop routine.
749 * @host_set: host data structure
751 * Disable ints, cleanup host memory, call general purpose
755 * Inherited from caller.
757 static void mv_host_stop(struct ata_host_set *host_set)
759 struct mv_host_priv *hpriv = host_set->private_data;
760 struct pci_dev *pdev = to_pci_dev(host_set->dev);
762 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
763 pci_disable_msi(pdev);
768 ata_host_stop(host_set);
771 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
773 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
777 * mv_port_start - Port specific init/start routine.
778 * @ap: ATA channel to manipulate
780 * Allocate and point to DMA memory, init port private memory,
784 * Inherited from caller.
786 static int mv_port_start(struct ata_port *ap)
788 struct device *dev = ap->host_set->dev;
789 struct mv_port_priv *pp;
790 void __iomem *port_mmio = mv_ap_base(ap);
795 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
798 memset(pp, 0, sizeof(*pp));
800 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
804 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
806 rc = ata_pad_alloc(ap, dev);
810 /* First item in chunk of DMA memory:
811 * 32-slot command request table (CRQB), 32 bytes each in size
814 pp->crqb_dma = mem_dma;
816 mem_dma += MV_CRQB_Q_SZ;
819 * 32-slot command response table (CRPB), 8 bytes each in size
822 pp->crpb_dma = mem_dma;
824 mem_dma += MV_CRPB_Q_SZ;
827 * Table of scatter-gather descriptors (ePRD), 16 bytes each
830 pp->sg_tbl_dma = mem_dma;
832 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
833 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
835 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
836 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
837 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
839 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
840 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
843 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
846 pp->req_producer = pp->rsp_consumer = 0;
848 /* Don't turn on EDMA here...do it before DMA commands only. Else
849 * we'll be unable to send non-data, PIO, etc due to restricted access
852 ap->private_data = pp;
856 mv_priv_free(pp, dev);
864 * mv_port_stop - Port specific cleanup/stop routine.
865 * @ap: ATA channel to manipulate
867 * Stop DMA, cleanup port memory.
870 * This routine uses the host_set lock to protect the DMA stop.
872 static void mv_port_stop(struct ata_port *ap)
874 struct device *dev = ap->host_set->dev;
875 struct mv_port_priv *pp = ap->private_data;
878 spin_lock_irqsave(&ap->host_set->lock, flags);
880 spin_unlock_irqrestore(&ap->host_set->lock, flags);
882 ap->private_data = NULL;
883 ata_pad_free(ap, dev);
884 mv_priv_free(pp, dev);
889 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
890 * @qc: queued command whose SG list to source from
892 * Populate the SG list and mark the last entry.
895 * Inherited from caller.
897 static void mv_fill_sg(struct ata_queued_cmd *qc)
899 struct mv_port_priv *pp = qc->ap->private_data;
901 struct scatterlist *sg;
903 ata_for_each_sg(sg, qc) {
905 u32 sg_len, len, offset;
907 addr = sg_dma_address(sg);
908 sg_len = sg_dma_len(sg);
911 offset = addr & MV_DMA_BOUNDARY;
913 if ((offset + sg_len) > 0x10000)
914 len = 0x10000 - offset;
916 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
917 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
918 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
923 if (!sg_len && ata_sg_is_last(sg, qc))
924 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
931 static inline unsigned mv_inc_q_index(unsigned *index)
933 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
937 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
939 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
940 (last ? CRQB_CMD_LAST : 0);
944 * mv_qc_prep - Host specific command preparation.
945 * @qc: queued command to prepare
947 * This routine simply redirects to the general purpose routine
948 * if command is not DMA. Else, it handles prep of the CRQB
949 * (command request block), does some sanity checking, and calls
950 * the SG load routine.
953 * Inherited from caller.
955 static void mv_qc_prep(struct ata_queued_cmd *qc)
957 struct ata_port *ap = qc->ap;
958 struct mv_port_priv *pp = ap->private_data;
960 struct ata_taskfile *tf;
963 if (ATA_PROT_DMA != qc->tf.protocol) {
967 /* the req producer index should be the same as we remember it */
968 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
969 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
972 /* Fill in command request block
974 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
975 flags |= CRQB_FLAG_READ;
977 assert(MV_MAX_Q_DEPTH > qc->tag);
978 flags |= qc->tag << CRQB_TAG_SHIFT;
980 pp->crqb[pp->req_producer].sg_addr =
981 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
982 pp->crqb[pp->req_producer].sg_addr_hi =
983 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
984 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
986 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
989 /* Sadly, the CRQB cannot accomodate all registers--there are
990 * only 11 bytes...so we must pick and choose required
991 * registers based on the command. So, we drop feature and
992 * hob_feature for [RW] DMA commands, but they are needed for
993 * NCQ. NCQ will drop hob_nsect.
995 switch (tf->command) {
997 case ATA_CMD_READ_EXT:
999 case ATA_CMD_WRITE_EXT:
1000 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1002 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1003 case ATA_CMD_FPDMA_READ:
1004 case ATA_CMD_FPDMA_WRITE:
1005 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1006 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1008 #endif /* FIXME: remove this line when NCQ added */
1010 /* The only other commands EDMA supports in non-queued and
1011 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1012 * of which are defined/used by Linux. If we get here, this
1013 * driver needs work.
1015 * FIXME: modify libata to give qc_prep a return value and
1016 * return error here.
1018 BUG_ON(tf->command);
1021 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1022 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1023 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1024 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1025 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1026 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1027 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1028 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1029 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1031 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1038 * mv_qc_issue - Initiate a command to the host
1039 * @qc: queued command to start
1041 * This routine simply redirects to the general purpose routine
1042 * if command is not DMA. Else, it sanity checks our local
1043 * caches of the request producer/consumer indices then enables
1044 * DMA and bumps the request producer index.
1047 * Inherited from caller.
1049 static int mv_qc_issue(struct ata_queued_cmd *qc)
1051 void __iomem *port_mmio = mv_ap_base(qc->ap);
1052 struct mv_port_priv *pp = qc->ap->private_data;
1055 if (ATA_PROT_DMA != qc->tf.protocol) {
1056 /* We're about to send a non-EDMA capable command to the
1057 * port. Turn off EDMA so there won't be problems accessing
1058 * shadow block, etc registers.
1060 mv_stop_dma(qc->ap);
1061 return ata_qc_issue_prot(qc);
1064 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1066 /* the req producer index should be the same as we remember it */
1067 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1069 /* until we do queuing, the queue should be empty at this point */
1070 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1071 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1072 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1074 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1076 mv_start_dma(port_mmio, pp);
1078 /* and write the request in pointer to kick the EDMA to life */
1079 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1080 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1081 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1087 * mv_get_crpb_status - get status from most recently completed cmd
1088 * @ap: ATA channel to manipulate
1090 * This routine is for use when the port is in DMA mode, when it
1091 * will be using the CRPB (command response block) method of
1092 * returning command completion information. We assert indices
1093 * are good, grab status, and bump the response consumer index to
1094 * prove that we're up to date.
1097 * Inherited from caller.
1099 static u8 mv_get_crpb_status(struct ata_port *ap)
1101 void __iomem *port_mmio = mv_ap_base(ap);
1102 struct mv_port_priv *pp = ap->private_data;
1105 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1107 /* the response consumer index should be the same as we remember it */
1108 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1111 /* increment our consumer index... */
1112 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1114 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1115 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1116 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1119 /* write out our inc'd consumer index so EDMA knows we're caught up */
1120 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1121 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1122 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1124 /* Return ATA status register for completed CRPB */
1125 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1129 * mv_err_intr - Handle error interrupts on the port
1130 * @ap: ATA channel to manipulate
1132 * In most cases, just clear the interrupt and move on. However,
1133 * some cases require an eDMA reset, which is done right before
1134 * the COMRESET in mv_phy_reset(). The SERR case requires a
1135 * clear of pending errors in the SATA SERROR register. Finally,
1136 * if the port disabled DMA, update our cached copy to match.
1139 * Inherited from caller.
1141 static void mv_err_intr(struct ata_port *ap)
1143 void __iomem *port_mmio = mv_ap_base(ap);
1144 u32 edma_err_cause, serr = 0;
1146 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1148 if (EDMA_ERR_SERR & edma_err_cause) {
1149 serr = scr_read(ap, SCR_ERROR);
1150 scr_write_flush(ap, SCR_ERROR, serr);
1152 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1153 struct mv_port_priv *pp = ap->private_data;
1154 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1156 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1157 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1159 /* Clear EDMA now that SERR cleanup done */
1160 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1162 /* check for fatal here and recover if needed */
1163 if (EDMA_ERR_FATAL & edma_err_cause) {
1164 mv_stop_and_reset(ap);
1169 * mv_host_intr - Handle all interrupts on the given host controller
1170 * @host_set: host specific structure
1171 * @relevant: port error bits relevant to this host controller
1172 * @hc: which host controller we're to look at
1174 * Read then write clear the HC interrupt status then walk each
1175 * port connected to the HC and see if it needs servicing. Port
1176 * success ints are reported in the HC interrupt status reg, the
1177 * port error ints are reported in the higher level main
1178 * interrupt status register and thus are passed in via the
1179 * 'relevant' argument.
1182 * Inherited from caller.
1184 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1187 void __iomem *mmio = host_set->mmio_base;
1188 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1189 struct ata_port *ap;
1190 struct ata_queued_cmd *qc;
1192 int shift, port, port0, hard_port, handled;
1193 unsigned int err_mask;
1199 port0 = MV_PORTS_PER_HC;
1202 /* we'll need the HC success int register in most cases */
1203 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1205 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1208 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1209 hc,relevant,hc_irq_cause);
1211 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1212 ap = host_set->ports[port];
1213 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1214 handled = 0; /* ensure ata_status is set if handled++ */
1216 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1217 /* new CRPB on the queue; just one at a time until NCQ
1219 ata_status = mv_get_crpb_status(ap);
1221 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1222 /* received ATA IRQ; read the status reg to clear INTRQ
1224 ata_status = readb((void __iomem *)
1225 ap->ioaddr.status_addr);
1230 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1233 err_mask = ac_err_mask(ata_status);
1235 shift = port << 1; /* (port * 2) */
1236 if (port >= MV_PORTS_PER_HC) {
1237 shift++; /* skip bit 8 in the HC Main IRQ reg */
1239 if ((PORT0_ERR << shift) & relevant) {
1241 err_mask |= AC_ERR_OTHER;
1245 if (handled && ap) {
1246 qc = ata_qc_from_tag(ap, ap->active_tag);
1248 VPRINTK("port %u IRQ found for qc, "
1249 "ata_status 0x%x\n", port,ata_status);
1250 /* mark qc status appropriately */
1251 if (!(qc->tf.ctl & ATA_NIEN)) {
1252 qc->err_mask |= err_mask;
1253 ata_qc_complete(qc);
1264 * @dev_instance: private data; in this case the host structure
1267 * Read the read only register to determine if any host
1268 * controllers have pending interrupts. If so, call lower level
1269 * routine to handle. Also check for PCI errors which are only
1273 * This routine holds the host_set lock while processing pending
1276 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1277 struct pt_regs *regs)
1279 struct ata_host_set *host_set = dev_instance;
1280 unsigned int hc, handled = 0, n_hcs;
1281 void __iomem *mmio = host_set->mmio_base;
1284 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1286 /* check the cases where we either have nothing pending or have read
1287 * a bogus register value which can indicate HW removal or PCI fault
1289 if (!irq_stat || (0xffffffffU == irq_stat)) {
1293 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1294 spin_lock(&host_set->lock);
1296 for (hc = 0; hc < n_hcs; hc++) {
1297 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1299 mv_host_intr(host_set, relevant, hc);
1303 if (PCI_ERR & irq_stat) {
1304 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1305 readl(mmio + PCI_IRQ_CAUSE_OFS));
1307 DPRINTK("All regs @ PCI error\n");
1308 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1310 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1313 spin_unlock(&host_set->lock);
1315 return IRQ_RETVAL(handled);
1318 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1320 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1321 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1323 return hc_mmio + ofs;
1326 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1330 switch (sc_reg_in) {
1334 ofs = sc_reg_in * sizeof(u32);
1343 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1345 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1346 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1348 if (ofs != 0xffffffffU)
1349 return readl(mmio + ofs);
1354 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1356 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1357 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1359 if (ofs != 0xffffffffU)
1360 writelfl(val, mmio + ofs);
1363 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1368 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1370 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1373 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1375 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1378 mv_reset_pci_bus(pdev, mmio);
1381 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1383 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1386 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1389 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1392 tmp = readl(phy_mmio + MV5_PHY_MODE);
1394 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1395 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1398 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1402 writel(0, mmio + MV_GPIO_PORT_CTL);
1404 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1406 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1408 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1411 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1414 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1415 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1417 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1420 tmp = readl(phy_mmio + MV5_LT_MODE);
1422 writel(tmp, phy_mmio + MV5_LT_MODE);
1424 tmp = readl(phy_mmio + MV5_PHY_CTL);
1427 writel(tmp, phy_mmio + MV5_PHY_CTL);
1430 tmp = readl(phy_mmio + MV5_PHY_MODE);
1432 tmp |= hpriv->signal[port].pre;
1433 tmp |= hpriv->signal[port].amps;
1434 writel(tmp, phy_mmio + MV5_PHY_MODE);
1439 #define ZERO(reg) writel(0, port_mmio + (reg))
1440 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1443 void __iomem *port_mmio = mv_port_base(mmio, port);
1445 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1447 mv_channel_reset(hpriv, mmio, port);
1449 ZERO(0x028); /* command */
1450 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1451 ZERO(0x004); /* timer */
1452 ZERO(0x008); /* irq err cause */
1453 ZERO(0x00c); /* irq err mask */
1454 ZERO(0x010); /* rq bah */
1455 ZERO(0x014); /* rq inp */
1456 ZERO(0x018); /* rq outp */
1457 ZERO(0x01c); /* respq bah */
1458 ZERO(0x024); /* respq outp */
1459 ZERO(0x020); /* respq inp */
1460 ZERO(0x02c); /* test control */
1461 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1465 #define ZERO(reg) writel(0, hc_mmio + (reg))
1466 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1469 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1477 tmp = readl(hc_mmio + 0x20);
1480 writel(tmp, hc_mmio + 0x20);
1484 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1487 unsigned int hc, port;
1489 for (hc = 0; hc < n_hc; hc++) {
1490 for (port = 0; port < MV_PORTS_PER_HC; port++)
1491 mv5_reset_hc_port(hpriv, mmio,
1492 (hc * MV_PORTS_PER_HC) + port);
1494 mv5_reset_one_hc(hpriv, mmio, hc);
1501 #define ZERO(reg) writel(0, mmio + (reg))
1502 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1506 tmp = readl(mmio + MV_PCI_MODE);
1508 writel(tmp, mmio + MV_PCI_MODE);
1510 ZERO(MV_PCI_DISC_TIMER);
1511 ZERO(MV_PCI_MSI_TRIGGER);
1512 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1513 ZERO(HC_MAIN_IRQ_MASK_OFS);
1514 ZERO(MV_PCI_SERR_MASK);
1515 ZERO(PCI_IRQ_CAUSE_OFS);
1516 ZERO(PCI_IRQ_MASK_OFS);
1517 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1518 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1519 ZERO(MV_PCI_ERR_ATTRIBUTE);
1520 ZERO(MV_PCI_ERR_COMMAND);
1524 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1528 mv5_reset_flash(hpriv, mmio);
1530 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1532 tmp |= (1 << 5) | (1 << 6);
1533 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1537 * mv6_reset_hc - Perform the 6xxx global soft reset
1538 * @mmio: base address of the HBA
1540 * This routine only applies to 6xxx parts.
1543 * Inherited from caller.
1545 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1548 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1552 /* Following procedure defined in PCI "main command and status
1556 writel(t | STOP_PCI_MASTER, reg);
1558 for (i = 0; i < 1000; i++) {
1561 if (PCI_MASTER_EMPTY & t) {
1565 if (!(PCI_MASTER_EMPTY & t)) {
1566 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1574 writel(t | GLOB_SFT_RST, reg);
1577 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1579 if (!(GLOB_SFT_RST & t)) {
1580 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1585 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1588 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1591 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1593 if (GLOB_SFT_RST & t) {
1594 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1601 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1604 void __iomem *port_mmio;
1607 tmp = readl(mmio + MV_RESET_CFG);
1608 if ((tmp & (1 << 0)) == 0) {
1609 hpriv->signal[idx].amps = 0x7 << 8;
1610 hpriv->signal[idx].pre = 0x1 << 5;
1614 port_mmio = mv_port_base(mmio, idx);
1615 tmp = readl(port_mmio + PHY_MODE2);
1617 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1618 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1621 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1623 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1626 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1629 void __iomem *port_mmio = mv_port_base(mmio, port);
1631 u32 hp_flags = hpriv->hp_flags;
1633 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1635 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1638 if (fix_phy_mode2) {
1639 m2 = readl(port_mmio + PHY_MODE2);
1642 writel(m2, port_mmio + PHY_MODE2);
1646 m2 = readl(port_mmio + PHY_MODE2);
1647 m2 &= ~((1 << 16) | (1 << 31));
1648 writel(m2, port_mmio + PHY_MODE2);
1653 /* who knows what this magic does */
1654 tmp = readl(port_mmio + PHY_MODE3);
1657 writel(tmp, port_mmio + PHY_MODE3);
1659 if (fix_phy_mode4) {
1662 m4 = readl(port_mmio + PHY_MODE4);
1664 if (hp_flags & MV_HP_ERRATA_60X1B2)
1665 tmp = readl(port_mmio + 0x310);
1667 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1669 writel(m4, port_mmio + PHY_MODE4);
1671 if (hp_flags & MV_HP_ERRATA_60X1B2)
1672 writel(tmp, port_mmio + 0x310);
1675 /* Revert values of pre-emphasis and signal amps to the saved ones */
1676 m2 = readl(port_mmio + PHY_MODE2);
1678 m2 &= ~MV_M2_PREAMP_MASK;
1679 m2 |= hpriv->signal[port].amps;
1680 m2 |= hpriv->signal[port].pre;
1683 writel(m2, port_mmio + PHY_MODE2);
1686 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1687 unsigned int port_no)
1689 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1691 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1693 if (IS_60XX(hpriv)) {
1694 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1695 ifctl |= (1 << 12) | (1 << 7);
1696 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1699 udelay(25); /* allow reset propagation */
1701 /* Spec never mentions clearing the bit. Marvell's driver does
1702 * clear the bit, however.
1704 writelfl(0, port_mmio + EDMA_CMD_OFS);
1706 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1712 static void mv_stop_and_reset(struct ata_port *ap)
1714 struct mv_host_priv *hpriv = ap->host_set->private_data;
1715 void __iomem *mmio = ap->host_set->mmio_base;
1719 mv_channel_reset(hpriv, mmio, ap->port_no);
1721 __mv_phy_reset(ap, 0);
1724 static inline void __msleep(unsigned int msec, int can_sleep)
1733 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1734 * @ap: ATA channel to manipulate
1736 * Part of this is taken from __sata_phy_reset and modified to
1737 * not sleep since this routine gets called from interrupt level.
1740 * Inherited from caller. This is coded to safe to call at
1741 * interrupt level, i.e. it does not sleep.
1743 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1745 struct mv_port_priv *pp = ap->private_data;
1746 struct mv_host_priv *hpriv = ap->host_set->private_data;
1747 void __iomem *port_mmio = mv_ap_base(ap);
1748 struct ata_taskfile tf;
1749 struct ata_device *dev = &ap->device[0];
1750 unsigned long timeout;
1754 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1756 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1757 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1758 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1760 /* Issue COMRESET via SControl */
1762 scr_write_flush(ap, SCR_CONTROL, 0x301);
1763 __msleep(1, can_sleep);
1765 scr_write_flush(ap, SCR_CONTROL, 0x300);
1766 __msleep(20, can_sleep);
1768 timeout = jiffies + msecs_to_jiffies(200);
1770 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1771 if ((sstatus == 3) || (sstatus == 0))
1774 __msleep(1, can_sleep);
1775 } while (time_before(jiffies, timeout));
1777 /* work around errata */
1778 if (IS_60XX(hpriv) &&
1779 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1781 goto comreset_retry;
1783 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1784 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1785 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1787 if (sata_dev_present(ap)) {
1790 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1791 ap->id, scr_read(ap, SCR_STATUS));
1792 ata_port_disable(ap);
1795 ap->cbl = ATA_CBL_SATA;
1797 /* even after SStatus reflects that device is ready,
1798 * it seems to take a while for link to be fully
1799 * established (and thus Status no longer 0x80/0x7F),
1800 * so we poll a bit for that, here.
1804 u8 drv_stat = ata_check_status(ap);
1805 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1807 __msleep(500, can_sleep);
1812 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1813 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1814 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1815 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1817 dev->class = ata_dev_classify(&tf);
1818 if (!ata_dev_present(dev)) {
1819 VPRINTK("Port disabled post-sig: No device present.\n");
1820 ata_port_disable(ap);
1823 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1825 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1830 static void mv_phy_reset(struct ata_port *ap)
1832 __mv_phy_reset(ap, 1);
1836 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1837 * @ap: ATA channel to manipulate
1839 * Intent is to clear all pending error conditions, reset the
1840 * chip/bus, fail the command, and move on.
1843 * This routine holds the host_set lock while failing the command.
1845 static void mv_eng_timeout(struct ata_port *ap)
1847 struct ata_queued_cmd *qc;
1848 unsigned long flags;
1850 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1851 DPRINTK("All regs @ start of eng_timeout\n");
1852 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1853 to_pci_dev(ap->host_set->dev));
1855 qc = ata_qc_from_tag(ap, ap->active_tag);
1856 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1857 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1858 &qc->scsicmd->cmnd);
1861 mv_stop_and_reset(ap);
1864 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1867 /* hack alert! We cannot use the supplied completion
1868 * function from inside the ->eh_strategy_handler() thread.
1869 * libata is the only user of ->eh_strategy_handler() in
1870 * any kernel, so the default scsi_done() assumes it is
1871 * not being called from the SCSI EH.
1873 spin_lock_irqsave(&ap->host_set->lock, flags);
1874 qc->scsidone = scsi_finish_command;
1875 qc->err_mask |= AC_ERR_OTHER;
1876 ata_qc_complete(qc);
1877 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1882 * mv_port_init - Perform some early initialization on a single port.
1883 * @port: libata data structure storing shadow register addresses
1884 * @port_mmio: base address of the port
1886 * Initialize shadow register mmio addresses, clear outstanding
1887 * interrupts on the port, and unmask interrupts for the future
1888 * start of the port.
1891 * Inherited from caller.
1893 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1895 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1898 /* PIO related setup
1900 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1902 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1903 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1904 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1905 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1906 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1907 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1909 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1910 /* special case: control/altstatus doesn't have ATA_REG_ address */
1911 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1914 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1916 /* Clear any currently outstanding port interrupt conditions */
1917 serr_ofs = mv_scr_offset(SCR_ERROR);
1918 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1919 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1921 /* unmask all EDMA error interrupts */
1922 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1924 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1925 readl(port_mmio + EDMA_CFG_OFS),
1926 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1927 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1930 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1931 unsigned int board_idx)
1934 u32 hp_flags = hpriv->hp_flags;
1936 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1940 hpriv->ops = &mv5xxx_ops;
1941 hp_flags |= MV_HP_50XX;
1945 hp_flags |= MV_HP_ERRATA_50XXB0;
1948 hp_flags |= MV_HP_ERRATA_50XXB2;
1951 dev_printk(KERN_WARNING, &pdev->dev,
1952 "Applying 50XXB2 workarounds to unknown rev\n");
1953 hp_flags |= MV_HP_ERRATA_50XXB2;
1960 hpriv->ops = &mv5xxx_ops;
1961 hp_flags |= MV_HP_50XX;
1965 hp_flags |= MV_HP_ERRATA_50XXB0;
1968 hp_flags |= MV_HP_ERRATA_50XXB2;
1971 dev_printk(KERN_WARNING, &pdev->dev,
1972 "Applying B2 workarounds to unknown rev\n");
1973 hp_flags |= MV_HP_ERRATA_50XXB2;
1980 hpriv->ops = &mv6xxx_ops;
1984 hp_flags |= MV_HP_ERRATA_60X1B2;
1987 hp_flags |= MV_HP_ERRATA_60X1C0;
1990 dev_printk(KERN_WARNING, &pdev->dev,
1991 "Applying B2 workarounds to unknown rev\n");
1992 hp_flags |= MV_HP_ERRATA_60X1B2;
1998 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2002 hpriv->hp_flags = hp_flags;
2008 * mv_init_host - Perform some early initialization of the host.
2009 * @pdev: host PCI device
2010 * @probe_ent: early data struct representing the host
2012 * If possible, do an early global reset of the host. Then do
2013 * our port init and clear/unmask all/relevant host interrupts.
2016 * Inherited from caller.
2018 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2019 unsigned int board_idx)
2021 int rc = 0, n_hc, port, hc;
2022 void __iomem *mmio = probe_ent->mmio_base;
2023 struct mv_host_priv *hpriv = probe_ent->private_data;
2025 /* global interrupt mask */
2026 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2028 rc = mv_chip_id(pdev, hpriv, board_idx);
2032 n_hc = mv_get_hc_count(probe_ent->host_flags);
2033 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2035 for (port = 0; port < probe_ent->n_ports; port++)
2036 hpriv->ops->read_preamp(hpriv, port, mmio);
2038 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2042 hpriv->ops->reset_flash(hpriv, mmio);
2043 hpriv->ops->reset_bus(pdev, mmio);
2044 hpriv->ops->enable_leds(hpriv, mmio);
2046 for (port = 0; port < probe_ent->n_ports; port++) {
2047 if (IS_60XX(hpriv)) {
2048 void __iomem *port_mmio = mv_port_base(mmio, port);
2050 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2052 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2055 hpriv->ops->phy_errata(hpriv, mmio, port);
2058 for (port = 0; port < probe_ent->n_ports; port++) {
2059 void __iomem *port_mmio = mv_port_base(mmio, port);
2060 mv_port_init(&probe_ent->port[port], port_mmio);
2063 for (hc = 0; hc < n_hc; hc++) {
2064 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2066 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2067 "(before clear)=0x%08x\n", hc,
2068 readl(hc_mmio + HC_CFG_OFS),
2069 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2071 /* Clear any currently outstanding hc interrupt conditions */
2072 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2075 /* Clear any currently outstanding host interrupt conditions */
2076 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2078 /* and unmask interrupt generation for host regs */
2079 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2080 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2082 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2083 "PCI int cause/mask=0x%08x/0x%08x\n",
2084 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2085 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2086 readl(mmio + PCI_IRQ_CAUSE_OFS),
2087 readl(mmio + PCI_IRQ_MASK_OFS));
2094 * mv_print_info - Dump key info to kernel log for perusal.
2095 * @probe_ent: early data struct representing the host
2097 * FIXME: complete this.
2100 * Inherited from caller.
2102 static void mv_print_info(struct ata_probe_ent *probe_ent)
2104 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2105 struct mv_host_priv *hpriv = probe_ent->private_data;
2109 /* Use this to determine the HW stepping of the chip so we know
2110 * what errata to workaround
2112 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2114 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2117 else if (scc == 0x01)
2122 dev_printk(KERN_INFO, &pdev->dev,
2123 "%u slots %u ports %s mode IRQ via %s\n",
2124 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2125 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2129 * mv_init_one - handle a positive probe of a Marvell host
2130 * @pdev: PCI device found
2131 * @ent: PCI device ID entry for the matched host
2134 * Inherited from caller.
2136 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2138 static int printed_version = 0;
2139 struct ata_probe_ent *probe_ent = NULL;
2140 struct mv_host_priv *hpriv;
2141 unsigned int board_idx = (unsigned int)ent->driver_data;
2142 void __iomem *mmio_base;
2143 int pci_dev_busy = 0, rc;
2145 if (!printed_version++)
2146 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2148 rc = pci_enable_device(pdev);
2153 rc = pci_request_regions(pdev, DRV_NAME);
2159 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2160 if (probe_ent == NULL) {
2162 goto err_out_regions;
2165 memset(probe_ent, 0, sizeof(*probe_ent));
2166 probe_ent->dev = pci_dev_to_dev(pdev);
2167 INIT_LIST_HEAD(&probe_ent->node);
2169 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2170 if (mmio_base == NULL) {
2172 goto err_out_free_ent;
2175 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2178 goto err_out_iounmap;
2180 memset(hpriv, 0, sizeof(*hpriv));
2182 probe_ent->sht = mv_port_info[board_idx].sht;
2183 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2184 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2185 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2186 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2188 probe_ent->irq = pdev->irq;
2189 probe_ent->irq_flags = SA_SHIRQ;
2190 probe_ent->mmio_base = mmio_base;
2191 probe_ent->private_data = hpriv;
2193 /* initialize adapter */
2194 rc = mv_init_host(pdev, probe_ent, board_idx);
2199 /* Enable interrupts */
2200 if (msi && pci_enable_msi(pdev) == 0) {
2201 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2206 mv_dump_pci_cfg(pdev, 0x68);
2207 mv_print_info(probe_ent);
2209 if (ata_device_add(probe_ent) == 0) {
2210 rc = -ENODEV; /* No devices discovered */
2211 goto err_out_dev_add;
2218 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2219 pci_disable_msi(pdev);
2226 pci_iounmap(pdev, mmio_base);
2230 pci_release_regions(pdev);
2232 if (!pci_dev_busy) {
2233 pci_disable_device(pdev);
2239 static int __init mv_init(void)
2241 return pci_module_init(&mv_pci_driver);
2244 static void __exit mv_exit(void)
2246 pci_unregister_driver(&mv_pci_driver);
2249 MODULE_AUTHOR("Brett Russ");
2250 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2251 MODULE_LICENSE("GPL");
2252 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2253 MODULE_VERSION(DRV_VERSION);
2255 module_param(msi, int, 0444);
2256 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2258 module_init(mv_init);
2259 module_exit(mv_exit);