drivers/scsi/qla2xxx/qla_nx.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2012 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include <linux/vmalloc.h>
  12 #include <scsi/scsi_tcq.h>
  13
  14 #define MASK(n)                 ((1ULL<<(n))-1)
  15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  16         ((addr >> 25) & 0x3ff))
  17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  18         ((addr >> 25) & 0x3ff))
  19 #define MS_WIN(addr) (addr & 0x0ffc0000)
  20 #define QLA82XX_PCI_MN_2M   (0)
  21 #define QLA82XX_PCI_MS_2M   (0x80000)
  22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
  23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  25 #define BLOCK_PROTECT_BITS 0x0F
  26
  27 /* CRB window related */
  28 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30 #define CRB_WINDOW_2M   (0x130060)
  31 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  32 #define CRB_HI(off)     ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  33                         ((off) & 0xf0000))
  34 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35 #define CRB_INDIRECT_2M (0x1e0000UL)
  36
  37 #define MAX_CRB_XFORM 60
  38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  39 static int qla82xx_crb_table_initialized;
  40
  41 #define qla82xx_crb_addr_transform(name) \
  42         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  43         QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  44
  45 static void qla82xx_crb_addr_transform_setup(void)
  46 {
  47         qla82xx_crb_addr_transform(XDMA);
  48         qla82xx_crb_addr_transform(TIMR);
  49         qla82xx_crb_addr_transform(SRE);
  50         qla82xx_crb_addr_transform(SQN3);
  51         qla82xx_crb_addr_transform(SQN2);
  52         qla82xx_crb_addr_transform(SQN1);
  53         qla82xx_crb_addr_transform(SQN0);
  54         qla82xx_crb_addr_transform(SQS3);
  55         qla82xx_crb_addr_transform(SQS2);
  56         qla82xx_crb_addr_transform(SQS1);
  57         qla82xx_crb_addr_transform(SQS0);
  58         qla82xx_crb_addr_transform(RPMX7);
  59         qla82xx_crb_addr_transform(RPMX6);
  60         qla82xx_crb_addr_transform(RPMX5);
  61         qla82xx_crb_addr_transform(RPMX4);
  62         qla82xx_crb_addr_transform(RPMX3);
  63         qla82xx_crb_addr_transform(RPMX2);
  64         qla82xx_crb_addr_transform(RPMX1);
  65         qla82xx_crb_addr_transform(RPMX0);
  66         qla82xx_crb_addr_transform(ROMUSB);
  67         qla82xx_crb_addr_transform(SN);
  68         qla82xx_crb_addr_transform(QMN);
  69         qla82xx_crb_addr_transform(QMS);
  70         qla82xx_crb_addr_transform(PGNI);
  71         qla82xx_crb_addr_transform(PGND);
  72         qla82xx_crb_addr_transform(PGN3);
  73         qla82xx_crb_addr_transform(PGN2);
  74         qla82xx_crb_addr_transform(PGN1);
  75         qla82xx_crb_addr_transform(PGN0);
  76         qla82xx_crb_addr_transform(PGSI);
  77         qla82xx_crb_addr_transform(PGSD);
  78         qla82xx_crb_addr_transform(PGS3);
  79         qla82xx_crb_addr_transform(PGS2);
  80         qla82xx_crb_addr_transform(PGS1);
  81         qla82xx_crb_addr_transform(PGS0);
  82         qla82xx_crb_addr_transform(PS);
  83         qla82xx_crb_addr_transform(PH);
  84         qla82xx_crb_addr_transform(NIU);
  85         qla82xx_crb_addr_transform(I2Q);
  86         qla82xx_crb_addr_transform(EG);
  87         qla82xx_crb_addr_transform(MN);
  88         qla82xx_crb_addr_transform(MS);
  89         qla82xx_crb_addr_transform(CAS2);
  90         qla82xx_crb_addr_transform(CAS1);
  91         qla82xx_crb_addr_transform(CAS0);
  92         qla82xx_crb_addr_transform(CAM);
  93         qla82xx_crb_addr_transform(C2C1);
  94         qla82xx_crb_addr_transform(C2C0);
  95         qla82xx_crb_addr_transform(SMB);
  96         qla82xx_crb_addr_transform(OCM0);
  97         /*
  98          * Used only in P3 just define it for P2 also.
  99          */
 100         qla82xx_crb_addr_transform(I2C0);
 101
 102         qla82xx_crb_table_initialized = 1;
 103 }
 104
 105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 106         {{{0, 0,         0,         0} } },
 107         {{{1, 0x0100000, 0x0102000, 0x120000},
 108         {1, 0x0110000, 0x0120000, 0x130000},
 109         {1, 0x0120000, 0x0122000, 0x124000},
 110         {1, 0x0130000, 0x0132000, 0x126000},
 111         {1, 0x0140000, 0x0142000, 0x128000},
 112         {1, 0x0150000, 0x0152000, 0x12a000},
 113         {1, 0x0160000, 0x0170000, 0x110000},
 114         {1, 0x0170000, 0x0172000, 0x12e000},
 115         {0, 0x0000000, 0x0000000, 0x000000},
 116         {0, 0x0000000, 0x0000000, 0x000000},
 117         {0, 0x0000000, 0x0000000, 0x000000},
 118         {0, 0x0000000, 0x0000000, 0x000000},
 119         {0, 0x0000000, 0x0000000, 0x000000},
 120         {0, 0x0000000, 0x0000000, 0x000000},
 121         {1, 0x01e0000, 0x01e0800, 0x122000},
 122         {0, 0x0000000, 0x0000000, 0x000000} } } ,
 123         {{{1, 0x0200000, 0x0210000, 0x180000} } },
 124         {{{0, 0,         0,         0} } },
 125         {{{1, 0x0400000, 0x0401000, 0x169000} } },
 126         {{{1, 0x0500000, 0x0510000, 0x140000} } },
 127         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 128         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 129         {{{1, 0x0800000, 0x0802000, 0x170000},
 130         {0, 0x0000000, 0x0000000, 0x000000},
 131         {0, 0x0000000, 0x0000000, 0x000000},
 132         {0, 0x0000000, 0x0000000, 0x000000},
 133         {0, 0x0000000, 0x0000000, 0x000000},
 134         {0, 0x0000000, 0x0000000, 0x000000},
 135         {0, 0x0000000, 0x0000000, 0x000000},
 136         {0, 0x0000000, 0x0000000, 0x000000},
 137         {0, 0x0000000, 0x0000000, 0x000000},
 138         {0, 0x0000000, 0x0000000, 0x000000},
 139         {0, 0x0000000, 0x0000000, 0x000000},
 140         {0, 0x0000000, 0x0000000, 0x000000},
 141         {0, 0x0000000, 0x0000000, 0x000000},
 142         {0, 0x0000000, 0x0000000, 0x000000},
 143         {0, 0x0000000, 0x0000000, 0x000000},
 144         {1, 0x08f0000, 0x08f2000, 0x172000} } },
 145         {{{1, 0x0900000, 0x0902000, 0x174000},
 146         {0, 0x0000000, 0x0000000, 0x000000},
 147         {0, 0x0000000, 0x0000000, 0x000000},
 148         {0, 0x0000000, 0x0000000, 0x000000},
 149         {0, 0x0000000, 0x0000000, 0x000000},
 150         {0, 0x0000000, 0x0000000, 0x000000},
 151         {0, 0x0000000, 0x0000000, 0x000000},
 152         {0, 0x0000000, 0x0000000, 0x000000},
 153         {0, 0x0000000, 0x0000000, 0x000000},
 154         {0, 0x0000000, 0x0000000, 0x000000},
 155         {0, 0x0000000, 0x0000000, 0x000000},
 156         {0, 0x0000000, 0x0000000, 0x000000},
 157         {0, 0x0000000, 0x0000000, 0x000000},
 158         {0, 0x0000000, 0x0000000, 0x000000},
 159         {0, 0x0000000, 0x0000000, 0x000000},
 160         {1, 0x09f0000, 0x09f2000, 0x176000} } },
 161         {{{0, 0x0a00000, 0x0a02000, 0x178000},
 162         {0, 0x0000000, 0x0000000, 0x000000},
 163         {0, 0x0000000, 0x0000000, 0x000000},
 164         {0, 0x0000000, 0x0000000, 0x000000},
 165         {0, 0x0000000, 0x0000000, 0x000000},
 166         {0, 0x0000000, 0x0000000, 0x000000},
 167         {0, 0x0000000, 0x0000000, 0x000000},
 168         {0, 0x0000000, 0x0000000, 0x000000},
 169         {0, 0x0000000, 0x0000000, 0x000000},
 170         {0, 0x0000000, 0x0000000, 0x000000},
 171         {0, 0x0000000, 0x0000000, 0x000000},
 172         {0, 0x0000000, 0x0000000, 0x000000},
 173         {0, 0x0000000, 0x0000000, 0x000000},
 174         {0, 0x0000000, 0x0000000, 0x000000},
 175         {0, 0x0000000, 0x0000000, 0x000000},
 176         {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 177         {{{0, 0x0b00000, 0x0b02000, 0x17c000},
 178         {0, 0x0000000, 0x0000000, 0x000000},
 179         {0, 0x0000000, 0x0000000, 0x000000},
 180         {0, 0x0000000, 0x0000000, 0x000000},
 181         {0, 0x0000000, 0x0000000, 0x000000},
 182         {0, 0x0000000, 0x0000000, 0x000000},
 183         {0, 0x0000000, 0x0000000, 0x000000},
 184         {0, 0x0000000, 0x0000000, 0x000000},
 185         {0, 0x0000000, 0x0000000, 0x000000},
 186         {0, 0x0000000, 0x0000000, 0x000000},
 187         {0, 0x0000000, 0x0000000, 0x000000},
 188         {0, 0x0000000, 0x0000000, 0x000000},
 189         {0, 0x0000000, 0x0000000, 0x000000},
 190         {0, 0x0000000, 0x0000000, 0x000000},
 191         {0, 0x0000000, 0x0000000, 0x000000},
 192         {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 193         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 194         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 195         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 196         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 197         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 198         {{{1, 0x1100000, 0x1101000, 0x160000} } },
 199         {{{1, 0x1200000, 0x1201000, 0x161000} } },
 200         {{{1, 0x1300000, 0x1301000, 0x162000} } },
 201         {{{1, 0x1400000, 0x1401000, 0x163000} } },
 202         {{{1, 0x1500000, 0x1501000, 0x165000} } },
 203         {{{1, 0x1600000, 0x1601000, 0x166000} } },
 204         {{{0, 0,         0,         0} } },
 205         {{{0, 0,         0,         0} } },
 206         {{{0, 0,         0,         0} } },
 207         {{{0, 0,         0,         0} } },
 208         {{{0, 0,         0,         0} } },
 209         {{{0, 0,         0,         0} } },
 210         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 211         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 212         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 213         {{{0} } },
 214         {{{1, 0x2100000, 0x2102000, 0x120000},
 215         {1, 0x2110000, 0x2120000, 0x130000},
 216         {1, 0x2120000, 0x2122000, 0x124000},
 217         {1, 0x2130000, 0x2132000, 0x126000},
 218         {1, 0x2140000, 0x2142000, 0x128000},
 219         {1, 0x2150000, 0x2152000, 0x12a000},
 220         {1, 0x2160000, 0x2170000, 0x110000},
 221         {1, 0x2170000, 0x2172000, 0x12e000},
 222         {0, 0x0000000, 0x0000000, 0x000000},
 223         {0, 0x0000000, 0x0000000, 0x000000},
 224         {0, 0x0000000, 0x0000000, 0x000000},
 225         {0, 0x0000000, 0x0000000, 0x000000},
 226         {0, 0x0000000, 0x0000000, 0x000000},
 227         {0, 0x0000000, 0x0000000, 0x000000},
 228         {0, 0x0000000, 0x0000000, 0x000000},
 229         {0, 0x0000000, 0x0000000, 0x000000} } },
 230         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 231         {{{0} } },
 232         {{{0} } },
 233         {{{0} } },
 234         {{{0} } },
 235         {{{0} } },
 236         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 237         {{{1, 0x2900000, 0x2901000, 0x16b000} } },
 238         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 239         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 240         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 241         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 242         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 243         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 244         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 245         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 246         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 247         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 248         {{{0} } },
 249         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 250         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 251         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 252         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 253         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 254         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 255         {{{0} } },
 256         {{{0} } },
 257         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 258         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 259         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 260 };
 261
 262 /*
 263  * top 12 bits of crb internal address (hub, agent)
 264  */
 265 static unsigned qla82xx_crb_hub_agt[64] = {
 266         0,
 267         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 268         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 269         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 270         0,
 271         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 272         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 293         0,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 296         0,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 298         0,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 301         0,
 302         0,
 303         0,
 304         0,
 305         0,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 307         0,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 309         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 310         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 311         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 318         0,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 323         0,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 327         0,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 329         0,
 330 };
 331
 332 /* Device states */
 333 static char *q_dev_state[] = {
 334          "Unknown",
 335         "Cold",
 336         "Initializing",
 337         "Ready",
 338         "Need Reset",
 339         "Need Quiescent",
 340         "Failed",
 341         "Quiescent",
 342 };
 343
 344 char *qdev_state(uint32_t dev_state)
 345 {
 346         return q_dev_state[dev_state];
 347 }
 348
 349 /*
 350  * In: 'off' is offset from CRB space in 128M pci map
 351  * Out: 'off' is 2M pci map addr
 352  * side effect: lock crb window
 353  */
 354 static void
 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
 356 {
 357         u32 win_read;
 358         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 359
 360         ha->crb_win = CRB_HI(*off);
 361         writel(ha->crb_win,
 362                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 363
 364         /* Read back value to make sure write has gone through before trying
 365          * to use it.
 366          */
 367         win_read = RD_REG_DWORD((void __iomem *)
 368             (CRB_WINDOW_2M + ha->nx_pcibase));
 369         if (win_read != ha->crb_win) {
 370                 ql_dbg(ql_dbg_p3p, vha, 0xb000,
 371                     "%s: Written crbwin (0x%x) "
 372                     "!= Read crbwin (0x%x), off=0x%lx.\n",
 373                     __func__, ha->crb_win, win_read, *off);
 374         }
 375         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 376 }
 377
 378 static inline unsigned long
 379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
 380 {
 381         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 382         /* See if we are currently pointing to the region we want to use next */
 383         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
 384                 /* No need to change window. PCIX and PCIEregs are in both
 385                  * regs are in both windows.
 386                  */
 387                 return off;
 388         }
 389
 390         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
 391                 /* We are in first CRB window */
 392                 if (ha->curr_window != 0)
 393                         WARN_ON(1);
 394                 return off;
 395         }
 396
 397         if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
 398                 /* We are in second CRB window */
 399                 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
 400
 401                 if (ha->curr_window != 1)
 402                         return off;
 403
 404                 /* We are in the QM or direct access
 405                  * register region - do nothing
 406                  */
 407                 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
 408                         (off < QLA82XX_PCI_CAMQM_MAX))
 409                         return off;
 410         }
 411         /* strange address given */
 412         ql_dbg(ql_dbg_p3p, vha, 0xb001,
 413             "%s: Warning: unm_nic_pci_set_crbwindow "
 414             "called with an unknown address(%llx).\n",
 415             QLA2XXX_DRIVER_NAME, off);
 416         return off;
 417 }
 418
 419 static int
 420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
 421 {
 422         struct crb_128M_2M_sub_block_map *m;
 423
 424         if (*off >= QLA82XX_CRB_MAX)
 425                 return -1;
 426
 427         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 428                 *off = (*off - QLA82XX_PCI_CAMQM) +
 429                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 430                 return 0;
 431         }
 432
 433         if (*off < QLA82XX_PCI_CRBSPACE)
 434                 return -1;
 435
 436         *off -= QLA82XX_PCI_CRBSPACE;
 437
 438         /* Try direct map */
 439         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 440
 441         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 442                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 443                 return 0;
 444         }
 445         /* Not in direct map, use crb window */
 446         return 1;
 447 }
 448
 449 #define CRB_WIN_LOCK_TIMEOUT 100000000
 450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 451 {
 452         int done = 0, timeout = 0;
 453
 454         while (!done) {
 455                 /* acquire semaphore3 from PCI HW block */
 456                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 457                 if (done == 1)
 458                         break;
 459                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 460                         return -1;
 461                 timeout++;
 462         }
 463         qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 464         return 0;
 465 }
 466
 467 int
 468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
 469 {
 470         unsigned long flags = 0;
 471         int rv;
 472
 473         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 474
 475         BUG_ON(rv == -1);
 476
 477         if (rv == 1) {
 478                 write_lock_irqsave(&ha->hw_lock, flags);
 479                 qla82xx_crb_win_lock(ha);
 480                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 481         }
 482
 483         writel(data, (void __iomem *)off);
 484
 485         if (rv == 1) {
 486                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 487                 write_unlock_irqrestore(&ha->hw_lock, flags);
 488         }
 489         return 0;
 490 }
 491
 492 int
 493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
 494 {
 495         unsigned long flags = 0;
 496         int rv;
 497         u32 data;
 498
 499         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 500
 501         BUG_ON(rv == -1);
 502
 503         if (rv == 1) {
 504                 write_lock_irqsave(&ha->hw_lock, flags);
 505                 qla82xx_crb_win_lock(ha);
 506                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 507         }
 508         data = RD_REG_DWORD((void __iomem *)off);
 509
 510         if (rv == 1) {
 511                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 512                 write_unlock_irqrestore(&ha->hw_lock, flags);
 513         }
 514         return data;
 515 }
 516
 517 #define IDC_LOCK_TIMEOUT 100000000
 518 int qla82xx_idc_lock(struct qla_hw_data *ha)
 519 {
 520         int i;
 521         int done = 0, timeout = 0;
 522
 523         while (!done) {
 524                 /* acquire semaphore5 from PCI HW block */
 525                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 526                 if (done == 1)
 527                         break;
 528                 if (timeout >= IDC_LOCK_TIMEOUT)
 529                         return -1;
 530
 531                 timeout++;
 532
 533                 /* Yield CPU */
 534                 if (!in_interrupt())
 535                         schedule();
 536                 else {
 537                         for (i = 0; i < 20; i++)
 538                                 cpu_relax();
 539                 }
 540         }
 541
 542         return 0;
 543 }
 544
 545 void qla82xx_idc_unlock(struct qla_hw_data *ha)
 546 {
 547         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 548 }
 549
 550 /*  PCI Windowing for DDR regions.  */
 551 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
 552         (((addr) <= (high)) && ((addr) >= (low)))
 553 /*
 554  * check memory access boundary.
 555  * used by test agent. support ddr access only for now
 556  */
 557 static unsigned long
 558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 559         unsigned long long addr, int size)
 560 {
 561         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 562                 QLA82XX_ADDR_DDR_NET_MAX) ||
 563                 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 564                 QLA82XX_ADDR_DDR_NET_MAX) ||
 565                 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 566                         return 0;
 567         else
 568                 return 1;
 569 }
 570
 571 static int qla82xx_pci_set_window_warning_count;
 572
 573 static unsigned long
 574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 575 {
 576         int window;
 577         u32 win_read;
 578         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 579
 580         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 581                 QLA82XX_ADDR_DDR_NET_MAX)) {
 582                 /* DDR network side */
 583                 window = MN_WIN(addr);
 584                 ha->ddr_mn_window = window;
 585                 qla82xx_wr_32(ha,
 586                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 587                 win_read = qla82xx_rd_32(ha,
 588                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 589                 if ((win_read << 17) != window) {
 590                         ql_dbg(ql_dbg_p3p, vha, 0xb003,
 591                             "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
 592                             __func__, window, win_read);
 593                 }
 594                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 595         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 596                 QLA82XX_ADDR_OCM0_MAX)) {
 597                 unsigned int temp1;
 598                 if ((addr & 0x00ff800) == 0xff800) {
 599                         ql_log(ql_log_warn, vha, 0xb004,
 600                             "%s: QM access not handled.\n", __func__);
 601                         addr = -1UL;
 602                 }
 603                 window = OCM_WIN(addr);
 604                 ha->ddr_mn_window = window;
 605                 qla82xx_wr_32(ha,
 606                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 607                 win_read = qla82xx_rd_32(ha,
 608                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 609                 temp1 = ((window & 0x1FF) << 7) |
 610                     ((window & 0x0FFFE0000) >> 17);
 611                 if (win_read != temp1) {
 612                         ql_log(ql_log_warn, vha, 0xb005,
 613                             "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
 614                             __func__, temp1, win_read);
 615                 }
 616                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 617
 618         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 619                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 620                 /* QDR network side */
 621                 window = MS_WIN(addr);
 622                 ha->qdr_sn_window = window;
 623                 qla82xx_wr_32(ha,
 624                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 625                 win_read = qla82xx_rd_32(ha,
 626                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 627                 if (win_read != window) {
 628                         ql_log(ql_log_warn, vha, 0xb006,
 629                             "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
 630                             __func__, window, win_read);
 631                 }
 632                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 633         } else {
 634                 /*
 635                  * peg gdb frequently accesses memory that doesn't exist,
 636                  * this limits the chit chat so debugging isn't slowed down.
 637                  */
 638                 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 639                     (qla82xx_pci_set_window_warning_count%64 == 0)) {
 640                         ql_log(ql_log_warn, vha, 0xb007,
 641                             "%s: Warning:%s Unknown address range!.\n",
 642                             __func__, QLA2XXX_DRIVER_NAME);
 643                 }
 644                 addr = -1UL;
 645         }
 646         return addr;
 647 }
 648
 649 /* check if address is in the same windows as the previous access */
 650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 651         unsigned long long addr)
 652 {
 653         int                     window;
 654         unsigned long long      qdr_max;
 655
 656         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 657
 658         /* DDR network side */
 659         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 660                 QLA82XX_ADDR_DDR_NET_MAX))
 661                 BUG();
 662         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 663                 QLA82XX_ADDR_OCM0_MAX))
 664                 return 1;
 665         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 666                 QLA82XX_ADDR_OCM1_MAX))
 667                 return 1;
 668         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 669                 /* QDR network side */
 670                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 671                 if (ha->qdr_sn_window == window)
 672                         return 1;
 673         }
 674         return 0;
 675 }
 676
 677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 678         u64 off, void *data, int size)
 679 {
 680         unsigned long   flags;
 681         void __iomem *addr = NULL;
 682         int             ret = 0;
 683         u64             start;
 684         uint8_t __iomem  *mem_ptr = NULL;
 685         unsigned long   mem_base;
 686         unsigned long   mem_page;
 687         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 688
 689         write_lock_irqsave(&ha->hw_lock, flags);
 690
 691         /*
 692          * If attempting to access unknown address or straddle hw windows,
 693          * do not access.
 694          */
 695         start = qla82xx_pci_set_window(ha, off);
 696         if ((start == -1UL) ||
 697                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 698                 write_unlock_irqrestore(&ha->hw_lock, flags);
 699                 ql_log(ql_log_fatal, vha, 0xb008,
 700                     "%s out of bound pci memory "
 701                     "access, offset is 0x%llx.\n",
 702                     QLA2XXX_DRIVER_NAME, off);
 703                 return -1;
 704         }
 705
 706         write_unlock_irqrestore(&ha->hw_lock, flags);
 707         mem_base = pci_resource_start(ha->pdev, 0);
 708         mem_page = start & PAGE_MASK;
 709         /* Map two pages whenever user tries to access addresses in two
 710         * consecutive pages.
 711         */
 712         if (mem_page != ((start + size - 1) & PAGE_MASK))
 713                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 714         else
 715                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 716         if (mem_ptr == NULL) {
 717                 *(u8  *)data = 0;
 718                 return -1;
 719         }
 720         addr = mem_ptr;
 721         addr += start & (PAGE_SIZE - 1);
 722         write_lock_irqsave(&ha->hw_lock, flags);
 723
 724         switch (size) {
 725         case 1:
 726                 *(u8  *)data = readb(addr);
 727                 break;
 728         case 2:
 729                 *(u16 *)data = readw(addr);
 730                 break;
 731         case 4:
 732                 *(u32 *)data = readl(addr);
 733                 break;
 734         case 8:
 735                 *(u64 *)data = readq(addr);
 736                 break;
 737         default:
 738                 ret = -1;
 739                 break;
 740         }
 741         write_unlock_irqrestore(&ha->hw_lock, flags);
 742
 743         if (mem_ptr)
 744                 iounmap(mem_ptr);
 745         return ret;
 746 }
 747
 748 static int
 749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 750         u64 off, void *data, int size)
 751 {
 752         unsigned long   flags;
 753         void  __iomem *addr = NULL;
 754         int             ret = 0;
 755         u64             start;
 756         uint8_t __iomem *mem_ptr = NULL;
 757         unsigned long   mem_base;
 758         unsigned long   mem_page;
 759         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 760
 761         write_lock_irqsave(&ha->hw_lock, flags);
 762
 763         /*
 764          * If attempting to access unknown address or straddle hw windows,
 765          * do not access.
 766          */
 767         start = qla82xx_pci_set_window(ha, off);
 768         if ((start == -1UL) ||
 769                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 770                 write_unlock_irqrestore(&ha->hw_lock, flags);
 771                 ql_log(ql_log_fatal, vha, 0xb009,
 772                     "%s out of bount memory "
 773                     "access, offset is 0x%llx.\n",
 774                     QLA2XXX_DRIVER_NAME, off);
 775                 return -1;
 776         }
 777
 778         write_unlock_irqrestore(&ha->hw_lock, flags);
 779         mem_base = pci_resource_start(ha->pdev, 0);
 780         mem_page = start & PAGE_MASK;
 781         /* Map two pages whenever user tries to access addresses in two
 782          * consecutive pages.
 783          */
 784         if (mem_page != ((start + size - 1) & PAGE_MASK))
 785                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 786         else
 787                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 788         if (mem_ptr == NULL)
 789                 return -1;
 790
 791         addr = mem_ptr;
 792         addr += start & (PAGE_SIZE - 1);
 793         write_lock_irqsave(&ha->hw_lock, flags);
 794
 795         switch (size) {
 796         case 1:
 797                 writeb(*(u8  *)data, addr);
 798                 break;
 799         case 2:
 800                 writew(*(u16 *)data, addr);
 801                 break;
 802         case 4:
 803                 writel(*(u32 *)data, addr);
 804                 break;
 805         case 8:
 806                 writeq(*(u64 *)data, addr);
 807                 break;
 808         default:
 809                 ret = -1;
 810                 break;
 811         }
 812         write_unlock_irqrestore(&ha->hw_lock, flags);
 813         if (mem_ptr)
 814                 iounmap(mem_ptr);
 815         return ret;
 816 }
 817
 818 #define MTU_FUDGE_FACTOR 100
 819 static unsigned long
 820 qla82xx_decode_crb_addr(unsigned long addr)
 821 {
 822         int i;
 823         unsigned long base_addr, offset, pci_base;
 824
 825         if (!qla82xx_crb_table_initialized)
 826                 qla82xx_crb_addr_transform_setup();
 827
 828         pci_base = ADDR_ERROR;
 829         base_addr = addr & 0xfff00000;
 830         offset = addr & 0x000fffff;
 831
 832         for (i = 0; i < MAX_CRB_XFORM; i++) {
 833                 if (crb_addr_xform[i] == base_addr) {
 834                         pci_base = i << 20;
 835                         break;
 836                 }
 837         }
 838         if (pci_base == ADDR_ERROR)
 839                 return pci_base;
 840         return pci_base + offset;
 841 }
 842
 843 static long rom_max_timeout = 100;
 844 static long qla82xx_rom_lock_timeout = 100;
 845
 846 static int
 847 qla82xx_rom_lock(struct qla_hw_data *ha)
 848 {
 849         int done = 0, timeout = 0;
 850
 851         while (!done) {
 852                 /* acquire semaphore2 from PCI HW block */
 853                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 854                 if (done == 1)
 855                         break;
 856                 if (timeout >= qla82xx_rom_lock_timeout)
 857                         return -1;
 858                 timeout++;
 859         }
 860         qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 861         return 0;
 862 }
 863
 864 static void
 865 qla82xx_rom_unlock(struct qla_hw_data *ha)
 866 {
 867         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 868 }
 869
 870 static int
 871 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
 872 {
 873         long timeout = 0;
 874         long done = 0 ;
 875         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 876
 877         while (done == 0) {
 878                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 879                 done &= 4;
 880                 timeout++;
 881                 if (timeout >= rom_max_timeout) {
 882                         ql_dbg(ql_dbg_p3p, vha, 0xb00a,
 883                             "%s: Timeout reached waiting for rom busy.\n",
 884                             QLA2XXX_DRIVER_NAME);
 885                         return -1;
 886                 }
 887         }
 888         return 0;
 889 }
 890
 891 static int
 892 qla82xx_wait_rom_done(struct qla_hw_data *ha)
 893 {
 894         long timeout = 0;
 895         long done = 0 ;
 896         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 897
 898         while (done == 0) {
 899                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 900                 done &= 2;
 901                 timeout++;
 902                 if (timeout >= rom_max_timeout) {
 903                         ql_dbg(ql_dbg_p3p, vha, 0xb00b,
 904                             "%s: Timeout reached waiting for rom done.\n",
 905                             QLA2XXX_DRIVER_NAME);
 906                         return -1;
 907                 }
 908         }
 909         return 0;
 910 }
 911
 912 static int
 913 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
 914 {
 915         uint32_t  off_value, rval = 0;
 916
 917         WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
 918             (off & 0xFFFF0000));
 919
 920         /* Read back value to make sure write has gone through */
 921         RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 922         off_value  = (off & 0x0000FFFF);
 923
 924         if (flag)
 925                 WRT_REG_DWORD((void __iomem *)
 926                     (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
 927                     data);
 928         else
 929                 rval = RD_REG_DWORD((void __iomem *)
 930                     (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
 931
 932         return rval;
 933 }
 934
 935 static int
 936 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 937 {
 938         /* Dword reads to flash. */
 939         qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
 940         *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
 941             (addr & 0x0000FFFF), 0, 0);
 942
 943         return 0;
 944 }
 945
 946 static int
 947 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 948 {
 949         int ret, loops = 0;
 950         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 951
 952         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 953                 udelay(100);
 954                 schedule();
 955                 loops++;
 956         }
 957         if (loops >= 50000) {
 958                 ql_log(ql_log_fatal, vha, 0x00b9,
 959                     "Failed to acquire SEM2 lock.\n");
 960                 return -1;
 961         }
 962         ret = qla82xx_do_rom_fast_read(ha, addr, valp);
 963         qla82xx_rom_unlock(ha);
 964         return ret;
 965 }
 966
 967 static int
 968 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
 969 {
 970         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 971         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
 972         qla82xx_wait_rom_busy(ha);
 973         if (qla82xx_wait_rom_done(ha)) {
 974                 ql_log(ql_log_warn, vha, 0xb00c,
 975                     "Error waiting for rom done.\n");
 976                 return -1;
 977         }
 978         *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 979         return 0;
 980 }
 981
 982 static int
 983 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
 984 {
 985         long timeout = 0;
 986         uint32_t done = 1 ;
 987         uint32_t val;
 988         int ret = 0;
 989         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 990
 991         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 992         while ((done != 0) && (ret == 0)) {
 993                 ret = qla82xx_read_status_reg(ha, &val);
 994                 done = val & 1;
 995                 timeout++;
 996                 udelay(10);
 997                 cond_resched();
 998                 if (timeout >= 50000) {
 999                         ql_log(ql_log_warn, vha, 0xb00d,
1000                             "Timeout reached waiting for write finish.\n");
1001                         return -1;
1002                 }
1003         }
1004         return ret;
1005 }
1006
1007 static int
1008 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1009 {
1010         uint32_t val;
1011         qla82xx_wait_rom_busy(ha);
1012         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1013         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1014         qla82xx_wait_rom_busy(ha);
1015         if (qla82xx_wait_rom_done(ha))
1016                 return -1;
1017         if (qla82xx_read_status_reg(ha, &val) != 0)
1018                 return -1;
1019         if ((val & 2) != 2)
1020                 return -1;
1021         return 0;
1022 }
1023
1024 static int
1025 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1026 {
1027         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1028         if (qla82xx_flash_set_write_enable(ha))
1029                 return -1;
1030         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1031         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1032         if (qla82xx_wait_rom_done(ha)) {
1033                 ql_log(ql_log_warn, vha, 0xb00e,
1034                     "Error waiting for rom done.\n");
1035                 return -1;
1036         }
1037         return qla82xx_flash_wait_write_finish(ha);
1038 }
1039
1040 static int
1041 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1042 {
1043         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1044         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1045         if (qla82xx_wait_rom_done(ha)) {
1046                 ql_log(ql_log_warn, vha, 0xb00f,
1047                     "Error waiting for rom done.\n");
1048                 return -1;
1049         }
1050         return 0;
1051 }
1052
1053 static int
1054 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1055 {
1056         int loops = 0;
1057         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1058
1059         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1060                 udelay(100);
1061                 cond_resched();
1062                 loops++;
1063         }
1064         if (loops >= 50000) {
1065                 ql_log(ql_log_warn, vha, 0xb010,
1066                     "ROM lock failed.\n");
1067                 return -1;
1068         }
1069         return 0;
1070 }
1071
1072 static int
1073 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1074         uint32_t data)
1075 {
1076         int ret = 0;
1077         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1078
1079         ret = ql82xx_rom_lock_d(ha);
1080         if (ret < 0) {
1081                 ql_log(ql_log_warn, vha, 0xb011,
1082                     "ROM lock failed.\n");
1083                 return ret;
1084         }
1085
1086         if (qla82xx_flash_set_write_enable(ha))
1087                 goto done_write;
1088
1089         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1090         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1091         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1092         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1093         qla82xx_wait_rom_busy(ha);
1094         if (qla82xx_wait_rom_done(ha)) {
1095                 ql_log(ql_log_warn, vha, 0xb012,
1096                     "Error waiting for rom done.\n");
1097                 ret = -1;
1098                 goto done_write;
1099         }
1100
1101         ret = qla82xx_flash_wait_write_finish(ha);
1102
1103 done_write:
1104         qla82xx_rom_unlock(ha);
1105         return ret;
1106 }
1107
1108 /* This routine does CRB initialize sequence
1109  *  to put the ISP into operational state
1110  */
1111 static int
1112 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1113 {
1114         int addr, val;
1115         int i ;
1116         struct crb_addr_pair *buf;
1117         unsigned long off;
1118         unsigned offset, n;
1119         struct qla_hw_data *ha = vha->hw;
1120
1121         struct crb_addr_pair {
1122                 long addr;
1123                 long data;
1124         };
1125
1126         /* Halt all the individual PEGs and other blocks of the ISP */
1127         qla82xx_rom_lock(ha);
1128
1129         /* disable all I2Q */
1130         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1131         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1132         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1133         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1134         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1135         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1136
1137         /* disable all niu interrupts */
1138         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1139         /* disable xge rx/tx */
1140         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1141         /* disable xg1 rx/tx */
1142         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1143         /* disable sideband mac */
1144         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1145         /* disable ap0 mac */
1146         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1147         /* disable ap1 mac */
1148         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1149
1150         /* halt sre */
1151         val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1152         qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1153
1154         /* halt epg */
1155         qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1156
1157         /* halt timers */
1158         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1159         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1160         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1161         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1162         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1163         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1164
1165         /* halt pegs */
1166         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1167         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1168         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1169         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1170         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1171         msleep(20);
1172
1173         /* big hammer */
1174         if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1175                 /* don't reset CAM block on reset */
1176                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1177         else
1178                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1179         qla82xx_rom_unlock(ha);
1180
1181         /* Read the signature value from the flash.
1182          * Offset 0: Contain signature (0xcafecafe)
1183          * Offset 4: Offset and number of addr/value pairs
1184          * that present in CRB initialize sequence
1185          */
1186         if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1187             qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1188                 ql_log(ql_log_fatal, vha, 0x006e,
1189                     "Error Reading crb_init area: n: %08x.\n", n);
1190                 return -1;
1191         }
1192
1193         /* Offset in flash = lower 16 bits
1194          * Number of entries = upper 16 bits
1195          */
1196         offset = n & 0xffffU;
1197         n = (n >> 16) & 0xffffU;
1198
1199         /* number of addr/value pair should not exceed 1024 entries */
1200         if (n  >= 1024) {
1201                 ql_log(ql_log_fatal, vha, 0x0071,
1202                     "Card flash not initialized:n=0x%x.\n", n);
1203                 return -1;
1204         }
1205
1206         ql_log(ql_log_info, vha, 0x0072,
1207             "%d CRB init values found in ROM.\n", n);
1208
1209         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1210         if (buf == NULL) {
1211                 ql_log(ql_log_fatal, vha, 0x010c,
1212                     "Unable to allocate memory.\n");
1213                 return -1;
1214         }
1215
1216         for (i = 0; i < n; i++) {
1217                 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1218                     qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1219                         kfree(buf);
1220                         return -1;
1221                 }
1222
1223                 buf[i].addr = addr;
1224                 buf[i].data = val;
1225         }
1226
1227         for (i = 0; i < n; i++) {
1228                 /* Translate internal CRB initialization
1229                  * address to PCI bus address
1230                  */
1231                 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1232                     QLA82XX_PCI_CRBSPACE;
1233                 /* Not all CRB  addr/value pair to be written,
1234                  * some of them are skipped
1235                  */
1236
1237                 /* skipping cold reboot MAGIC */
1238                 if (off == QLA82XX_CAM_RAM(0x1fc))
1239                         continue;
1240
1241                 /* do not reset PCI */
1242                 if (off == (ROMUSB_GLB + 0xbc))
1243                         continue;
1244
1245                 /* skip core clock, so that firmware can increase the clock */
1246                 if (off == (ROMUSB_GLB + 0xc8))
1247                         continue;
1248
1249                 /* skip the function enable register */
1250                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1251                         continue;
1252
1253                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1254                         continue;
1255
1256                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1257                         continue;
1258
1259                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1260                         continue;
1261
1262                 if (off == ADDR_ERROR) {
1263                         ql_log(ql_log_fatal, vha, 0x0116,
1264                             "Unknow addr: 0x%08lx.\n", buf[i].addr);
1265                         continue;
1266                 }
1267
1268                 qla82xx_wr_32(ha, off, buf[i].data);
1269
1270                 /* ISP requires much bigger delay to settle down,
1271                  * else crb_window returns 0xffffffff
1272                  */
1273                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1274                         msleep(1000);
1275
1276                 /* ISP requires millisec delay between
1277                  * successive CRB register updation
1278                  */
1279                 msleep(1);
1280         }
1281
1282         kfree(buf);
1283
1284         /* Resetting the data and instruction cache */
1285         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1286         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1287         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1288
1289         /* Clear all protocol processing engines */
1290         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1291         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1292         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1293         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1294         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1295         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1296         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1297         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1298         return 0;
1299 }
1300
1301 static int
1302 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1303                 u64 off, void *data, int size)
1304 {
1305         int i, j, ret = 0, loop, sz[2], off0;
1306         int scale, shift_amount, startword;
1307         uint32_t temp;
1308         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1309
1310         /*
1311          * If not MN, go check for MS or invalid.
1312          */
1313         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1314                 mem_crb = QLA82XX_CRB_QDR_NET;
1315         else {
1316                 mem_crb = QLA82XX_CRB_DDR_NET;
1317                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1318                         return qla82xx_pci_mem_write_direct(ha,
1319                             off, data, size);
1320         }
1321
1322         off0 = off & 0x7;
1323         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1324         sz[1] = size - sz[0];
1325
1326         off8 = off & 0xfffffff0;
1327         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1328         shift_amount = 4;
1329         scale = 2;
1330         startword = (off & 0xf)/8;
1331
1332         for (i = 0; i < loop; i++) {
1333                 if (qla82xx_pci_mem_read_2M(ha, off8 +
1334                     (i << shift_amount), &word[i * scale], 8))
1335                         return -1;
1336         }
1337
1338         switch (size) {
1339         case 1:
1340                 tmpw = *((uint8_t *)data);
1341                 break;
1342         case 2:
1343                 tmpw = *((uint16_t *)data);
1344                 break;
1345         case 4:
1346                 tmpw = *((uint32_t *)data);
1347                 break;
1348         case 8:
1349         default:
1350                 tmpw = *((uint64_t *)data);
1351                 break;
1352         }
1353
1354         if (sz[0] == 8) {
1355                 word[startword] = tmpw;
1356         } else {
1357                 word[startword] &=
1358                         ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1359                 word[startword] |= tmpw << (off0 * 8);
1360         }
1361         if (sz[1] != 0) {
1362                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1363                 word[startword+1] |= tmpw >> (sz[0] * 8);
1364         }
1365
1366         for (i = 0; i < loop; i++) {
1367                 temp = off8 + (i << shift_amount);
1368                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1369                 temp = 0;
1370                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1371                 temp = word[i * scale] & 0xffffffff;
1372                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1373                 temp = (word[i * scale] >> 32) & 0xffffffff;
1374                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1375                 temp = word[i*scale + 1] & 0xffffffff;
1376                 qla82xx_wr_32(ha, mem_crb +
1377                     MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1378                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1379                 qla82xx_wr_32(ha, mem_crb +
1380                     MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1381
1382                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1383                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1384                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1385                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1386
1387                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1388                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1389                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1390                                 break;
1391                 }
1392
1393                 if (j >= MAX_CTL_CHECK) {
1394                         if (printk_ratelimit())
1395                                 dev_err(&ha->pdev->dev,
1396                                     "failed to write through agent.\n");
1397                         ret = -1;
1398                         break;
1399                 }
1400         }
1401
1402         return ret;
1403 }
1404
1405 static int
1406 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1407 {
1408         int  i;
1409         long size = 0;
1410         long flashaddr = ha->flt_region_bootload << 2;
1411         long memaddr = BOOTLD_START;
1412         u64 data;
1413         u32 high, low;
1414         size = (IMAGE_START - BOOTLD_START) / 8;
1415
1416         for (i = 0; i < size; i++) {
1417                 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1418                     (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1419                         return -1;
1420                 }
1421                 data = ((u64)high << 32) | low ;
1422                 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1423                 flashaddr += 8;
1424                 memaddr += 8;
1425
1426                 if (i % 0x1000 == 0)
1427                         msleep(1);
1428         }
1429         udelay(100);
1430         read_lock(&ha->hw_lock);
1431         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1432         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1433         read_unlock(&ha->hw_lock);
1434         return 0;
1435 }
1436
1437 int
1438 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1439                 u64 off, void *data, int size)
1440 {
1441         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1442         int           shift_amount;
1443         uint32_t      temp;
1444         uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1445
1446         /*
1447          * If not MN, go check for MS or invalid.
1448          */
1449
1450         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1451                 mem_crb = QLA82XX_CRB_QDR_NET;
1452         else {
1453                 mem_crb = QLA82XX_CRB_DDR_NET;
1454                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1455                         return qla82xx_pci_mem_read_direct(ha,
1456                             off, data, size);
1457         }
1458
1459         off8 = off & 0xfffffff0;
1460         off0[0] = off & 0xf;
1461         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1462         shift_amount = 4;
1463         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1464         off0[1] = 0;
1465         sz[1] = size - sz[0];
1466
1467         for (i = 0; i < loop; i++) {
1468                 temp = off8 + (i << shift_amount);
1469                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1470                 temp = 0;
1471                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1472                 temp = MIU_TA_CTL_ENABLE;
1473                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1474                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1475                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1476
1477                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1478                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1479                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1480                                 break;
1481                 }
1482
1483                 if (j >= MAX_CTL_CHECK) {
1484                         if (printk_ratelimit())
1485                                 dev_err(&ha->pdev->dev,
1486                                     "failed to read through agent.\n");
1487                         break;
1488                 }
1489
1490                 start = off0[i] >> 2;
1491                 end   = (off0[i] + sz[i] - 1) >> 2;
1492                 for (k = start; k <= end; k++) {
1493                         temp = qla82xx_rd_32(ha,
1494                                         mem_crb + MIU_TEST_AGT_RDDATA(k));
1495                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1496                 }
1497         }
1498
1499         if (j >= MAX_CTL_CHECK)
1500                 return -1;
1501
1502         if ((off0[0] & 7) == 0) {
1503                 val = word[0];
1504         } else {
1505                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1506                         ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1507         }
1508
1509         switch (size) {
1510         case 1:
1511                 *(uint8_t  *)data = val;
1512                 break;
1513         case 2:
1514                 *(uint16_t *)data = val;
1515                 break;
1516         case 4:
1517                 *(uint32_t *)data = val;
1518                 break;
1519         case 8:
1520                 *(uint64_t *)data = val;
1521                 break;
1522         }
1523         return 0;
1524 }
1525
1526
1527 static struct qla82xx_uri_table_desc *
1528 qla82xx_get_table_desc(const u8 *unirom, int section)
1529 {
1530         uint32_t i;
1531         struct qla82xx_uri_table_desc *directory =
1532                 (struct qla82xx_uri_table_desc *)&unirom[0];
1533         __le32 offset;
1534         __le32 tab_type;
1535         __le32 entries = cpu_to_le32(directory->num_entries);
1536
1537         for (i = 0; i < entries; i++) {
1538                 offset = cpu_to_le32(directory->findex) +
1539                     (i * cpu_to_le32(directory->entry_size));
1540                 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1541
1542                 if (tab_type == section)
1543                         return (struct qla82xx_uri_table_desc *)&unirom[offset];
1544         }
1545
1546         return NULL;
1547 }
1548
1549 static struct qla82xx_uri_data_desc *
1550 qla82xx_get_data_desc(struct qla_hw_data *ha,
1551         u32 section, u32 idx_offset)
1552 {
1553         const u8 *unirom = ha->hablob->fw->data;
1554         int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1555         struct qla82xx_uri_table_desc *tab_desc = NULL;
1556         __le32 offset;
1557
1558         tab_desc = qla82xx_get_table_desc(unirom, section);
1559         if (!tab_desc)
1560                 return NULL;
1561
1562         offset = cpu_to_le32(tab_desc->findex) +
1563             (cpu_to_le32(tab_desc->entry_size) * idx);
1564
1565         return (struct qla82xx_uri_data_desc *)&unirom[offset];
1566 }
1567
1568 static u8 *
1569 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1570 {
1571         u32 offset = BOOTLD_START;
1572         struct qla82xx_uri_data_desc *uri_desc = NULL;
1573
1574         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1575                 uri_desc = qla82xx_get_data_desc(ha,
1576                     QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1577                 if (uri_desc)
1578                         offset = cpu_to_le32(uri_desc->findex);
1579         }
1580
1581         return (u8 *)&ha->hablob->fw->data[offset];
1582 }
1583
1584 static __le32
1585 qla82xx_get_fw_size(struct qla_hw_data *ha)
1586 {
1587         struct qla82xx_uri_data_desc *uri_desc = NULL;
1588
1589         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1590                 uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1591                     QLA82XX_URI_FIRMWARE_IDX_OFF);
1592                 if (uri_desc)
1593                         return cpu_to_le32(uri_desc->size);
1594         }
1595
1596         return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1597 }
1598
1599 static u8 *
1600 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1601 {
1602         u32 offset = IMAGE_START;
1603         struct qla82xx_uri_data_desc *uri_desc = NULL;
1604
1605         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1606                 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1607                         QLA82XX_URI_FIRMWARE_IDX_OFF);
1608                 if (uri_desc)
1609                         offset = cpu_to_le32(uri_desc->findex);
1610         }
1611
1612         return (u8 *)&ha->hablob->fw->data[offset];
1613 }
1614
1615 /* PCI related functions */
1616 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1617 {
1618         unsigned long val = 0;
1619         u32 control;
1620
1621         switch (region) {
1622         case 0:
1623                 val = 0;
1624                 break;
1625         case 1:
1626                 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1627                 val = control + QLA82XX_MSIX_TBL_SPACE;
1628                 break;
1629         }
1630         return val;
1631 }
1632
1633
1634 int
1635 qla82xx_iospace_config(struct qla_hw_data *ha)
1636 {
1637         uint32_t len = 0;
1638
1639         if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1640                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1641                     "Failed to reserver selected regions.\n");
1642                 goto iospace_error_exit;
1643         }
1644
1645         /* Use MMIO operations for all accesses. */
1646         if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1647                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1648                     "Region #0 not an MMIO resource, aborting.\n");
1649                 goto iospace_error_exit;
1650         }
1651
1652         len = pci_resource_len(ha->pdev, 0);
1653         ha->nx_pcibase =
1654             (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1655         if (!ha->nx_pcibase) {
1656                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1657                     "Cannot remap pcibase MMIO, aborting.\n");
1658                 goto iospace_error_exit;
1659         }
1660
1661         /* Mapping of IO base pointer */
1662         ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1663             0xbc000 + (ha->pdev->devfn << 11));
1664
1665         if (!ql2xdbwr) {
1666                 ha->nxdb_wr_ptr =
1667                     (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1668                     (ha->pdev->devfn << 12)), 4);
1669                 if (!ha->nxdb_wr_ptr) {
1670                         ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1671                             "Cannot remap MMIO, aborting.\n");
1672                         goto iospace_error_exit;
1673                 }
1674
1675                 /* Mapping of IO base pointer,
1676                  * door bell read and write pointer
1677                  */
1678                 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1679                     (ha->pdev->devfn * 8);
1680         } else {
1681                 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1682                         QLA82XX_CAMRAM_DB1 :
1683                         QLA82XX_CAMRAM_DB2);
1684         }
1685
1686         ha->max_req_queues = ha->max_rsp_queues = 1;
1687         ha->msix_count = ha->max_rsp_queues + 1;
1688         ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1689             "nx_pci_base=%p iobase=%p "
1690             "max_req_queues=%d msix_count=%d.\n",
1691             (void *)ha->nx_pcibase, ha->iobase,
1692             ha->max_req_queues, ha->msix_count);
1693         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1694             "nx_pci_base=%p iobase=%p "
1695             "max_req_queues=%d msix_count=%d.\n",
1696             (void *)ha->nx_pcibase, ha->iobase,
1697             ha->max_req_queues, ha->msix_count);
1698         return 0;
1699
1700 iospace_error_exit:
1701         return -ENOMEM;
1702 }
1703
1704 /* GS related functions */
1705
1706 /* Initialization related functions */
1707
1708 /**
1709  * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1710  * @ha: HA context
1711  *
1712  * Returns 0 on success.
1713 */
1714 int
1715 qla82xx_pci_config(scsi_qla_host_t *vha)
1716 {
1717         struct qla_hw_data *ha = vha->hw;
1718         int ret;
1719
1720         pci_set_master(ha->pdev);
1721         ret = pci_set_mwi(ha->pdev);
1722         ha->chip_revision = ha->pdev->revision;
1723         ql_dbg(ql_dbg_init, vha, 0x0043,
1724             "Chip revision:%d.\n",
1725             ha->chip_revision);
1726         return 0;
1727 }
1728
1729 /**
1730  * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1731  * @ha: HA context
1732  *
1733  * Returns 0 on success.
1734  */
1735 void
1736 qla82xx_reset_chip(scsi_qla_host_t *vha)
1737 {
1738         struct qla_hw_data *ha = vha->hw;
1739         ha->isp_ops->disable_intrs(ha);
1740 }
1741
1742 void qla82xx_config_rings(struct scsi_qla_host *vha)
1743 {
1744         struct qla_hw_data *ha = vha->hw;
1745         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1746         struct init_cb_81xx *icb;
1747         struct req_que *req = ha->req_q_map[0];
1748         struct rsp_que *rsp = ha->rsp_q_map[0];
1749
1750         /* Setup ring parameters in initialization control block. */
1751         icb = (struct init_cb_81xx *)ha->init_cb;
1752         icb->request_q_outpointer = __constant_cpu_to_le16(0);
1753         icb->response_q_inpointer = __constant_cpu_to_le16(0);
1754         icb->request_q_length = cpu_to_le16(req->length);
1755         icb->response_q_length = cpu_to_le16(rsp->length);
1756         icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1757         icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1758         icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1759         icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1760
1761         WRT_REG_DWORD((unsigned long  __iomem *)&reg->req_q_out[0], 0);
1762         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_in[0], 0);
1763         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_out[0], 0);
1764 }
1765
1766 static int
1767 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1768 {
1769         u64 *ptr64;
1770         u32 i, flashaddr, size;
1771         __le64 data;
1772
1773         size = (IMAGE_START - BOOTLD_START) / 8;
1774
1775         ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1776         flashaddr = BOOTLD_START;
1777
1778         for (i = 0; i < size; i++) {
1779                 data = cpu_to_le64(ptr64[i]);
1780                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1781                         return -EIO;
1782                 flashaddr += 8;
1783         }
1784
1785         flashaddr = FLASH_ADDR_START;
1786         size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1787         ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1788
1789         for (i = 0; i < size; i++) {
1790                 data = cpu_to_le64(ptr64[i]);
1791
1792                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1793                         return -EIO;
1794                 flashaddr += 8;
1795         }
1796         udelay(100);
1797
1798         /* Write a magic value to CAMRAM register
1799          * at a specified offset to indicate
1800          * that all data is written and
1801          * ready for firmware to initialize.
1802          */
1803         qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1804
1805         read_lock(&ha->hw_lock);
1806         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1807         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1808         read_unlock(&ha->hw_lock);
1809         return 0;
1810 }
1811
1812 static int
1813 qla82xx_set_product_offset(struct qla_hw_data *ha)
1814 {
1815         struct qla82xx_uri_table_desc *ptab_desc = NULL;
1816         const uint8_t *unirom = ha->hablob->fw->data;
1817         uint32_t i;
1818         __le32 entries;
1819         __le32 flags, file_chiprev, offset;
1820         uint8_t chiprev = ha->chip_revision;
1821         /* Hardcoding mn_present flag for P3P */
1822         int mn_present = 0;
1823         uint32_t flagbit;
1824
1825         ptab_desc = qla82xx_get_table_desc(unirom,
1826                  QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1827        if (!ptab_desc)
1828                 return -1;
1829
1830         entries = cpu_to_le32(ptab_desc->num_entries);
1831
1832         for (i = 0; i < entries; i++) {
1833                 offset = cpu_to_le32(ptab_desc->findex) +
1834                         (i * cpu_to_le32(ptab_desc->entry_size));
1835                 flags = cpu_to_le32(*((int *)&unirom[offset] +
1836                         QLA82XX_URI_FLAGS_OFF));
1837                 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1838                         QLA82XX_URI_CHIP_REV_OFF));
1839
1840                 flagbit = mn_present ? 1 : 2;
1841
1842                 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1843                         ha->file_prd_off = offset;
1844                         return 0;
1845                 }
1846         }
1847         return -1;
1848 }
1849
1850 static int
1851 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1852 {
1853         __le32 val;
1854         uint32_t min_size;
1855         struct qla_hw_data *ha = vha->hw;
1856         const struct firmware *fw = ha->hablob->fw;
1857
1858         ha->fw_type = fw_type;
1859
1860         if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1861                 if (qla82xx_set_product_offset(ha))
1862                         return -EINVAL;
1863
1864                 min_size = QLA82XX_URI_FW_MIN_SIZE;
1865         } else {
1866                 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1867                 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1868                         return -EINVAL;
1869
1870                 min_size = QLA82XX_FW_MIN_SIZE;
1871         }
1872
1873         if (fw->size < min_size)
1874                 return -EINVAL;
1875         return 0;
1876 }
1877
1878 static int
1879 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1880 {
1881         u32 val = 0;
1882         int retries = 60;
1883         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1884
1885         do {
1886                 read_lock(&ha->hw_lock);
1887                 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1888                 read_unlock(&ha->hw_lock);
1889
1890                 switch (val) {
1891                 case PHAN_INITIALIZE_COMPLETE:
1892                 case PHAN_INITIALIZE_ACK:
1893                         return QLA_SUCCESS;
1894                 case PHAN_INITIALIZE_FAILED:
1895                         break;
1896                 default:
1897                         break;
1898                 }
1899                 ql_log(ql_log_info, vha, 0x00a8,
1900                     "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1901                     val, retries);
1902
1903                 msleep(500);
1904
1905         } while (--retries);
1906
1907         ql_log(ql_log_fatal, vha, 0x00a9,
1908             "Cmd Peg initialization failed: 0x%x.\n", val);
1909
1910         val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1911         read_lock(&ha->hw_lock);
1912         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1913         read_unlock(&ha->hw_lock);
1914         return QLA_FUNCTION_FAILED;
1915 }
1916
1917 static int
1918 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1919 {
1920         u32 val = 0;
1921         int retries = 60;
1922         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1923
1924         do {
1925                 read_lock(&ha->hw_lock);
1926                 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1927                 read_unlock(&ha->hw_lock);
1928
1929                 switch (val) {
1930                 case PHAN_INITIALIZE_COMPLETE:
1931                 case PHAN_INITIALIZE_ACK:
1932                         return QLA_SUCCESS;
1933                 case PHAN_INITIALIZE_FAILED:
1934                         break;
1935                 default:
1936                         break;
1937                 }
1938                 ql_log(ql_log_info, vha, 0x00ab,
1939                     "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1940                     val, retries);
1941
1942                 msleep(500);
1943
1944         } while (--retries);
1945
1946         ql_log(ql_log_fatal, vha, 0x00ac,
1947             "Rcv Peg initializatin failed: 0x%x.\n", val);
1948         read_lock(&ha->hw_lock);
1949         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1950         read_unlock(&ha->hw_lock);
1951         return QLA_FUNCTION_FAILED;
1952 }
1953
1954 /* ISR related functions */
1955 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1956         QLA82XX_LEGACY_INTR_CONFIG;
1957
1958 /*
1959  * qla82xx_mbx_completion() - Process mailbox command completions.
1960  * @ha: SCSI driver HA context
1961  * @mb0: Mailbox0 register
1962  */
1963 static void
1964 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1965 {
1966         uint16_t        cnt;
1967         uint16_t __iomem *wptr;
1968         struct qla_hw_data *ha = vha->hw;
1969         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1970         wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1971
1972         /* Load return mailbox registers. */
1973         ha->flags.mbox_int = 1;
1974         ha->mailbox_out[0] = mb0;
1975
1976         for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1977                 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1978                 wptr++;
1979         }
1980
1981         if (!ha->mcp)
1982                 ql_dbg(ql_dbg_async, vha, 0x5053,
1983                     "MBX pointer ERROR.\n");
1984 }
1985
1986 /*
1987  * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1988  * @irq:
1989  * @dev_id: SCSI driver HA context
1990  * @regs:
1991  *
1992  * Called by system whenever the host adapter generates an interrupt.
1993  *
1994  * Returns handled flag.
1995  */
1996 irqreturn_t
1997 qla82xx_intr_handler(int irq, void *dev_id)
1998 {
1999         scsi_qla_host_t *vha;
2000         struct qla_hw_data *ha;
2001         struct rsp_que *rsp;
2002         struct device_reg_82xx __iomem *reg;
2003         int status = 0, status1 = 0;
2004         unsigned long   flags;
2005         unsigned long   iter;
2006         uint32_t        stat = 0;
2007         uint16_t        mb[4];
2008
2009         rsp = (struct rsp_que *) dev_id;
2010         if (!rsp) {
2011                 ql_log(ql_log_info, NULL, 0xb053,
2012                     "%s: NULL response queue pointer.\n", __func__);
2013                 return IRQ_NONE;
2014         }
2015         ha = rsp->hw;
2016
2017         if (!ha->flags.msi_enabled) {
2018                 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2019                 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2020                         return IRQ_NONE;
2021
2022                 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2023                 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2024                         return IRQ_NONE;
2025         }
2026
2027         /* clear the interrupt */
2028         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2029
2030         /* read twice to ensure write is flushed */
2031         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2032         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2033
2034         reg = &ha->iobase->isp82;
2035
2036         spin_lock_irqsave(&ha->hardware_lock, flags);
2037         vha = pci_get_drvdata(ha->pdev);
2038         for (iter = 1; iter--; ) {
2039
2040                 if (RD_REG_DWORD(&reg->host_int)) {
2041                         stat = RD_REG_DWORD(&reg->host_status);
2042
2043                         switch (stat & 0xff) {
2044                         case 0x1:
2045                         case 0x2:
2046                         case 0x10:
2047                         case 0x11:
2048                                 qla82xx_mbx_completion(vha, MSW(stat));
2049                                 status |= MBX_INTERRUPT;
2050                                 break;
2051                         case 0x12:
2052                                 mb[0] = MSW(stat);
2053                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2054                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2055                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2056                                 qla2x00_async_event(vha, rsp, mb);
2057                                 break;
2058                         case 0x13:
2059                                 qla24xx_process_response_queue(vha, rsp);
2060                                 break;
2061                         default:
2062                                 ql_dbg(ql_dbg_async, vha, 0x5054,
2063                                     "Unrecognized interrupt type (%d).\n",
2064                                     stat & 0xff);
2065                                 break;
2066                         }
2067                 }
2068                 WRT_REG_DWORD(&reg->host_int, 0);
2069         }
2070         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2071         if (!ha->flags.msi_enabled)
2072                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2073
2074 #ifdef QL_DEBUG_LEVEL_17
2075         if (!irq && ha->flags.eeh_busy)
2076                 ql_log(ql_log_warn, vha, 0x503d,
2077                     "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2078                     status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2079 #endif
2080
2081         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2082             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2083                 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2084                 complete(&ha->mbx_intr_comp);
2085         }
2086         return IRQ_HANDLED;
2087 }
2088
2089 irqreturn_t
2090 qla82xx_msix_default(int irq, void *dev_id)
2091 {
2092         scsi_qla_host_t *vha;
2093         struct qla_hw_data *ha;
2094         struct rsp_que *rsp;
2095         struct device_reg_82xx __iomem *reg;
2096         int status = 0;
2097         unsigned long flags;
2098         uint32_t stat = 0;
2099         uint16_t mb[4];
2100
2101         rsp = (struct rsp_que *) dev_id;
2102         if (!rsp) {
2103                 printk(KERN_INFO
2104                         "%s(): NULL response queue pointer.\n", __func__);
2105                 return IRQ_NONE;
2106         }
2107         ha = rsp->hw;
2108
2109         reg = &ha->iobase->isp82;
2110
2111         spin_lock_irqsave(&ha->hardware_lock, flags);
2112         vha = pci_get_drvdata(ha->pdev);
2113         do {
2114                 if (RD_REG_DWORD(&reg->host_int)) {
2115                         stat = RD_REG_DWORD(&reg->host_status);
2116
2117                         switch (stat & 0xff) {
2118                         case 0x1:
2119                         case 0x2:
2120                         case 0x10:
2121                         case 0x11:
2122                                 qla82xx_mbx_completion(vha, MSW(stat));
2123                                 status |= MBX_INTERRUPT;
2124                                 break;
2125                         case 0x12:
2126                                 mb[0] = MSW(stat);
2127                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2128                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2129                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2130                                 qla2x00_async_event(vha, rsp, mb);
2131                                 break;
2132                         case 0x13:
2133                                 qla24xx_process_response_queue(vha, rsp);
2134                                 break;
2135                         default:
2136                                 ql_dbg(ql_dbg_async, vha, 0x5041,
2137                                     "Unrecognized interrupt type (%d).\n",
2138                                     stat & 0xff);
2139                                 break;
2140                         }
2141                 }
2142                 WRT_REG_DWORD(&reg->host_int, 0);
2143         } while (0);
2144
2145         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2146
2147 #ifdef QL_DEBUG_LEVEL_17
2148         if (!irq && ha->flags.eeh_busy)
2149                 ql_log(ql_log_warn, vha, 0x5044,
2150                     "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2151                     status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2152 #endif
2153
2154         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2155                 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2156                         set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2157                         complete(&ha->mbx_intr_comp);
2158         }
2159         return IRQ_HANDLED;
2160 }
2161
2162 irqreturn_t
2163 qla82xx_msix_rsp_q(int irq, void *dev_id)
2164 {
2165         scsi_qla_host_t *vha;
2166         struct qla_hw_data *ha;
2167         struct rsp_que *rsp;
2168         struct device_reg_82xx __iomem *reg;
2169         unsigned long flags;
2170
2171         rsp = (struct rsp_que *) dev_id;
2172         if (!rsp) {
2173                 printk(KERN_INFO
2174                         "%s(): NULL response queue pointer.\n", __func__);
2175                 return IRQ_NONE;
2176         }
2177
2178         ha = rsp->hw;
2179         reg = &ha->iobase->isp82;
2180         spin_lock_irqsave(&ha->hardware_lock, flags);
2181         vha = pci_get_drvdata(ha->pdev);
2182         qla24xx_process_response_queue(vha, rsp);
2183         WRT_REG_DWORD(&reg->host_int, 0);
2184         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2185         return IRQ_HANDLED;
2186 }
2187
2188 void
2189 qla82xx_poll(int irq, void *dev_id)
2190 {
2191         scsi_qla_host_t *vha;
2192         struct qla_hw_data *ha;
2193         struct rsp_que *rsp;
2194         struct device_reg_82xx __iomem *reg;
2195         int status = 0;
2196         uint32_t stat;
2197         uint16_t mb[4];
2198         unsigned long flags;
2199
2200         rsp = (struct rsp_que *) dev_id;
2201         if (!rsp) {
2202                 printk(KERN_INFO
2203                         "%s(): NULL response queue pointer.\n", __func__);
2204                 return;
2205         }
2206         ha = rsp->hw;
2207
2208         reg = &ha->iobase->isp82;
2209         spin_lock_irqsave(&ha->hardware_lock, flags);
2210         vha = pci_get_drvdata(ha->pdev);
2211
2212         if (RD_REG_DWORD(&reg->host_int)) {
2213                 stat = RD_REG_DWORD(&reg->host_status);
2214                 switch (stat & 0xff) {
2215                 case 0x1:
2216                 case 0x2:
2217                 case 0x10:
2218                 case 0x11:
2219                         qla82xx_mbx_completion(vha, MSW(stat));
2220                         status |= MBX_INTERRUPT;
2221                         break;
2222                 case 0x12:
2223                         mb[0] = MSW(stat);
2224                         mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2225                         mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2226                         mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2227                         qla2x00_async_event(vha, rsp, mb);
2228                         break;
2229                 case 0x13:
2230                         qla24xx_process_response_queue(vha, rsp);
2231                         break;
2232                 default:
2233                         ql_dbg(ql_dbg_p3p, vha, 0xb013,
2234                             "Unrecognized interrupt type (%d).\n",
2235                             stat * 0xff);
2236                         break;
2237                 }
2238         }
2239         WRT_REG_DWORD(&reg->host_int, 0);
2240         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2241 }
2242
2243 void
2244 qla82xx_enable_intrs(struct qla_hw_data *ha)
2245 {
2246         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2247         qla82xx_mbx_intr_enable(vha);
2248         spin_lock_irq(&ha->hardware_lock);
2249         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2250         spin_unlock_irq(&ha->hardware_lock);
2251         ha->interrupts_on = 1;
2252 }
2253
2254 void
2255 qla82xx_disable_intrs(struct qla_hw_data *ha)
2256 {
2257         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2258         qla82xx_mbx_intr_disable(vha);
2259         spin_lock_irq(&ha->hardware_lock);
2260         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2261         spin_unlock_irq(&ha->hardware_lock);
2262         ha->interrupts_on = 0;
2263 }
2264
2265 void qla82xx_init_flags(struct qla_hw_data *ha)
2266 {
2267         struct qla82xx_legacy_intr_set *nx_legacy_intr;
2268
2269         /* ISP 8021 initializations */
2270         rwlock_init(&ha->hw_lock);
2271         ha->qdr_sn_window = -1;
2272         ha->ddr_mn_window = -1;
2273         ha->curr_window = 255;
2274         ha->portnum = PCI_FUNC(ha->pdev->devfn);
2275         nx_legacy_intr = &legacy_intr[ha->portnum];
2276         ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2277         ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2278         ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2279         ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2280 }
2281
2282 inline void
2283 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2284 {
2285         int idc_ver;
2286         uint32_t drv_active;
2287         struct qla_hw_data *ha = vha->hw;
2288
2289         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2290         if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2291                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2292                     QLA82XX_IDC_VERSION);
2293                 ql_log(ql_log_info, vha, 0xb082,
2294                     "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2295         } else {
2296                 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2297                 if (idc_ver != QLA82XX_IDC_VERSION)
2298                         ql_log(ql_log_info, vha, 0xb083,
2299                             "qla2xxx driver IDC version %d is not compatible "
2300                             "with IDC version %d of the other drivers\n",
2301                             QLA82XX_IDC_VERSION, idc_ver);
2302         }
2303 }
2304
2305 inline void
2306 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2307 {
2308         uint32_t drv_active;
2309         struct qla_hw_data *ha = vha->hw;
2310
2311         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2312
2313         /* If reset value is all FF's, initialize DRV_ACTIVE */
2314         if (drv_active == 0xffffffff) {
2315                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2316                         QLA82XX_DRV_NOT_ACTIVE);
2317                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2318         }
2319         drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2320         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2321 }
2322
2323 inline void
2324 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2325 {
2326         uint32_t drv_active;
2327
2328         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2329         drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2330         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2331 }
2332
2333 static inline int
2334 qla82xx_need_reset(struct qla_hw_data *ha)
2335 {
2336         uint32_t drv_state;
2337         int rval;
2338
2339         if (ha->flags.nic_core_reset_owner)
2340                 return 1;
2341         else {
2342                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2343                 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2344                 return rval;
2345         }
2346 }
2347
2348 static inline void
2349 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2350 {
2351         uint32_t drv_state;
2352         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2353
2354         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2355
2356         /* If reset value is all FF's, initialize DRV_STATE */
2357         if (drv_state == 0xffffffff) {
2358                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2359                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2360         }
2361         drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2362         ql_dbg(ql_dbg_init, vha, 0x00bb,
2363             "drv_state = 0x%08x.\n", drv_state);
2364         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2365 }
2366
2367 static inline void
2368 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2369 {
2370         uint32_t drv_state;
2371
2372         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2373         drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2374         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2375 }
2376
2377 static inline void
2378 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2379 {
2380         uint32_t qsnt_state;
2381
2382         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2383         qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2384         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2385 }
2386
2387 void
2388 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2389 {
2390         struct qla_hw_data *ha = vha->hw;
2391         uint32_t qsnt_state;
2392
2393         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2394         qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2395         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2396 }
2397
2398 static int
2399 qla82xx_load_fw(scsi_qla_host_t *vha)
2400 {
2401         int rst;
2402         struct fw_blob *blob;
2403         struct qla_hw_data *ha = vha->hw;
2404
2405         if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2406                 ql_log(ql_log_fatal, vha, 0x009f,
2407                     "Error during CRB initialization.\n");
2408                 return QLA_FUNCTION_FAILED;
2409         }
2410         udelay(500);
2411
2412         /* Bring QM and CAMRAM out of reset */
2413         rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2414         rst &= ~((1 << 28) | (1 << 24));
2415         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2416
2417         /*
2418          * FW Load priority:
2419          * 1) Operational firmware residing in flash.
2420          * 2) Firmware via request-firmware interface (.bin file).
2421          */
2422         if (ql2xfwloadbin == 2)
2423                 goto try_blob_fw;
2424
2425         ql_log(ql_log_info, vha, 0x00a0,
2426             "Attempting to load firmware from flash.\n");
2427
2428         if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2429                 ql_log(ql_log_info, vha, 0x00a1,
2430                     "Firmware loaded successfully from flash.\n");
2431                 return QLA_SUCCESS;
2432         } else {
2433                 ql_log(ql_log_warn, vha, 0x0108,
2434                     "Firmware load from flash failed.\n");
2435         }
2436
2437 try_blob_fw:
2438         ql_log(ql_log_info, vha, 0x00a2,
2439             "Attempting to load firmware from blob.\n");
2440
2441         /* Load firmware blob. */
2442         blob = ha->hablob = qla2x00_request_firmware(vha);
2443         if (!blob) {
2444                 ql_log(ql_log_fatal, vha, 0x00a3,
2445                     "Firmware image not present.\n");
2446                 goto fw_load_failed;
2447         }
2448
2449         /* Validating firmware blob */
2450         if (qla82xx_validate_firmware_blob(vha,
2451                 QLA82XX_FLASH_ROMIMAGE)) {
2452                 /* Fallback to URI format */
2453                 if (qla82xx_validate_firmware_blob(vha,
2454                         QLA82XX_UNIFIED_ROMIMAGE)) {
2455                         ql_log(ql_log_fatal, vha, 0x00a4,
2456                             "No valid firmware image found.\n");
2457                         return QLA_FUNCTION_FAILED;
2458                 }
2459         }
2460
2461         if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2462                 ql_log(ql_log_info, vha, 0x00a5,
2463                     "Firmware loaded successfully from binary blob.\n");
2464                 return QLA_SUCCESS;
2465         } else {
2466                 ql_log(ql_log_fatal, vha, 0x00a6,
2467                     "Firmware load failed for binary blob.\n");
2468                 blob->fw = NULL;
2469                 blob = NULL;
2470                 goto fw_load_failed;
2471         }
2472         return QLA_SUCCESS;
2473
2474 fw_load_failed:
2475         return QLA_FUNCTION_FAILED;
2476 }
2477
2478 int
2479 qla82xx_start_firmware(scsi_qla_host_t *vha)
2480 {
2481         uint16_t      lnk;
2482         struct qla_hw_data *ha = vha->hw;
2483
2484         /* scrub dma mask expansion register */
2485         qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2486
2487         /* Put both the PEG CMD and RCV PEG to default state
2488          * of 0 before resetting the hardware
2489          */
2490         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2491         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2492
2493         /* Overwrite stale initialization register values */
2494         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2495         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2496
2497         if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2498                 ql_log(ql_log_fatal, vha, 0x00a7,
2499                     "Error trying to start fw.\n");
2500                 return QLA_FUNCTION_FAILED;
2501         }
2502
2503         /* Handshake with the card before we register the devices. */
2504         if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2505                 ql_log(ql_log_fatal, vha, 0x00aa,
2506                     "Error during card handshake.\n");
2507                 return QLA_FUNCTION_FAILED;
2508         }
2509
2510         /* Negotiated Link width */
2511         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2512         ha->link_width = (lnk >> 4) & 0x3f;
2513
2514         /* Synchronize with Receive peg */
2515         return qla82xx_check_rcvpeg_state(ha);
2516 }
2517
2518 static uint32_t *
2519 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2520         uint32_t length)
2521 {
2522         uint32_t i;
2523         uint32_t val;
2524         struct qla_hw_data *ha = vha->hw;
2525
2526         /* Dword reads to flash. */
2527         for (i = 0; i < length/4; i++, faddr += 4) {
2528                 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2529                         ql_log(ql_log_warn, vha, 0x0106,
2530                             "Do ROM fast read failed.\n");
2531                         goto done_read;
2532                 }
2533                 dwptr[i] = __constant_cpu_to_le32(val);
2534         }
2535 done_read:
2536         return dwptr;
2537 }
2538
2539 static int
2540 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2541 {
2542         int ret;
2543         uint32_t val;
2544         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2545
2546         ret = ql82xx_rom_lock_d(ha);
2547         if (ret < 0) {
2548                 ql_log(ql_log_warn, vha, 0xb014,
2549                     "ROM Lock failed.\n");
2550                 return ret;
2551         }
2552
2553         ret = qla82xx_read_status_reg(ha, &val);
2554         if (ret < 0)
2555                 goto done_unprotect;
2556
2557         val &= ~(BLOCK_PROTECT_BITS << 2);
2558         ret = qla82xx_write_status_reg(ha, val);
2559         if (ret < 0) {
2560                 val |= (BLOCK_PROTECT_BITS << 2);
2561                 qla82xx_write_status_reg(ha, val);
2562         }
2563
2564         if (qla82xx_write_disable_flash(ha) != 0)
2565                 ql_log(ql_log_warn, vha, 0xb015,
2566                     "Write disable failed.\n");
2567
2568 done_unprotect:
2569         qla82xx_rom_unlock(ha);
2570         return ret;
2571 }
2572
2573 static int
2574 qla82xx_protect_flash(struct qla_hw_data *ha)
2575 {
2576         int ret;
2577         uint32_t val;
2578         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2579
2580         ret = ql82xx_rom_lock_d(ha);
2581         if (ret < 0) {
2582                 ql_log(ql_log_warn, vha, 0xb016,
2583                     "ROM Lock failed.\n");
2584                 return ret;
2585         }
2586
2587         ret = qla82xx_read_status_reg(ha, &val);
2588         if (ret < 0)
2589                 goto done_protect;
2590
2591         val |= (BLOCK_PROTECT_BITS << 2);
2592         /* LOCK all sectors */
2593         ret = qla82xx_write_status_reg(ha, val);
2594         if (ret < 0)
2595                 ql_log(ql_log_warn, vha, 0xb017,
2596                     "Write status register failed.\n");
2597
2598         if (qla82xx_write_disable_flash(ha) != 0)
2599                 ql_log(ql_log_warn, vha, 0xb018,
2600                     "Write disable failed.\n");
2601 done_protect:
2602         qla82xx_rom_unlock(ha);
2603         return ret;
2604 }
2605
2606 static int
2607 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2608 {
2609         int ret = 0;
2610         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2611
2612         ret = ql82xx_rom_lock_d(ha);
2613         if (ret < 0) {
2614                 ql_log(ql_log_warn, vha, 0xb019,
2615                     "ROM Lock failed.\n");
2616                 return ret;
2617         }
2618
2619         qla82xx_flash_set_write_enable(ha);
2620         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2621         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2622         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2623
2624         if (qla82xx_wait_rom_done(ha)) {
2625                 ql_log(ql_log_warn, vha, 0xb01a,
2626                     "Error waiting for rom done.\n");
2627                 ret = -1;
2628                 goto done;
2629         }
2630         ret = qla82xx_flash_wait_write_finish(ha);
2631 done:
2632         qla82xx_rom_unlock(ha);
2633         return ret;
2634 }
2635
2636 /*
2637  * Address and length are byte address
2638  */
2639 uint8_t *
2640 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2641         uint32_t offset, uint32_t length)
2642 {
2643         scsi_block_requests(vha->host);
2644         qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2645         scsi_unblock_requests(vha->host);
2646         return buf;
2647 }
2648
2649 static int
2650 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2651         uint32_t faddr, uint32_t dwords)
2652 {
2653         int ret;
2654         uint32_t liter;
2655         uint32_t sec_mask, rest_addr;
2656         dma_addr_t optrom_dma;
2657         void *optrom = NULL;
2658         int page_mode = 0;
2659         struct qla_hw_data *ha = vha->hw;
2660
2661         ret = -1;
2662
2663         /* Prepare burst-capable write on supported ISPs. */
2664         if (page_mode && !(faddr & 0xfff) &&
2665             dwords > OPTROM_BURST_DWORDS) {
2666                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2667                     &optrom_dma, GFP_KERNEL);
2668                 if (!optrom) {
2669                         ql_log(ql_log_warn, vha, 0xb01b,
2670                             "Unable to allocate memory "
2671                             "for optrom burst write (%x KB).\n",
2672                             OPTROM_BURST_SIZE / 1024);
2673                 }
2674         }
2675
2676         rest_addr = ha->fdt_block_size - 1;
2677         sec_mask = ~rest_addr;
2678
2679         ret = qla82xx_unprotect_flash(ha);
2680         if (ret) {
2681                 ql_log(ql_log_warn, vha, 0xb01c,
2682                     "Unable to unprotect flash for update.\n");
2683                 goto write_done;
2684         }
2685
2686         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2687                 /* Are we at the beginning of a sector? */
2688                 if ((faddr & rest_addr) == 0) {
2689
2690                         ret = qla82xx_erase_sector(ha, faddr);
2691                         if (ret) {
2692                                 ql_log(ql_log_warn, vha, 0xb01d,
2693                                     "Unable to erase sector: address=%x.\n",
2694                                     faddr);
2695                                 break;
2696                         }
2697                 }
2698
2699                 /* Go with burst-write. */
2700                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2701                         /* Copy data to DMA'ble buffer. */
2702                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2703
2704                         ret = qla2x00_load_ram(vha, optrom_dma,
2705                             (ha->flash_data_off | faddr),
2706                             OPTROM_BURST_DWORDS);
2707                         if (ret != QLA_SUCCESS) {
2708                                 ql_log(ql_log_warn, vha, 0xb01e,
2709                                     "Unable to burst-write optrom segment "
2710                                     "(%x/%x/%llx).\n", ret,
2711                                     (ha->flash_data_off | faddr),
2712                                     (unsigned long long)optrom_dma);
2713                                 ql_log(ql_log_warn, vha, 0xb01f,
2714                                     "Reverting to slow-write.\n");
2715
2716                                 dma_free_coherent(&ha->pdev->dev,
2717                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2718                                 optrom = NULL;
2719                         } else {
2720                                 liter += OPTROM_BURST_DWORDS - 1;
2721                                 faddr += OPTROM_BURST_DWORDS - 1;
2722                                 dwptr += OPTROM_BURST_DWORDS - 1;
2723                                 continue;
2724                         }
2725                 }
2726
2727                 ret = qla82xx_write_flash_dword(ha, faddr,
2728                     cpu_to_le32(*dwptr));
2729                 if (ret) {
2730                         ql_dbg(ql_dbg_p3p, vha, 0xb020,
2731                             "Unable to program flash address=%x data=%x.\n",
2732                             faddr, *dwptr);
2733                         break;
2734                 }
2735         }
2736
2737         ret = qla82xx_protect_flash(ha);
2738         if (ret)
2739                 ql_log(ql_log_warn, vha, 0xb021,
2740                     "Unable to protect flash after update.\n");
2741 write_done:
2742         if (optrom)
2743                 dma_free_coherent(&ha->pdev->dev,
2744                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2745         return ret;
2746 }
2747
2748 int
2749 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2750         uint32_t offset, uint32_t length)
2751 {
2752         int rval;
2753
2754         /* Suspend HBA. */
2755         scsi_block_requests(vha->host);
2756         rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2757                 length >> 2);
2758         scsi_unblock_requests(vha->host);
2759
2760         /* Convert return ISP82xx to generic */
2761         if (rval)
2762                 rval = QLA_FUNCTION_FAILED;
2763         else
2764                 rval = QLA_SUCCESS;
2765         return rval;
2766 }
2767
2768 void
2769 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2770 {
2771         struct qla_hw_data *ha = vha->hw;
2772         struct req_que *req = ha->req_q_map[0];
2773         struct device_reg_82xx __iomem *reg;
2774         uint32_t dbval;
2775
2776         /* Adjust ring index. */
2777         req->ring_index++;
2778         if (req->ring_index == req->length) {
2779                 req->ring_index = 0;
2780                 req->ring_ptr = req->ring;
2781         } else
2782                 req->ring_ptr++;
2783
2784         reg = &ha->iobase->isp82;
2785         dbval = 0x04 | (ha->portnum << 5);
2786
2787         dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2788         if (ql2xdbwr)
2789                 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2790         else {
2791                 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
2792                 wmb();
2793                 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
2794                         WRT_REG_DWORD((unsigned long  __iomem *)ha->nxdb_wr_ptr,
2795                                 dbval);
2796                         wmb();
2797                 }
2798         }
2799 }
2800
2801 static void
2802 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2803 {
2804         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2805
2806         if (qla82xx_rom_lock(ha))
2807                 /* Someone else is holding the lock. */
2808                 ql_log(ql_log_info, vha, 0xb022,
2809                     "Resetting rom_lock.\n");
2810
2811         /*
2812          * Either we got the lock, or someone
2813          * else died while holding it.
2814          * In either case, unlock.
2815          */
2816         qla82xx_rom_unlock(ha);
2817 }
2818
2819 /*
2820  * qla82xx_device_bootstrap
2821  *    Initialize device, set DEV_READY, start fw
2822  *
2823  * Note:
2824  *      IDC lock must be held upon entry
2825  *
2826  * Return:
2827  *    Success : 0
2828  *    Failed  : 1
2829  */
2830 static int
2831 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2832 {
2833         int rval = QLA_SUCCESS;
2834         int i, timeout;
2835         uint32_t old_count, count;
2836         struct qla_hw_data *ha = vha->hw;
2837         int need_reset = 0, peg_stuck = 1;
2838
2839         need_reset = qla82xx_need_reset(ha);
2840
2841         old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2842
2843         for (i = 0; i < 10; i++) {
2844                 timeout = msleep_interruptible(200);
2845                 if (timeout) {
2846                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2847                                 QLA8XXX_DEV_FAILED);
2848                         return QLA_FUNCTION_FAILED;
2849                 }
2850
2851                 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2852                 if (count != old_count)
2853                         peg_stuck = 0;
2854         }
2855
2856         if (need_reset) {
2857                 /* We are trying to perform a recovery here. */
2858                 if (peg_stuck)
2859                         qla82xx_rom_lock_recovery(ha);
2860                 goto dev_initialize;
2861         } else  {
2862                 /* Start of day for this ha context. */
2863                 if (peg_stuck) {
2864                         /* Either we are the first or recovery in progress. */
2865                         qla82xx_rom_lock_recovery(ha);
2866                         goto dev_initialize;
2867                 } else
2868                         /* Firmware already running. */
2869                         goto dev_ready;
2870         }
2871
2872         return rval;
2873
2874 dev_initialize:
2875         /* set to DEV_INITIALIZING */
2876         ql_log(ql_log_info, vha, 0x009e,
2877             "HW State: INITIALIZING.\n");
2878         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2879
2880         qla82xx_idc_unlock(ha);
2881         rval = qla82xx_start_firmware(vha);
2882         qla82xx_idc_lock(ha);
2883
2884         if (rval != QLA_SUCCESS) {
2885                 ql_log(ql_log_fatal, vha, 0x00ad,
2886                     "HW State: FAILED.\n");
2887                 qla82xx_clear_drv_active(ha);
2888                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2889                 return rval;
2890         }
2891
2892 dev_ready:
2893         ql_log(ql_log_info, vha, 0x00ae,
2894             "HW State: READY.\n");
2895         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2896
2897         return QLA_SUCCESS;
2898 }
2899
2900 /*
2901 * qla82xx_need_qsnt_handler
2902 *    Code to start quiescence sequence
2903 *
2904 * Note:
2905 *      IDC lock must be held upon entry
2906 *
2907 * Return: void
2908 */
2909
2910 static void
2911 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2912 {
2913         struct qla_hw_data *ha = vha->hw;
2914         uint32_t dev_state, drv_state, drv_active;
2915         unsigned long reset_timeout;
2916
2917         if (vha->flags.online) {
2918                 /*Block any further I/O and wait for pending cmnds to complete*/
2919                 qla2x00_quiesce_io(vha);
2920         }
2921
2922         /* Set the quiescence ready bit */
2923         qla82xx_set_qsnt_ready(ha);
2924
2925         /*wait for 30 secs for other functions to ack */
2926         reset_timeout = jiffies + (30 * HZ);
2927
2928         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2929         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2930         /* Its 2 that is written when qsnt is acked, moving one bit */
2931         drv_active = drv_active << 0x01;
2932
2933         while (drv_state != drv_active) {
2934
2935                 if (time_after_eq(jiffies, reset_timeout)) {
2936                         /* quiescence timeout, other functions didn't ack
2937                          * changing the state to DEV_READY
2938                          */
2939                         ql_log(ql_log_info, vha, 0xb023,
2940                             "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2941                             "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2942                             drv_active, drv_state);
2943                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2944                             QLA8XXX_DEV_READY);
2945                         ql_log(ql_log_info, vha, 0xb025,
2946                             "HW State: DEV_READY.\n");
2947                         qla82xx_idc_unlock(ha);
2948                         qla2x00_perform_loop_resync(vha);
2949                         qla82xx_idc_lock(ha);
2950
2951                         qla82xx_clear_qsnt_ready(vha);
2952                         return;
2953                 }
2954
2955                 qla82xx_idc_unlock(ha);
2956                 msleep(1000);
2957                 qla82xx_idc_lock(ha);
2958
2959                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2960                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2961                 drv_active = drv_active << 0x01;
2962         }
2963         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2964         /* everyone acked so set the state to DEV_QUIESCENCE */
2965         if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2966                 ql_log(ql_log_info, vha, 0xb026,
2967                     "HW State: DEV_QUIESCENT.\n");
2968                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2969         }
2970 }
2971
2972 /*
2973 * qla82xx_wait_for_state_change
2974 *    Wait for device state to change from given current state
2975 *
2976 * Note:
2977 *     IDC lock must not be held upon entry
2978 *
2979 * Return:
2980 *    Changed device state.
2981 */
2982 uint32_t
2983 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2984 {
2985         struct qla_hw_data *ha = vha->hw;
2986         uint32_t dev_state;
2987
2988         do {
2989                 msleep(1000);
2990                 qla82xx_idc_lock(ha);
2991                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2992                 qla82xx_idc_unlock(ha);
2993         } while (dev_state == curr_state);
2994
2995         return dev_state;
2996 }
2997
2998 void
2999 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3000 {
3001         struct qla_hw_data *ha = vha->hw;
3002
3003         /* Disable the board */
3004         ql_log(ql_log_fatal, vha, 0x00b8,
3005             "Disabling the board.\n");
3006
3007         if (IS_QLA82XX(ha)) {
3008                 qla82xx_clear_drv_active(ha);
3009                 qla82xx_idc_unlock(ha);
3010         }
3011
3012         /* Set DEV_FAILED flag to disable timer */
3013         vha->device_flags |= DFLG_DEV_FAILED;
3014         qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3015         qla2x00_mark_all_devices_lost(vha, 0);
3016         vha->flags.online = 0;
3017         vha->flags.init_done = 0;
3018 }
3019
3020 /*
3021  * qla82xx_need_reset_handler
3022  *    Code to start reset sequence
3023  *
3024  * Note:
3025  *      IDC lock must be held upon entry
3026  *
3027  * Return:
3028  *    Success : 0
3029  *    Failed  : 1
3030  */
3031 static void
3032 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3033 {
3034         uint32_t dev_state, drv_state, drv_active;
3035         uint32_t active_mask = 0;
3036         unsigned long reset_timeout;
3037         struct qla_hw_data *ha = vha->hw;
3038         struct req_que *req = ha->req_q_map[0];
3039
3040         if (vha->flags.online) {
3041                 qla82xx_idc_unlock(ha);
3042                 qla2x00_abort_isp_cleanup(vha);
3043                 ha->isp_ops->get_flash_version(vha, req->ring);
3044                 ha->isp_ops->nvram_config(vha);
3045                 qla82xx_idc_lock(ha);
3046         }
3047
3048         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3049         if (!ha->flags.nic_core_reset_owner) {
3050                 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3051                     "reset_acknowledged by 0x%x\n", ha->portnum);
3052                 qla82xx_set_rst_ready(ha);
3053         } else {
3054                 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3055                 drv_active &= active_mask;
3056                 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3057                     "active_mask: 0x%08x\n", active_mask);
3058         }
3059
3060         /* wait for 10 seconds for reset ack from all functions */
3061         reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3062
3063         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3064         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3065         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3066
3067         ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3068             "drv_state: 0x%08x, drv_active: 0x%08x, "
3069             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3070             drv_state, drv_active, dev_state, active_mask);
3071
3072         while (drv_state != drv_active &&
3073             dev_state != QLA8XXX_DEV_INITIALIZING) {
3074                 if (time_after_eq(jiffies, reset_timeout)) {
3075                         ql_log(ql_log_warn, vha, 0x00b5,
3076                             "Reset timeout.\n");
3077                         break;
3078                 }
3079                 qla82xx_idc_unlock(ha);
3080                 msleep(1000);
3081                 qla82xx_idc_lock(ha);
3082                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3083                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3084                 if (ha->flags.nic_core_reset_owner)
3085                         drv_active &= active_mask;
3086                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3087         }
3088
3089         ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3090             "drv_state: 0x%08x, drv_active: 0x%08x, "
3091             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3092             drv_state, drv_active, dev_state, active_mask);
3093
3094         ql_log(ql_log_info, vha, 0x00b6,
3095             "Device state is 0x%x = %s.\n",
3096             dev_state,
3097             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3098
3099         /* Force to DEV_COLD unless someone else is starting a reset */
3100         if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3101             dev_state != QLA8XXX_DEV_COLD) {
3102                 ql_log(ql_log_info, vha, 0x00b7,
3103                     "HW State: COLD/RE-INIT.\n");
3104                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3105                 qla82xx_set_rst_ready(ha);
3106                 if (ql2xmdenable) {
3107                         if (qla82xx_md_collect(vha))
3108                                 ql_log(ql_log_warn, vha, 0xb02c,
3109                                     "Minidump not collected.\n");
3110                 } else
3111                         ql_log(ql_log_warn, vha, 0xb04f,
3112                             "Minidump disabled.\n");
3113         }
3114 }
3115
3116 int
3117 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3118 {
3119         struct qla_hw_data *ha = vha->hw;
3120         uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3121         int rval = QLA_SUCCESS;
3122
3123         fw_major_version = ha->fw_major_version;
3124         fw_minor_version = ha->fw_minor_version;
3125         fw_subminor_version = ha->fw_subminor_version;
3126
3127         rval = qla2x00_get_fw_version(vha);
3128         if (rval != QLA_SUCCESS)
3129                 return rval;
3130
3131         if (ql2xmdenable) {
3132                 if (!ha->fw_dumped) {
3133                         if (fw_major_version != ha->fw_major_version ||
3134                             fw_minor_version != ha->fw_minor_version ||
3135                             fw_subminor_version != ha->fw_subminor_version) {
3136                                 ql_log(ql_log_info, vha, 0xb02d,
3137                                     "Firmware version differs "
3138                                     "Previous version: %d:%d:%d - "
3139                                     "New version: %d:%d:%d\n",
3140                                     fw_major_version, fw_minor_version,
3141                                     fw_subminor_version,
3142                                     ha->fw_major_version,
3143                                     ha->fw_minor_version,
3144                                     ha->fw_subminor_version);
3145                                 /* Release MiniDump resources */
3146                                 qla82xx_md_free(vha);
3147                                 /* ALlocate MiniDump resources */
3148                                 qla82xx_md_prep(vha);
3149                         }
3150                 } else
3151                         ql_log(ql_log_info, vha, 0xb02e,
3152                             "Firmware dump available to retrieve\n");
3153         }
3154         return rval;
3155 }
3156
3157
3158 static int
3159 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3160 {
3161         uint32_t fw_heartbeat_counter;
3162         int status = 0;
3163
3164         fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3165                 QLA82XX_PEG_ALIVE_COUNTER);
3166         /* all 0xff, assume AER/EEH in progress, ignore */
3167         if (fw_heartbeat_counter == 0xffffffff) {
3168                 ql_dbg(ql_dbg_timer, vha, 0x6003,
3169                     "FW heartbeat counter is 0xffffffff, "
3170                     "returning status=%d.\n", status);
3171                 return status;
3172         }
3173         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3174                 vha->seconds_since_last_heartbeat++;
3175                 /* FW not alive after 2 seconds */
3176                 if (vha->seconds_since_last_heartbeat == 2) {
3177                         vha->seconds_since_last_heartbeat = 0;
3178                         status = 1;
3179                 }
3180         } else
3181                 vha->seconds_since_last_heartbeat = 0;
3182         vha->fw_heartbeat_counter = fw_heartbeat_counter;
3183         if (status)
3184                 ql_dbg(ql_dbg_timer, vha, 0x6004,
3185                     "Returning status=%d.\n", status);
3186         return status;
3187 }
3188
3189 /*
3190  * qla82xx_device_state_handler
3191  *      Main state handler
3192  *
3193  * Note:
3194  *      IDC lock must be held upon entry
3195  *
3196  * Return:
3197  *    Success : 0
3198  *    Failed  : 1
3199  */
3200 int
3201 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3202 {
3203         uint32_t dev_state;
3204         uint32_t old_dev_state;
3205         int rval = QLA_SUCCESS;
3206         unsigned long dev_init_timeout;
3207         struct qla_hw_data *ha = vha->hw;
3208         int loopcount = 0;
3209
3210         qla82xx_idc_lock(ha);
3211         if (!vha->flags.init_done) {
3212                 qla82xx_set_drv_active(vha);
3213                 qla82xx_set_idc_version(vha);
3214         }
3215
3216         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3217         old_dev_state = dev_state;
3218         ql_log(ql_log_info, vha, 0x009b,
3219             "Device state is 0x%x = %s.\n",
3220             dev_state,
3221             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3222
3223         /* wait for 30 seconds for device to go ready */
3224         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3225
3226         while (1) {
3227
3228                 if (time_after_eq(jiffies, dev_init_timeout)) {
3229                         ql_log(ql_log_fatal, vha, 0x009c,
3230                             "Device init failed.\n");
3231                         rval = QLA_FUNCTION_FAILED;
3232                         break;
3233                 }
3234                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3235                 if (old_dev_state != dev_state) {
3236                         loopcount = 0;
3237                         old_dev_state = dev_state;
3238                 }
3239                 if (loopcount < 5) {
3240                         ql_log(ql_log_info, vha, 0x009d,
3241                             "Device state is 0x%x = %s.\n",
3242                             dev_state,
3243                             dev_state < MAX_STATES ? qdev_state(dev_state) :
3244                             "Unknown");
3245                 }
3246
3247                 switch (dev_state) {
3248                 case QLA8XXX_DEV_READY:
3249                         ha->flags.nic_core_reset_owner = 0;
3250                         goto rel_lock;
3251                 case QLA8XXX_DEV_COLD:
3252                         rval = qla82xx_device_bootstrap(vha);
3253                         break;
3254                 case QLA8XXX_DEV_INITIALIZING:
3255                         qla82xx_idc_unlock(ha);
3256                         msleep(1000);
3257                         qla82xx_idc_lock(ha);
3258                         break;
3259                 case QLA8XXX_DEV_NEED_RESET:
3260                         if (!ql2xdontresethba)
3261                                 qla82xx_need_reset_handler(vha);
3262                         else {
3263                                 qla82xx_idc_unlock(ha);
3264                                 msleep(1000);
3265                                 qla82xx_idc_lock(ha);
3266                         }
3267                         dev_init_timeout = jiffies +
3268                             (ha->fcoe_dev_init_timeout * HZ);
3269                         break;
3270                 case QLA8XXX_DEV_NEED_QUIESCENT:
3271                         qla82xx_need_qsnt_handler(vha);
3272                         /* Reset timeout value after quiescence handler */
3273                         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3274                                                          * HZ);
3275                         break;
3276                 case QLA8XXX_DEV_QUIESCENT:
3277                         /* Owner will exit and other will wait for the state
3278                          * to get changed
3279                          */
3280                         if (ha->flags.quiesce_owner)
3281                                 goto rel_lock;
3282
3283                         qla82xx_idc_unlock(ha);
3284                         msleep(1000);
3285                         qla82xx_idc_lock(ha);
3286
3287                         /* Reset timeout value after quiescence handler */
3288                         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3289                                                          * HZ);
3290                         break;
3291                 case QLA8XXX_DEV_FAILED:
3292                         qla8xxx_dev_failed_handler(vha);
3293                         rval = QLA_FUNCTION_FAILED;
3294                         goto exit;
3295                 default:
3296                         qla82xx_idc_unlock(ha);
3297                         msleep(1000);
3298                         qla82xx_idc_lock(ha);
3299                 }
3300                 loopcount++;
3301         }
3302 rel_lock:
3303         qla82xx_idc_unlock(ha);
3304 exit:
3305         return rval;
3306 }
3307
3308 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3309 {
3310         uint32_t temp, temp_state, temp_val;
3311         struct qla_hw_data *ha = vha->hw;
3312
3313         temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3314         temp_state = qla82xx_get_temp_state(temp);
3315         temp_val = qla82xx_get_temp_val(temp);
3316
3317         if (temp_state == QLA82XX_TEMP_PANIC) {
3318                 ql_log(ql_log_warn, vha, 0x600e,
3319                     "Device temperature %d degrees C exceeds "
3320                     " maximum allowed. Hardware has been shut down.\n",
3321                     temp_val);
3322                 return 1;
3323         } else if (temp_state == QLA82XX_TEMP_WARN) {
3324                 ql_log(ql_log_warn, vha, 0x600f,
3325                     "Device temperature %d degrees C exceeds "
3326                     "operating range. Immediate action needed.\n",
3327                     temp_val);
3328         }
3329         return 0;
3330 }
3331
3332 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3333 {
3334         struct qla_hw_data *ha = vha->hw;
3335
3336         if (ha->flags.mbox_busy) {
3337                 ha->flags.mbox_int = 1;
3338                 ha->flags.mbox_busy = 0;
3339                 ql_log(ql_log_warn, vha, 0x6010,
3340                     "Doing premature completion of mbx command.\n");
3341                 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3342                         complete(&ha->mbx_intr_comp);
3343         }
3344 }
3345
3346 void qla82xx_watchdog(scsi_qla_host_t *vha)
3347 {
3348         uint32_t dev_state, halt_status;
3349         struct qla_hw_data *ha = vha->hw;
3350
3351         /* don't poll if reset is going on */
3352         if (!ha->flags.nic_core_reset_hdlr_active) {
3353                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3354                 if (qla82xx_check_temp(vha)) {
3355                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3356                         ha->flags.isp82xx_fw_hung = 1;
3357                         qla82xx_clear_pending_mbx(vha);
3358                 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3359                     !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3360                         ql_log(ql_log_warn, vha, 0x6001,
3361                             "Adapter reset needed.\n");
3362                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3363                 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3364                         !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3365                         ql_log(ql_log_warn, vha, 0x6002,
3366                             "Quiescent needed.\n");
3367                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3368                 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3369                         !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3370                         vha->flags.online == 1) {
3371                         ql_log(ql_log_warn, vha, 0xb055,
3372                             "Adapter state is failed. Offlining.\n");
3373                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3374                         ha->flags.isp82xx_fw_hung = 1;
3375                         qla82xx_clear_pending_mbx(vha);
3376                 } else {
3377                         if (qla82xx_check_fw_alive(vha)) {
3378                                 ql_dbg(ql_dbg_timer, vha, 0x6011,
3379                                     "disabling pause transmit on port 0 & 1.\n");
3380                                 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3381                                     CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3382                                 halt_status = qla82xx_rd_32(ha,
3383                                     QLA82XX_PEG_HALT_STATUS1);
3384                                 ql_log(ql_log_info, vha, 0x6005,
3385                                     "dumping hw/fw registers:.\n "
3386                                     " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3387                                     " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3388                                     " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3389                                     " PEG_NET_4_PC: 0x%x.\n", halt_status,
3390                                     qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3391                                     qla82xx_rd_32(ha,
3392                                             QLA82XX_CRB_PEG_NET_0 + 0x3c),
3393                                     qla82xx_rd_32(ha,
3394                                             QLA82XX_CRB_PEG_NET_1 + 0x3c),
3395                                     qla82xx_rd_32(ha,
3396                                             QLA82XX_CRB_PEG_NET_2 + 0x3c),
3397                                     qla82xx_rd_32(ha,
3398                                             QLA82XX_CRB_PEG_NET_3 + 0x3c),
3399                                     qla82xx_rd_32(ha,
3400                                             QLA82XX_CRB_PEG_NET_4 + 0x3c));
3401                                 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3402                                         ql_log(ql_log_warn, vha, 0xb052,
3403                                             "Firmware aborted with "
3404                                             "error code 0x00006700. Device is "
3405                                             "being reset.\n");
3406                                 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3407                                         set_bit(ISP_UNRECOVERABLE,
3408                                             &vha->dpc_flags);
3409                                 } else {
3410                                         ql_log(ql_log_info, vha, 0x6006,
3411                                             "Detect abort  needed.\n");
3412                                         set_bit(ISP_ABORT_NEEDED,
3413                                             &vha->dpc_flags);
3414                                 }
3415                                 ha->flags.isp82xx_fw_hung = 1;
3416                                 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3417                                 qla82xx_clear_pending_mbx(vha);
3418                         }
3419                 }
3420         }
3421 }
3422
3423 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3424 {
3425         int rval;
3426         rval = qla82xx_device_state_handler(vha);
3427         return rval;
3428 }
3429
3430 void
3431 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3432 {
3433         struct qla_hw_data *ha = vha->hw;
3434         uint32_t dev_state;
3435
3436         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3437         if (dev_state == QLA8XXX_DEV_READY) {
3438                 ql_log(ql_log_info, vha, 0xb02f,
3439                     "HW State: NEED RESET\n");
3440                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3441                         QLA8XXX_DEV_NEED_RESET);
3442                 ha->flags.nic_core_reset_owner = 1;
3443                 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3444                     "reset_owner is 0x%x\n", ha->portnum);
3445         } else
3446                 ql_log(ql_log_info, vha, 0xb031,
3447                     "Device state is 0x%x = %s.\n",
3448                     dev_state,
3449                     dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3450 }
3451
3452 /*
3453  *  qla82xx_abort_isp
3454  *      Resets ISP and aborts all outstanding commands.
3455  *
3456  * Input:
3457  *      ha           = adapter block pointer.
3458  *
3459  * Returns:
3460  *      0 = success
3461  */
3462 int
3463 qla82xx_abort_isp(scsi_qla_host_t *vha)
3464 {
3465         int rval;
3466         struct qla_hw_data *ha = vha->hw;
3467
3468         if (vha->device_flags & DFLG_DEV_FAILED) {
3469                 ql_log(ql_log_warn, vha, 0x8024,
3470                     "Device in failed state, exiting.\n");
3471                 return QLA_SUCCESS;
3472         }
3473         ha->flags.nic_core_reset_hdlr_active = 1;
3474
3475         qla82xx_idc_lock(ha);
3476         qla82xx_set_reset_owner(vha);
3477         qla82xx_idc_unlock(ha);
3478
3479         rval = qla82xx_device_state_handler(vha);
3480
3481         qla82xx_idc_lock(ha);
3482         qla82xx_clear_rst_ready(ha);
3483         qla82xx_idc_unlock(ha);
3484
3485         if (rval == QLA_SUCCESS) {
3486                 ha->flags.isp82xx_fw_hung = 0;
3487                 ha->flags.nic_core_reset_hdlr_active = 0;
3488                 qla82xx_restart_isp(vha);
3489         }
3490
3491         if (rval) {
3492                 vha->flags.online = 1;
3493                 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3494                         if (ha->isp_abort_cnt == 0) {
3495                                 ql_log(ql_log_warn, vha, 0x8027,
3496                                     "ISP error recover failed - board "
3497                                     "disabled.\n");
3498                                 /*
3499                                  * The next call disables the board
3500                                  * completely.
3501                                  */
3502                                 ha->isp_ops->reset_adapter(vha);
3503                                 vha->flags.online = 0;
3504                                 clear_bit(ISP_ABORT_RETRY,
3505                                     &vha->dpc_flags);
3506                                 rval = QLA_SUCCESS;
3507                         } else { /* schedule another ISP abort */
3508                                 ha->isp_abort_cnt--;
3509                                 ql_log(ql_log_warn, vha, 0x8036,
3510                                     "ISP abort - retry remaining %d.\n",
3511                                     ha->isp_abort_cnt);
3512                                 rval = QLA_FUNCTION_FAILED;
3513                         }
3514                 } else {
3515                         ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3516                         ql_dbg(ql_dbg_taskm, vha, 0x8029,
3517                             "ISP error recovery - retrying (%d) more times.\n",
3518                             ha->isp_abort_cnt);
3519                         set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3520                         rval = QLA_FUNCTION_FAILED;
3521                 }
3522         }
3523         return rval;
3524 }
3525
3526 /*
3527  *  qla82xx_fcoe_ctx_reset
3528  *      Perform a quick reset and aborts all outstanding commands.
3529  *      This will only perform an FCoE context reset and avoids a full blown
3530  *      chip reset.
3531  *
3532  * Input:
3533  *      ha = adapter block pointer.
3534  *      is_reset_path = flag for identifying the reset path.
3535  *
3536  * Returns:
3537  *      0 = success
3538  */
3539 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3540 {
3541         int rval = QLA_FUNCTION_FAILED;
3542
3543         if (vha->flags.online) {
3544                 /* Abort all outstanding commands, so as to be requeued later */
3545                 qla2x00_abort_isp_cleanup(vha);
3546         }
3547
3548         /* Stop currently executing firmware.
3549          * This will destroy existing FCoE context at the F/W end.
3550          */
3551         qla2x00_try_to_stop_firmware(vha);
3552
3553         /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3554         rval = qla82xx_restart_isp(vha);
3555
3556         return rval;
3557 }
3558
3559 /*
3560  * qla2x00_wait_for_fcoe_ctx_reset
3561  *    Wait till the FCoE context is reset.
3562  *
3563  * Note:
3564  *    Does context switching here.
3565  *    Release SPIN_LOCK (if any) before calling this routine.
3566  *
3567  * Return:
3568  *    Success (fcoe_ctx reset is done) : 0
3569  *    Failed  (fcoe_ctx reset not completed within max loop timout ) : 1
3570  */
3571 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3572 {
3573         int status = QLA_FUNCTION_FAILED;
3574         unsigned long wait_reset;
3575
3576         wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3577         while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3578             test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3579             && time_before(jiffies, wait_reset)) {
3580
3581                 set_current_state(TASK_UNINTERRUPTIBLE);
3582                 schedule_timeout(HZ);
3583
3584                 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3585                     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3586                         status = QLA_SUCCESS;
3587                         break;
3588                 }
3589         }
3590         ql_dbg(ql_dbg_p3p, vha, 0xb027,
3591                "%s: status=%d.\n", __func__, status);
3592
3593         return status;
3594 }
3595
3596 void
3597 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3598 {
3599         int i;
3600         unsigned long flags;
3601         struct qla_hw_data *ha = vha->hw;
3602
3603         /* Check if 82XX firmware is alive or not
3604          * We may have arrived here from NEED_RESET
3605          * detection only
3606          */
3607         if (!ha->flags.isp82xx_fw_hung) {
3608                 for (i = 0; i < 2; i++) {
3609                         msleep(1000);
3610                         if (qla82xx_check_fw_alive(vha)) {
3611                                 ha->flags.isp82xx_fw_hung = 1;
3612                                 qla82xx_clear_pending_mbx(vha);
3613                                 break;
3614                         }
3615                 }
3616         }
3617         ql_dbg(ql_dbg_init, vha, 0x00b0,
3618             "Entered %s fw_hung=%d.\n",
3619             __func__, ha->flags.isp82xx_fw_hung);
3620
3621         /* Abort all commands gracefully if fw NOT hung */
3622         if (!ha->flags.isp82xx_fw_hung) {
3623                 int cnt, que;
3624                 srb_t *sp;
3625                 struct req_que *req;
3626
3627                 spin_lock_irqsave(&ha->hardware_lock, flags);
3628                 for (que = 0; que < ha->max_req_queues; que++) {
3629                         req = ha->req_q_map[que];
3630                         if (!req)
3631                                 continue;
3632                         for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3633                                 sp = req->outstanding_cmds[cnt];
3634                                 if (sp) {
3635                                         if (!sp->u.scmd.ctx ||
3636                                             (sp->flags & SRB_FCP_CMND_DMA_VALID)) {
3637                                                 spin_unlock_irqrestore(
3638                                                     &ha->hardware_lock, flags);
3639                                                 if (ha->isp_ops->abort_command(sp)) {
3640                                                         ql_log(ql_log_info, vha,
3641                                                             0x00b1,
3642                                                             "mbx abort failed.\n");
3643                                                 } else {
3644                                                         ql_log(ql_log_info, vha,
3645                                                             0x00b2,
3646                                                             "mbx abort success.\n");
3647                                                 }
3648                                                 spin_lock_irqsave(&ha->hardware_lock, flags);
3649                                         }
3650                                 }
3651                         }
3652                 }
3653                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3654
3655                 /* Wait for pending cmds (physical and virtual) to complete */
3656                 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3657                     WAIT_HOST) == QLA_SUCCESS) {
3658                         ql_dbg(ql_dbg_init, vha, 0x00b3,
3659                             "Done wait for "
3660                             "pending commands.\n");
3661                 }
3662         }
3663 }
3664
3665 /* Minidump related functions */
3666 static int
3667 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3668         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3669 {
3670         struct qla_hw_data *ha = vha->hw;
3671         struct qla82xx_md_entry_crb *crb_entry;
3672         uint32_t read_value, opcode, poll_time;
3673         uint32_t addr, index, crb_addr;
3674         unsigned long wtime;
3675         struct qla82xx_md_template_hdr *tmplt_hdr;
3676         uint32_t rval = QLA_SUCCESS;
3677         int i;
3678
3679         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3680         crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3681         crb_addr = crb_entry->addr;
3682
3683         for (i = 0; i < crb_entry->op_count; i++) {
3684                 opcode = crb_entry->crb_ctrl.opcode;
3685                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3686                         qla82xx_md_rw_32(ha, crb_addr,
3687                             crb_entry->value_1, 1);
3688                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
3689                 }
3690
3691                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3692                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3693                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3694                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
3695                 }
3696
3697                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3698                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3699                         read_value &= crb_entry->value_2;
3700                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
3701                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
3702                                 read_value |= crb_entry->value_3;
3703                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3704                         }
3705                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3706                 }
3707
3708                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3709                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3710                         read_value |= crb_entry->value_3;
3711                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3712                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
3713                 }
3714
3715                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3716                         poll_time = crb_entry->crb_strd.poll_timeout;
3717                         wtime = jiffies + poll_time;
3718                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3719
3720                         do {
3721                                 if ((read_value & crb_entry->value_2)
3722                                     == crb_entry->value_1)
3723                                         break;
3724                                 else if (time_after_eq(jiffies, wtime)) {
3725                                         /* capturing dump failed */
3726                                         rval = QLA_FUNCTION_FAILED;
3727                                         break;
3728                                 } else
3729                                         read_value = qla82xx_md_rw_32(ha,
3730                                             crb_addr, 0, 0);
3731                         } while (1);
3732                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3733                 }
3734
3735                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3736                         if (crb_entry->crb_strd.state_index_a) {
3737                                 index = crb_entry->crb_strd.state_index_a;
3738                                 addr = tmplt_hdr->saved_state_array[index];
3739                         } else
3740                                 addr = crb_addr;
3741
3742                         read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3743                         index = crb_entry->crb_ctrl.state_index_v;
3744                         tmplt_hdr->saved_state_array[index] = read_value;
3745                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3746                 }
3747
3748                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3749                         if (crb_entry->crb_strd.state_index_a) {
3750                                 index = crb_entry->crb_strd.state_index_a;
3751                                 addr = tmplt_hdr->saved_state_array[index];
3752                         } else
3753                                 addr = crb_addr;
3754
3755                         if (crb_entry->crb_ctrl.state_index_v) {
3756                                 index = crb_entry->crb_ctrl.state_index_v;
3757                                 read_value =
3758                                     tmplt_hdr->saved_state_array[index];
3759                         } else
3760                                 read_value = crb_entry->value_1;
3761
3762                         qla82xx_md_rw_32(ha, addr, read_value, 1);
3763                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3764                 }
3765
3766                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3767                         index = crb_entry->crb_ctrl.state_index_v;
3768                         read_value = tmplt_hdr->saved_state_array[index];
3769                         read_value <<= crb_entry->crb_ctrl.shl;
3770                         read_value >>= crb_entry->crb_ctrl.shr;
3771                         if (crb_entry->value_2)
3772                                 read_value &= crb_entry->value_2;
3773                         read_value |= crb_entry->value_3;
3774                         read_value += crb_entry->value_1;
3775                         tmplt_hdr->saved_state_array[index] = read_value;
3776                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3777                 }
3778                 crb_addr += crb_entry->crb_strd.addr_stride;
3779         }
3780         return rval;
3781 }
3782
3783 static void
3784 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3785         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3786 {
3787         struct qla_hw_data *ha = vha->hw;
3788         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3789         struct qla82xx_md_entry_rdocm *ocm_hdr;
3790         uint32_t *data_ptr = *d_ptr;
3791
3792         ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3793         r_addr = ocm_hdr->read_addr;
3794         r_stride = ocm_hdr->read_addr_stride;
3795         loop_cnt = ocm_hdr->op_count;
3796
3797         for (i = 0; i < loop_cnt; i++) {
3798                 r_value = RD_REG_DWORD((void __iomem *)
3799                     (r_addr + ha->nx_pcibase));
3800                 *data_ptr++ = cpu_to_le32(r_value);
3801                 r_addr += r_stride;
3802         }
3803         *d_ptr = data_ptr;
3804 }
3805
3806 static void
3807 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3808         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3809 {
3810         struct qla_hw_data *ha = vha->hw;
3811         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3812         struct qla82xx_md_entry_mux *mux_hdr;
3813         uint32_t *data_ptr = *d_ptr;
3814
3815         mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3816         r_addr = mux_hdr->read_addr;
3817         s_addr = mux_hdr->select_addr;
3818         s_stride = mux_hdr->select_value_stride;
3819         s_value = mux_hdr->select_value;
3820         loop_cnt = mux_hdr->op_count;
3821
3822         for (i = 0; i < loop_cnt; i++) {
3823                 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3824                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3825                 *data_ptr++ = cpu_to_le32(s_value);
3826                 *data_ptr++ = cpu_to_le32(r_value);
3827                 s_value += s_stride;
3828         }
3829         *d_ptr = data_ptr;
3830 }
3831
3832 static void
3833 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3834         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3835 {
3836         struct qla_hw_data *ha = vha->hw;
3837         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3838         struct qla82xx_md_entry_crb *crb_hdr;
3839         uint32_t *data_ptr = *d_ptr;
3840
3841         crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3842         r_addr = crb_hdr->addr;
3843         r_stride = crb_hdr->crb_strd.addr_stride;
3844         loop_cnt = crb_hdr->op_count;
3845
3846         for (i = 0; i < loop_cnt; i++) {
3847                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3848                 *data_ptr++ = cpu_to_le32(r_addr);
3849                 *data_ptr++ = cpu_to_le32(r_value);
3850                 r_addr += r_stride;
3851         }
3852         *d_ptr = data_ptr;
3853 }
3854
3855 static int
3856 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3857         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3858 {
3859         struct qla_hw_data *ha = vha->hw;
3860         uint32_t addr, r_addr, c_addr, t_r_addr;
3861         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3862         unsigned long p_wait, w_time, p_mask;
3863         uint32_t c_value_w, c_value_r;
3864         struct qla82xx_md_entry_cache *cache_hdr;
3865         int rval = QLA_FUNCTION_FAILED;
3866         uint32_t *data_ptr = *d_ptr;
3867
3868         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3869         loop_count = cache_hdr->op_count;
3870         r_addr = cache_hdr->read_addr;
3871         c_addr = cache_hdr->control_addr;
3872         c_value_w = cache_hdr->cache_ctrl.write_value;
3873
3874         t_r_addr = cache_hdr->tag_reg_addr;
3875         t_value = cache_hdr->addr_ctrl.init_tag_value;
3876         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3877         p_wait = cache_hdr->cache_ctrl.poll_wait;
3878         p_mask = cache_hdr->cache_ctrl.poll_mask;
3879
3880         for (i = 0; i < loop_count; i++) {
3881                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3882                 if (c_value_w)
3883                         qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3884
3885                 if (p_mask) {
3886                         w_time = jiffies + p_wait;
3887                         do {
3888                                 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3889                                 if ((c_value_r & p_mask) == 0)
3890                                         break;
3891                                 else if (time_after_eq(jiffies, w_time)) {
3892                                         /* capturing dump failed */
3893                                         ql_dbg(ql_dbg_p3p, vha, 0xb032,
3894                                             "c_value_r: 0x%x, poll_mask: 0x%lx, "
3895                                             "w_time: 0x%lx\n",
3896                                             c_value_r, p_mask, w_time);
3897                                         return rval;
3898                                 }
3899                         } while (1);
3900                 }
3901
3902                 addr = r_addr;
3903                 for (k = 0; k < r_cnt; k++) {
3904                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3905                         *data_ptr++ = cpu_to_le32(r_value);
3906                         addr += cache_hdr->read_ctrl.read_addr_stride;
3907                 }
3908                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3909         }
3910         *d_ptr = data_ptr;
3911         return QLA_SUCCESS;
3912 }
3913
3914 static void
3915 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3916         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3917 {
3918         struct qla_hw_data *ha = vha->hw;
3919         uint32_t addr, r_addr, c_addr, t_r_addr;
3920         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3921         uint32_t c_value_w;
3922         struct qla82xx_md_entry_cache *cache_hdr;
3923         uint32_t *data_ptr = *d_ptr;
3924
3925         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3926         loop_count = cache_hdr->op_count;
3927         r_addr = cache_hdr->read_addr;
3928         c_addr = cache_hdr->control_addr;
3929         c_value_w = cache_hdr->cache_ctrl.write_value;
3930
3931         t_r_addr = cache_hdr->tag_reg_addr;
3932         t_value = cache_hdr->addr_ctrl.init_tag_value;
3933         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3934
3935         for (i = 0; i < loop_count; i++) {
3936                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3937                 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3938                 addr = r_addr;
3939                 for (k = 0; k < r_cnt; k++) {
3940                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3941                         *data_ptr++ = cpu_to_le32(r_value);
3942                         addr += cache_hdr->read_ctrl.read_addr_stride;
3943                 }
3944                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3945         }
3946         *d_ptr = data_ptr;
3947 }
3948
3949 static void
3950 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3951         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3952 {
3953         struct qla_hw_data *ha = vha->hw;
3954         uint32_t s_addr, r_addr;
3955         uint32_t r_stride, r_value, r_cnt, qid = 0;
3956         uint32_t i, k, loop_cnt;
3957         struct qla82xx_md_entry_queue *q_hdr;
3958         uint32_t *data_ptr = *d_ptr;
3959
3960         q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3961         s_addr = q_hdr->select_addr;
3962         r_cnt = q_hdr->rd_strd.read_addr_cnt;
3963         r_stride = q_hdr->rd_strd.read_addr_stride;
3964         loop_cnt = q_hdr->op_count;
3965
3966         for (i = 0; i < loop_cnt; i++) {
3967                 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3968                 r_addr = q_hdr->read_addr;
3969                 for (k = 0; k < r_cnt; k++) {
3970                         r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3971                         *data_ptr++ = cpu_to_le32(r_value);
3972                         r_addr += r_stride;
3973                 }
3974                 qid += q_hdr->q_strd.queue_id_stride;
3975         }
3976         *d_ptr = data_ptr;
3977 }
3978
3979 static void
3980 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3981         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3982 {
3983         struct qla_hw_data *ha = vha->hw;
3984         uint32_t r_addr, r_value;
3985         uint32_t i, loop_cnt;
3986         struct qla82xx_md_entry_rdrom *rom_hdr;
3987         uint32_t *data_ptr = *d_ptr;
3988
3989         rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
3990         r_addr = rom_hdr->read_addr;
3991         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
3992
3993         for (i = 0; i < loop_cnt; i++) {
3994                 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
3995                     (r_addr & 0xFFFF0000), 1);
3996                 r_value = qla82xx_md_rw_32(ha,
3997                     MD_DIRECT_ROM_READ_BASE +
3998                     (r_addr & 0x0000FFFF), 0, 0);
3999                 *data_ptr++ = cpu_to_le32(r_value);
4000                 r_addr += sizeof(uint32_t);
4001         }
4002         *d_ptr = data_ptr;
4003 }
4004
4005 static int
4006 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4007         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4008 {
4009         struct qla_hw_data *ha = vha->hw;
4010         uint32_t r_addr, r_value, r_data;
4011         uint32_t i, j, loop_cnt;
4012         struct qla82xx_md_entry_rdmem *m_hdr;
4013         unsigned long flags;
4014         int rval = QLA_FUNCTION_FAILED;
4015         uint32_t *data_ptr = *d_ptr;
4016
4017         m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4018         r_addr = m_hdr->read_addr;
4019         loop_cnt = m_hdr->read_data_size/16;
4020
4021         if (r_addr & 0xf) {
4022                 ql_log(ql_log_warn, vha, 0xb033,
4023                     "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4024                 return rval;
4025         }
4026
4027         if (m_hdr->read_data_size % 16) {
4028                 ql_log(ql_log_warn, vha, 0xb034,
4029                     "Read data[0x%x] not multiple of 16 bytes\n",
4030                     m_hdr->read_data_size);
4031                 return rval;
4032         }
4033
4034         ql_dbg(ql_dbg_p3p, vha, 0xb035,
4035             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4036             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4037
4038         write_lock_irqsave(&ha->hw_lock, flags);
4039         for (i = 0; i < loop_cnt; i++) {
4040                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4041                 r_value = 0;
4042                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4043                 r_value = MIU_TA_CTL_ENABLE;
4044                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4045                 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4046                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4047
4048                 for (j = 0; j < MAX_CTL_CHECK; j++) {
4049                         r_value = qla82xx_md_rw_32(ha,
4050                             MD_MIU_TEST_AGT_CTRL, 0, 0);
4051                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
4052                                 break;
4053                 }
4054
4055                 if (j >= MAX_CTL_CHECK) {
4056                         printk_ratelimited(KERN_ERR
4057                             "failed to read through agent\n");
4058                         write_unlock_irqrestore(&ha->hw_lock, flags);
4059                         return rval;
4060                 }
4061
4062                 for (j = 0; j < 4; j++) {
4063                         r_data = qla82xx_md_rw_32(ha,
4064                             MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4065                         *data_ptr++ = cpu_to_le32(r_data);
4066                 }
4067                 r_addr += 16;
4068         }
4069         write_unlock_irqrestore(&ha->hw_lock, flags);
4070         *d_ptr = data_ptr;
4071         return QLA_SUCCESS;
4072 }
4073
4074 static int
4075 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4076 {
4077         struct qla_hw_data *ha = vha->hw;
4078         uint64_t chksum = 0;
4079         uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4080         int count = ha->md_template_size/sizeof(uint32_t);
4081
4082         while (count-- > 0)
4083                 chksum += *d_ptr++;
4084         while (chksum >> 32)
4085                 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4086         return ~chksum;
4087 }
4088
4089 static void
4090 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4091         qla82xx_md_entry_hdr_t *entry_hdr, int index)
4092 {
4093         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4094         ql_dbg(ql_dbg_p3p, vha, 0xb036,
4095             "Skipping entry[%d]: "
4096             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4097             index, entry_hdr->entry_type,
4098             entry_hdr->d_ctrl.entry_capture_mask);
4099 }
4100
4101 int
4102 qla82xx_md_collect(scsi_qla_host_t *vha)
4103 {
4104         struct qla_hw_data *ha = vha->hw;
4105         int no_entry_hdr = 0;
4106         qla82xx_md_entry_hdr_t *entry_hdr;
4107         struct qla82xx_md_template_hdr *tmplt_hdr;
4108         uint32_t *data_ptr;
4109         uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4110         int i = 0, rval = QLA_FUNCTION_FAILED;
4111
4112         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4113         data_ptr = (uint32_t *)ha->md_dump;
4114
4115         if (ha->fw_dumped) {
4116                 ql_log(ql_log_warn, vha, 0xb037,
4117                     "Firmware has been previously dumped (%p) "
4118                     "-- ignoring request.\n", ha->fw_dump);
4119                 goto md_failed;
4120         }
4121
4122         ha->fw_dumped = 0;
4123
4124         if (!ha->md_tmplt_hdr || !ha->md_dump) {
4125                 ql_log(ql_log_warn, vha, 0xb038,
4126                     "Memory not allocated for minidump capture\n");
4127                 goto md_failed;
4128         }
4129
4130         if (ha->flags.isp82xx_no_md_cap) {
4131                 ql_log(ql_log_warn, vha, 0xb054,
4132                     "Forced reset from application, "
4133                     "ignore minidump capture\n");
4134                 ha->flags.isp82xx_no_md_cap = 0;
4135                 goto md_failed;
4136         }
4137
4138         if (qla82xx_validate_template_chksum(vha)) {
4139                 ql_log(ql_log_info, vha, 0xb039,
4140                     "Template checksum validation error\n");
4141                 goto md_failed;
4142         }
4143
4144         no_entry_hdr = tmplt_hdr->num_of_entries;
4145         ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4146             "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4147
4148         ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4149             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4150
4151         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4152
4153         /* Validate whether required debug level is set */
4154         if ((f_capture_mask & 0x3) != 0x3) {
4155                 ql_log(ql_log_warn, vha, 0xb03c,
4156                     "Minimum required capture mask[0x%x] level not set\n",
4157                     f_capture_mask);
4158                 goto md_failed;
4159         }
4160         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4161
4162         tmplt_hdr->driver_info[0] = vha->host_no;
4163         tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4164             (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4165             QLA_DRIVER_BETA_VER;
4166
4167         total_data_size = ha->md_dump_size;
4168
4169         ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4170             "Total minidump data_size 0x%x to be captured\n", total_data_size);
4171
4172         /* Check whether template obtained is valid */
4173         if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4174                 ql_log(ql_log_warn, vha, 0xb04e,
4175                     "Bad template header entry type: 0x%x obtained\n",
4176                     tmplt_hdr->entry_type);
4177                 goto md_failed;
4178         }
4179
4180         entry_hdr = (qla82xx_md_entry_hdr_t *) \
4181             (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4182
4183         /* Walk through the entry headers */
4184         for (i = 0; i < no_entry_hdr; i++) {
4185
4186                 if (data_collected > total_data_size) {
4187                         ql_log(ql_log_warn, vha, 0xb03e,
4188                             "More MiniDump data collected: [0x%x]\n",
4189                             data_collected);
4190                         goto md_failed;
4191                 }
4192
4193                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4194                     ql2xmdcapmask)) {
4195                         entry_hdr->d_ctrl.driver_flags |=
4196                             QLA82XX_DBG_SKIPPED_FLAG;
4197                         ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4198                             "Skipping entry[%d]: "
4199                             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4200                             i, entry_hdr->entry_type,
4201                             entry_hdr->d_ctrl.entry_capture_mask);
4202                         goto skip_nxt_entry;
4203                 }
4204
4205                 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4206                     "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4207                     "entry_type: 0x%x, captrue_mask: 0x%x\n",
4208                     __func__, i, data_ptr, entry_hdr,
4209                     entry_hdr->entry_type,
4210                     entry_hdr->d_ctrl.entry_capture_mask);
4211
4212                 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4213                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
4214                     data_collected, (ha->md_dump_size - data_collected));
4215
4216                 /* Decode the entry type and take
4217                  * required action to capture debug data */
4218                 switch (entry_hdr->entry_type) {
4219                 case QLA82XX_RDEND:
4220                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4221                         break;
4222                 case QLA82XX_CNTRL:
4223                         rval = qla82xx_minidump_process_control(vha,
4224                             entry_hdr, &data_ptr);
4225                         if (rval != QLA_SUCCESS) {
4226                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4227                                 goto md_failed;
4228                         }
4229                         break;
4230                 case QLA82XX_RDCRB:
4231                         qla82xx_minidump_process_rdcrb(vha,
4232                             entry_hdr, &data_ptr);
4233                         break;
4234                 case QLA82XX_RDMEM:
4235                         rval = qla82xx_minidump_process_rdmem(vha,
4236                             entry_hdr, &data_ptr);
4237                         if (rval != QLA_SUCCESS) {
4238                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4239                                 goto md_failed;
4240                         }
4241                         break;
4242                 case QLA82XX_BOARD:
4243                 case QLA82XX_RDROM:
4244                         qla82xx_minidump_process_rdrom(vha,
4245                             entry_hdr, &data_ptr);
4246                         break;
4247                 case QLA82XX_L2DTG:
4248                 case QLA82XX_L2ITG:
4249                 case QLA82XX_L2DAT:
4250                 case QLA82XX_L2INS:
4251                         rval = qla82xx_minidump_process_l2tag(vha,
4252                             entry_hdr, &data_ptr);
4253                         if (rval != QLA_SUCCESS) {
4254                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4255                                 goto md_failed;
4256                         }
4257                         break;
4258                 case QLA82XX_L1DAT:
4259                 case QLA82XX_L1INS:
4260                         qla82xx_minidump_process_l1cache(vha,
4261                             entry_hdr, &data_ptr);
4262                         break;
4263                 case QLA82XX_RDOCM:
4264                         qla82xx_minidump_process_rdocm(vha,
4265                             entry_hdr, &data_ptr);
4266                         break;
4267                 case QLA82XX_RDMUX:
4268                         qla82xx_minidump_process_rdmux(vha,
4269                             entry_hdr, &data_ptr);
4270                         break;
4271                 case QLA82XX_QUEUE:
4272                         qla82xx_minidump_process_queue(vha,
4273                             entry_hdr, &data_ptr);
4274                         break;
4275                 case QLA82XX_RDNOP:
4276                 default:
4277                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4278                         break;
4279                 }
4280
4281                 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4282                     "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4283
4284                 data_collected = (uint8_t *)data_ptr -
4285                     (uint8_t *)ha->md_dump;
4286 skip_nxt_entry:
4287                 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4288                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4289         }
4290
4291         if (data_collected != total_data_size) {
4292                 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4293                     "MiniDump data mismatch: Data collected: [0x%x],"
4294                     "total_data_size:[0x%x]\n",
4295                     data_collected, total_data_size);
4296                 goto md_failed;
4297         }
4298
4299         ql_log(ql_log_info, vha, 0xb044,
4300             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4301             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4302         ha->fw_dumped = 1;
4303         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4304
4305 md_failed:
4306         return rval;
4307 }
4308
4309 int
4310 qla82xx_md_alloc(scsi_qla_host_t *vha)
4311 {
4312         struct qla_hw_data *ha = vha->hw;
4313         int i, k;
4314         struct qla82xx_md_template_hdr *tmplt_hdr;
4315
4316         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4317
4318         if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4319                 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4320                 ql_log(ql_log_info, vha, 0xb045,
4321                     "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4322                     ql2xmdcapmask);
4323         }
4324
4325         for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4326                 if (i & ql2xmdcapmask)
4327                         ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4328         }
4329
4330         if (ha->md_dump) {
4331                 ql_log(ql_log_warn, vha, 0xb046,
4332                     "Firmware dump previously allocated.\n");
4333                 return 1;
4334         }
4335
4336         ha->md_dump = vmalloc(ha->md_dump_size);
4337         if (ha->md_dump == NULL) {
4338                 ql_log(ql_log_warn, vha, 0xb047,
4339                     "Unable to allocate memory for Minidump size "
4340                     "(0x%x).\n", ha->md_dump_size);
4341                 return 1;
4342         }
4343         return 0;
4344 }
4345
4346 void
4347 qla82xx_md_free(scsi_qla_host_t *vha)
4348 {
4349         struct qla_hw_data *ha = vha->hw;
4350
4351         /* Release the template header allocated */
4352         if (ha->md_tmplt_hdr) {
4353                 ql_log(ql_log_info, vha, 0xb048,
4354                     "Free MiniDump template: %p, size (%d KB)\n",
4355                     ha->md_tmplt_hdr, ha->md_template_size / 1024);
4356                 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4357                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4358                 ha->md_tmplt_hdr = NULL;
4359         }
4360
4361         /* Release the template data buffer allocated */
4362         if (ha->md_dump) {
4363                 ql_log(ql_log_info, vha, 0xb049,
4364                     "Free MiniDump memory: %p, size (%d KB)\n",
4365                     ha->md_dump, ha->md_dump_size / 1024);
4366                 vfree(ha->md_dump);
4367                 ha->md_dump_size = 0;
4368                 ha->md_dump = NULL;
4369         }
4370 }
4371
4372 void
4373 qla82xx_md_prep(scsi_qla_host_t *vha)
4374 {
4375         struct qla_hw_data *ha = vha->hw;
4376         int rval;
4377
4378         /* Get Minidump template size */
4379         rval = qla82xx_md_get_template_size(vha);
4380         if (rval == QLA_SUCCESS) {
4381                 ql_log(ql_log_info, vha, 0xb04a,
4382                     "MiniDump Template size obtained (%d KB)\n",
4383                     ha->md_template_size / 1024);
4384
4385                 /* Get Minidump template */
4386                 rval = qla82xx_md_get_template(vha);
4387                 if (rval == QLA_SUCCESS) {
4388                         ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4389                             "MiniDump Template obtained\n");
4390
4391                         /* Allocate memory for minidump */
4392                         rval = qla82xx_md_alloc(vha);
4393                         if (rval == QLA_SUCCESS)
4394                                 ql_log(ql_log_info, vha, 0xb04c,
4395                                     "MiniDump memory allocated (%d KB)\n",
4396                                     ha->md_dump_size / 1024);
4397                         else {
4398                                 ql_log(ql_log_info, vha, 0xb04d,
4399                                     "Free MiniDump template: %p, size: (%d KB)\n",
4400                                     ha->md_tmplt_hdr,
4401                                     ha->md_template_size / 1024);
4402                                 dma_free_coherent(&ha->pdev->dev,
4403                                     ha->md_template_size,
4404                                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4405                                 ha->md_tmplt_hdr = NULL;
4406                         }
4407
4408                 }
4409         }
4410 }
4411
4412 int
4413 qla82xx_beacon_on(struct scsi_qla_host *vha)
4414 {
4415
4416         int rval;
4417         struct qla_hw_data *ha = vha->hw;
4418         qla82xx_idc_lock(ha);
4419         rval = qla82xx_mbx_beacon_ctl(vha, 1);
4420
4421         if (rval) {
4422                 ql_log(ql_log_warn, vha, 0xb050,
4423                     "mbx set led config failed in %s\n", __func__);
4424                 goto exit;
4425         }
4426         ha->beacon_blink_led = 1;
4427 exit:
4428         qla82xx_idc_unlock(ha);
4429         return rval;
4430 }
4431
4432 int
4433 qla82xx_beacon_off(struct scsi_qla_host *vha)
4434 {
4435
4436         int rval;
4437         struct qla_hw_data *ha = vha->hw;
4438         qla82xx_idc_lock(ha);
4439         rval = qla82xx_mbx_beacon_ctl(vha, 0);
4440
4441         if (rval) {
4442                 ql_log(ql_log_warn, vha, 0xb051,
4443                     "mbx set led config failed in %s\n", __func__);
4444                 goto exit;
4445         }
4446         ha->beacon_blink_led = 0;
4447 exit:
4448         qla82xx_idc_unlock(ha);
4449         return rval;
4450 }