drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48 /**
  49  * read_main_config_table - read the configure table and save it.
  50  * @pm8001_ha: our hba card information
  51  */
  52 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  53 {
  54         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  55
  56         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
  57                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
  58         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
  59                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
  60         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
  61                 pm8001_mr32(address, MAIN_FW_REVISION);
  62         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
  63                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
  64         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
  65                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
  66         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
  67                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
  68         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
  69                 pm8001_mr32(address, MAIN_GST_OFFSET);
  70         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
  71                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  72         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
  73                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  74
  75         /* read Error Dump Offset and Length */
  76         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
  77                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  78         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
  79                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  80         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
  81                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  82         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
  83                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  84
  85         /* read GPIO LED settings from the configuration table */
  86         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
  87                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
  88
  89         /* read analog Setting offset from the configuration table */
  90         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
  91                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  92
  93         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
  94                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
  95         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
  96                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
  97 }
  98
  99 /**
 100  * read_general_status_table - read the general status table and save it.
 101  * @pm8001_ha: our hba card information
 102  */
 103 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 104 {
 105         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 106         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 107                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 108         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 109                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 110         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 111                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 112         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 113                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 114         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 115                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 116         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 117                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 118         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 119                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 120         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 121                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 122         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 123                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 124         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 125                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 126         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 127                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 128         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 129                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 130         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 131                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 132         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 133                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 134 }
 135 /**
 136  * read_phy_attr_table - read the phy attribute table and save it.
 137  * @pm8001_ha: our hba card information
 138  */
 139 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 140 {
 141         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 142         pm8001_ha->phy_attr_table.phystart1_16[0] =
 143                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 144         pm8001_ha->phy_attr_table.phystart1_16[1] =
 145                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 146         pm8001_ha->phy_attr_table.phystart1_16[2] =
 147                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 148         pm8001_ha->phy_attr_table.phystart1_16[3] =
 149                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 150         pm8001_ha->phy_attr_table.phystart1_16[4] =
 151                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 152         pm8001_ha->phy_attr_table.phystart1_16[5] =
 153                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 154         pm8001_ha->phy_attr_table.phystart1_16[6] =
 155                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 156         pm8001_ha->phy_attr_table.phystart1_16[7] =
 157                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 158         pm8001_ha->phy_attr_table.phystart1_16[8] =
 159                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 160         pm8001_ha->phy_attr_table.phystart1_16[9] =
 161                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 162         pm8001_ha->phy_attr_table.phystart1_16[10] =
 163                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 164         pm8001_ha->phy_attr_table.phystart1_16[11] =
 165                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 166         pm8001_ha->phy_attr_table.phystart1_16[12] =
 167                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 168         pm8001_ha->phy_attr_table.phystart1_16[13] =
 169                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 170         pm8001_ha->phy_attr_table.phystart1_16[14] =
 171                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 172         pm8001_ha->phy_attr_table.phystart1_16[15] =
 173                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 174
 175         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 176                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 177         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 178                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 179         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 180                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 181         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 182                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 183         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 184                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 185         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 186                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 187         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 188                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 189         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 190                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 191         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 192                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 193         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 194                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 195         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 196                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 197         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 198                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 199         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 200                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 201         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 202                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 203         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 204                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 205         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 206                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 207
 208 }
 209
 210 /**
 211  * read_inbnd_queue_table - read the inbound queue table and save it.
 212  * @pm8001_ha: our hba card information
 213  */
 214 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 215 {
 216         int i;
 217         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 218         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 219                 u32 offset = i * 0x20;
 220                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 221                         get_pci_bar_index(pm8001_mr32(address,
 222                                 (offset + IB_PIPCI_BAR)));
 223                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 224                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 225         }
 226 }
 227
 228 /**
 229  * read_outbnd_queue_table - read the outbound queue table and save it.
 230  * @pm8001_ha: our hba card information
 231  */
 232 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 233 {
 234         int i;
 235         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 236         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 237                 u32 offset = i * 0x24;
 238                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 239                         get_pci_bar_index(pm8001_mr32(address,
 240                                 (offset + OB_CIPCI_BAR)));
 241                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 242                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 243         }
 244 }
 245
 246 /**
 247  * init_default_table_values - init the default table.
 248  * @pm8001_ha: our hba card information
 249  */
 250 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 251 {
 252         int i;
 253         u32 offsetib, offsetob;
 254         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 255         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 256
 257         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 258                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 259         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 260                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 261         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 262                                                         PM8001_EVENT_LOG_SIZE;
 263         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 264         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 265                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 266         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 267                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 268         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 269                                                         PM8001_EVENT_LOG_SIZE;
 270         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 272
 273         /* Disable end to end CRC checking */
 274         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 275
 276         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 277                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 278                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 279                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 280                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 281                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 282                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 283                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 284                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 285                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 286                         pm8001_ha->memoryMap.region[IB + i].total_len;
 287                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 288                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 289                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 290                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 291                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 292                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 293                 offsetib = i * 0x20;
 294                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 295                         get_pci_bar_index(pm8001_mr32(addressib,
 296                                 (offsetib + 0x14)));
 297                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 298                         pm8001_mr32(addressib, (offsetib + 0x18));
 299                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 300                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 301         }
 302         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 303                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 304                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 305                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 306                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 307                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 308                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 309                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 310                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 311                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 312                         pm8001_ha->memoryMap.region[OB + i].total_len;
 313                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 314                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 315                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 316                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 317                 /* interrupt vector based on oq */
 318                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 319                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 320                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 321                 offsetob = i * 0x24;
 322                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 323                         get_pci_bar_index(pm8001_mr32(addressob,
 324                         offsetob + 0x14));
 325                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 326                         pm8001_mr32(addressob, (offsetob + 0x18));
 327                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 328                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 329         }
 330 }
 331
 332 /**
 333  * update_main_config_table - update the main default table to the HBA.
 334  * @pm8001_ha: our hba card information
 335  */
 336 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 337 {
 338         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 339         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 340                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 341         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 342                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 343         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 344                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 345         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 346                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 347         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 348                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 349         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 350                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 351         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 352                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 353         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 354                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 355         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 356                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 357         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 358                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 359         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 360                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 361
 362         /* SPCv specific */
 363         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 364         /* Set GPIOLED to 0x2 for LED indicator */
 365         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 366         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 367                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 368
 369         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 370                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 371         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 372                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 373 }
 374
 375 /**
 376  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 377  * @pm8001_ha: our hba card information
 378  */
 379 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 380                                          int number)
 381 {
 382         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 383         u16 offset = number * 0x20;
 384         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 385                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 386         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 387                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 388         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 389                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 390         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 391                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 392         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 393                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 394 }
 395
 396 /**
 397  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 398  * @pm8001_ha: our hba card information
 399  */
 400 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 401                                                  int number)
 402 {
 403         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 404         u16 offset = number * 0x24;
 405         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 406                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 407         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 408                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 409         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 410                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 411         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 412                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 413         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 414                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 415         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 416                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 417 }
 418
 419 /**
 420  * mpi_init_check - check firmware initialization status.
 421  * @pm8001_ha: our hba card information
 422  */
 423 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 424 {
 425         u32 max_wait_count;
 426         u32 value;
 427         u32 gst_len_mpistate;
 428
 429         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 430         table is updated */
 431         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 432         /* wait until Inbound DoorBell Clear Register toggled */
 433         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 434                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 435         } else {
 436                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 437         }
 438         do {
 439                 udelay(1);
 440                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 441                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 442         } while ((value != 0) && (--max_wait_count));
 443
 444         if (!max_wait_count)
 445                 return -1;
 446         /* check the MPI-State for initialization upto 100ms*/
 447         max_wait_count = 100 * 1000;/* 100 msec */
 448         do {
 449                 udelay(1);
 450                 gst_len_mpistate =
 451                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 452                                         GST_GSTLEN_MPIS_OFFSET);
 453         } while ((GST_MPI_STATE_INIT !=
 454                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 455         if (!max_wait_count)
 456                 return -1;
 457
 458         /* check MPI Initialization error */
 459         gst_len_mpistate = gst_len_mpistate >> 16;
 460         if (0x0000 != gst_len_mpistate)
 461                 return -1;
 462
 463         return 0;
 464 }
 465
 466 /**
 467  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 468  * @pm8001_ha: our hba card information
 469  */
 470 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 471 {
 472         u32 value;
 473         u32 max_wait_count;
 474         u32 max_wait_time;
 475         int ret = 0;
 476
 477         /* reset / PCIe ready */
 478         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 479         do {
 480                 udelay(1);
 481                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 482         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 483
 484         /* check ila status */
 485         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 486         do {
 487                 udelay(1);
 488                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 489         } while (((value & SCRATCH_PAD_ILA_READY) !=
 490                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 491         if (!max_wait_count)
 492                 ret = -1;
 493         else {
 494                 PM8001_MSG_DBG(pm8001_ha,
 495                         pm8001_printk(" ila ready status in %d millisec\n",
 496                                 (max_wait_time - max_wait_count)));
 497         }
 498
 499         /* check RAAE status */
 500         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 501         do {
 502                 udelay(1);
 503                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 504         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 505                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 506         if (!max_wait_count)
 507                 ret = -1;
 508         else {
 509                 PM8001_MSG_DBG(pm8001_ha,
 510                         pm8001_printk(" raae ready status in %d millisec\n",
 511                                         (max_wait_time - max_wait_count)));
 512         }
 513
 514         /* check iop0 status */
 515         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 516         do {
 517                 udelay(1);
 518                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 519         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 520                         (--max_wait_count));
 521         if (!max_wait_count)
 522                 ret = -1;
 523         else {
 524                 PM8001_MSG_DBG(pm8001_ha,
 525                         pm8001_printk(" iop0 ready status in %d millisec\n",
 526                                 (max_wait_time - max_wait_count)));
 527         }
 528
 529         /* check iop1 status only for 16 port controllers */
 530         if ((pm8001_ha->chip_id != chip_8008) &&
 531                         (pm8001_ha->chip_id != chip_8009)) {
 532                 /* 200 milli sec */
 533                 max_wait_time = max_wait_count = 200 * 1000;
 534                 do {
 535                         udelay(1);
 536                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 537                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 538                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 539                 if (!max_wait_count)
 540                         ret = -1;
 541                 else {
 542                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 543                                 "iop1 ready status in %d millisec\n",
 544                                 (max_wait_time - max_wait_count)));
 545                 }
 546         }
 547
 548         return ret;
 549 }
 550
 551 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 552 {
 553         void __iomem *base_addr;
 554         u32     value;
 555         u32     offset;
 556         u32     pcibar;
 557         u32     pcilogic;
 558
 559         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 560         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 561
 562         PM8001_INIT_DBG(pm8001_ha,
 563                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 564                                 offset, value));
 565         pcilogic = (value & 0xFC000000) >> 26;
 566         pcibar = get_pci_bar_index(pcilogic);
 567         PM8001_INIT_DBG(pm8001_ha,
 568                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 569         pm8001_ha->main_cfg_tbl_addr = base_addr =
 570                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 571         pm8001_ha->general_stat_tbl_addr =
 572                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 573                                         0xFFFFFF);
 574         pm8001_ha->inbnd_q_tbl_addr =
 575                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 576                                         0xFFFFFF);
 577         pm8001_ha->outbnd_q_tbl_addr =
 578                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 579                                         0xFFFFFF);
 580         pm8001_ha->ivt_tbl_addr =
 581                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 582                                         0xFFFFFF);
 583         pm8001_ha->pspa_q_tbl_addr =
 584                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 585                                         0xFFFFFF);
 586
 587         PM8001_INIT_DBG(pm8001_ha,
 588                         pm8001_printk("GST OFFSET 0x%x\n",
 589                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 590         PM8001_INIT_DBG(pm8001_ha,
 591                         pm8001_printk("INBND OFFSET 0x%x\n",
 592                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 593         PM8001_INIT_DBG(pm8001_ha,
 594                         pm8001_printk("OBND OFFSET 0x%x\n",
 595                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 596         PM8001_INIT_DBG(pm8001_ha,
 597                         pm8001_printk("IVT OFFSET 0x%x\n",
 598                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 599         PM8001_INIT_DBG(pm8001_ha,
 600                         pm8001_printk("PSPA OFFSET 0x%x\n",
 601                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 602         PM8001_INIT_DBG(pm8001_ha,
 603                         pm8001_printk("addr - main cfg %p general status %p\n",
 604                         pm8001_ha->main_cfg_tbl_addr,
 605                         pm8001_ha->general_stat_tbl_addr));
 606         PM8001_INIT_DBG(pm8001_ha,
 607                         pm8001_printk("addr - inbnd %p obnd %p\n",
 608                         pm8001_ha->inbnd_q_tbl_addr,
 609                         pm8001_ha->outbnd_q_tbl_addr));
 610         PM8001_INIT_DBG(pm8001_ha,
 611                         pm8001_printk("addr - pspa %p ivt %p\n",
 612                         pm8001_ha->pspa_q_tbl_addr,
 613                         pm8001_ha->ivt_tbl_addr));
 614 }
 615
 616 /**
 617  * pm80xx_set_thermal_config - support the thermal configuration
 618  * @pm8001_ha: our hba card information.
 619  */
 620 int
 621 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 622 {
 623         struct set_ctrl_cfg_req payload;
 624         struct inbound_queue_table *circularQ;
 625         int rc;
 626         u32 tag;
 627         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 628
 629         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 630         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 631         if (rc)
 632                 return -1;
 633
 634         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 635         payload.tag = cpu_to_le32(tag);
 636         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
 637                         (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
 638         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
 639
 640         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 641         return rc;
 642
 643 }
 644
 645 /**
 646 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 647 * Timer configuration page
 648 * @pm8001_ha: our hba card information.
 649 */
 650 static int
 651 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 652 {
 653         struct set_ctrl_cfg_req payload;
 654         struct inbound_queue_table *circularQ;
 655         SASProtocolTimerConfig_t SASConfigPage;
 656         int rc;
 657         u32 tag;
 658         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 659
 660         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 661         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 662
 663         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 664
 665         if (rc)
 666                 return -1;
 667
 668         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 669         payload.tag = cpu_to_le32(tag);
 670
 671         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 672         SASConfigPage.MST_MSI         =  3 << 15;
 673         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 674         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 675                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 676         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 677
 678         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 679                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 680
 681
 682         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 683                                                 SAS_OPNRJT_RTRY_INTVL;
 684         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 685                                                 | SAS_COPNRJT_RTRY_TMO;
 686         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 687                                                 | SAS_COPNRJT_RTRY_THR;
 688         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 689
 690         PM8001_INIT_DBG(pm8001_ha,
 691                         pm8001_printk("SASConfigPage.pageCode "
 692                         "0x%08x\n", SASConfigPage.pageCode));
 693         PM8001_INIT_DBG(pm8001_ha,
 694                         pm8001_printk("SASConfigPage.MST_MSI "
 695                         " 0x%08x\n", SASConfigPage.MST_MSI));
 696         PM8001_INIT_DBG(pm8001_ha,
 697                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 698                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 699         PM8001_INIT_DBG(pm8001_ha,
 700                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 701                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 702         PM8001_INIT_DBG(pm8001_ha,
 703                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 704                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 705         PM8001_INIT_DBG(pm8001_ha,
 706                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 707                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 708         PM8001_INIT_DBG(pm8001_ha,
 709                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 710                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 711         PM8001_INIT_DBG(pm8001_ha,
 712                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 713                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 714         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 715                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 716
 717         memcpy(&payload.cfg_pg, &SASConfigPage,
 718                          sizeof(SASProtocolTimerConfig_t));
 719
 720         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 721
 722         return rc;
 723 }
 724
 725 /**
 726  * pm80xx_get_encrypt_info - Check for encryption
 727  * @pm8001_ha: our hba card information.
 728  */
 729 static int
 730 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 731 {
 732         u32 scratch3_value;
 733         int ret;
 734
 735         /* Read encryption status from SCRATCH PAD 3 */
 736         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 737
 738         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 739                                         SCRATCH_PAD3_ENC_READY) {
 740                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 741                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 742                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 743                                                 SCRATCH_PAD3_SMF_ENABLED)
 744                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 745                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 746                                                 SCRATCH_PAD3_SMA_ENABLED)
 747                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 748                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 749                                                 SCRATCH_PAD3_SMB_ENABLED)
 750                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 751                 pm8001_ha->encrypt_info.status = 0;
 752                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 753                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
 754                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
 755                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 756                         pm8001_ha->encrypt_info.sec_mode,
 757                         pm8001_ha->encrypt_info.status));
 758                 ret = 0;
 759         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
 760                                         SCRATCH_PAD3_ENC_DISABLED) {
 761                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 762                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
 763                         scratch3_value));
 764                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
 765                 pm8001_ha->encrypt_info.cipher_mode = 0;
 766                 pm8001_ha->encrypt_info.sec_mode = 0;
 767                 return 0;
 768         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 769                                 SCRATCH_PAD3_ENC_DIS_ERR) {
 770                 pm8001_ha->encrypt_info.status =
 771                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
 772                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 773                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 774                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 775                                         SCRATCH_PAD3_SMF_ENABLED)
 776                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 777                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 778                                         SCRATCH_PAD3_SMA_ENABLED)
 779                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 780                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 781                                         SCRATCH_PAD3_SMB_ENABLED)
 782                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 783                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 784                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
 785                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
 786                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 787                         pm8001_ha->encrypt_info.sec_mode,
 788                         pm8001_ha->encrypt_info.status));
 789                 ret = -1;
 790         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 791                                  SCRATCH_PAD3_ENC_ENA_ERR) {
 792
 793                 pm8001_ha->encrypt_info.status =
 794                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
 795                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 796                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 797                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 798                                         SCRATCH_PAD3_SMF_ENABLED)
 799                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 800                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 801                                         SCRATCH_PAD3_SMA_ENABLED)
 802                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 803                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 804                                         SCRATCH_PAD3_SMB_ENABLED)
 805                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 806
 807                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 808                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
 809                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
 810                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 811                         pm8001_ha->encrypt_info.sec_mode,
 812                         pm8001_ha->encrypt_info.status));
 813                 ret = -1;
 814         }
 815         return ret;
 816 }
 817
 818 /**
 819  * pm80xx_encrypt_update - update flash with encryption informtion
 820  * @pm8001_ha: our hba card information.
 821  */
 822 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
 823 {
 824         struct kek_mgmt_req payload;
 825         struct inbound_queue_table *circularQ;
 826         int rc;
 827         u32 tag;
 828         u32 opc = OPC_INB_KEK_MANAGEMENT;
 829
 830         memset(&payload, 0, sizeof(struct kek_mgmt_req));
 831         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 832         if (rc)
 833                 return -1;
 834
 835         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 836         payload.tag = cpu_to_le32(tag);
 837         /* Currently only one key is used. New KEK index is 1.
 838          * Current KEK index is 1. Store KEK to NVRAM is 1.
 839          */
 840         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
 841                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
 842
 843         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 844
 845         return rc;
 846 }
 847
 848 /**
 849  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 850  * @pm8001_ha: our hba card information
 851  */
 852 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
 853 {
 854         int ret;
 855         u8 i = 0;
 856
 857         /* check the firmware status */
 858         if (-1 == check_fw_ready(pm8001_ha)) {
 859                 PM8001_FAIL_DBG(pm8001_ha,
 860                         pm8001_printk("Firmware is not ready!\n"));
 861                 return -EBUSY;
 862         }
 863
 864         /* Initialize pci space address eg: mpi offset */
 865         init_pci_device_addresses(pm8001_ha);
 866         init_default_table_values(pm8001_ha);
 867         read_main_config_table(pm8001_ha);
 868         read_general_status_table(pm8001_ha);
 869         read_inbnd_queue_table(pm8001_ha);
 870         read_outbnd_queue_table(pm8001_ha);
 871         read_phy_attr_table(pm8001_ha);
 872
 873         /* update main config table ,inbound table and outbound table */
 874         update_main_config_table(pm8001_ha);
 875         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
 876                 update_inbnd_queue_table(pm8001_ha, i);
 877         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
 878                 update_outbnd_queue_table(pm8001_ha, i);
 879
 880         /* notify firmware update finished and check initialization status */
 881         if (0 == mpi_init_check(pm8001_ha)) {
 882                 PM8001_INIT_DBG(pm8001_ha,
 883                         pm8001_printk("MPI initialize successful!\n"));
 884         } else
 885                 return -EBUSY;
 886
 887         /* send SAS protocol timer configuration page to FW */
 888         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
 889
 890         /* Check for encryption */
 891         if (pm8001_ha->chip->encrypt) {
 892                 PM8001_INIT_DBG(pm8001_ha,
 893                         pm8001_printk("Checking for encryption\n"));
 894                 ret = pm80xx_get_encrypt_info(pm8001_ha);
 895                 if (ret == -1) {
 896                         PM8001_INIT_DBG(pm8001_ha,
 897                                 pm8001_printk("Encryption error !!\n"));
 898                         if (pm8001_ha->encrypt_info.status == 0x81) {
 899                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 900                                         "Encryption enabled with error."
 901                                         "Saving encryption key to flash\n"));
 902                                 pm80xx_encrypt_update(pm8001_ha);
 903                         }
 904                 }
 905         }
 906         return 0;
 907 }
 908
 909 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 910 {
 911         u32 max_wait_count;
 912         u32 value;
 913         u32 gst_len_mpistate;
 914         init_pci_device_addresses(pm8001_ha);
 915         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 916         table is stop */
 917         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
 918
 919         /* wait until Inbound DoorBell Clear Register toggled */
 920         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 921                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 922         } else {
 923                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 924         }
 925         do {
 926                 udelay(1);
 927                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 928                 value &= SPCv_MSGU_CFG_TABLE_RESET;
 929         } while ((value != 0) && (--max_wait_count));
 930
 931         if (!max_wait_count) {
 932                 PM8001_FAIL_DBG(pm8001_ha,
 933                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
 934                 return -1;
 935         }
 936
 937         /* check the MPI-State for termination in progress */
 938         /* wait until Inbound DoorBell Clear Register toggled */
 939         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
 940         do {
 941                 udelay(1);
 942                 gst_len_mpistate =
 943                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 944                         GST_GSTLEN_MPIS_OFFSET);
 945                 if (GST_MPI_STATE_UNINIT ==
 946                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 947                         break;
 948         } while (--max_wait_count);
 949         if (!max_wait_count) {
 950                 PM8001_FAIL_DBG(pm8001_ha,
 951                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 952                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 953                 return -1;
 954         }
 955
 956         return 0;
 957 }
 958
 959 /**
 960  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 961  * the FW register status to the originated status.
 962  * @pm8001_ha: our hba card information
 963  */
 964
 965 static int
 966 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 967 {
 968         u32 regval;
 969         u32 bootloader_state;
 970         u32 ibutton0, ibutton1;
 971
 972         /* Check if MPI is in ready state to reset */
 973         if (mpi_uninit_check(pm8001_ha) != 0) {
 974                 PM8001_FAIL_DBG(pm8001_ha,
 975                         pm8001_printk("MPI state is not ready\n"));
 976                 return -1;
 977         }
 978
 979         /* checked for reset register normal state; 0x0 */
 980         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
 981         PM8001_INIT_DBG(pm8001_ha,
 982                 pm8001_printk("reset register before write : 0x%x\n", regval));
 983
 984         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
 985         mdelay(500);
 986
 987         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
 988         PM8001_INIT_DBG(pm8001_ha,
 989         pm8001_printk("reset register after write 0x%x\n", regval));
 990
 991         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
 992                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
 993                 PM8001_MSG_DBG(pm8001_ha,
 994                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
 995                                         regval));
 996         } else {
 997                 PM8001_MSG_DBG(pm8001_ha,
 998                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
 999                                         regval));
1000
1001                 /* check bootloader is successfully executed or in HDA mode */
1002                 bootloader_state =
1003                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1004                         SCRATCH_PAD1_BOOTSTATE_MASK;
1005
1006                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1007                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1008                                 "Bootloader state - HDA mode SEEPROM\n"));
1009                 } else if (bootloader_state ==
1010                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1011                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1012                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1013                 } else if (bootloader_state ==
1014                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1015                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1016                                 "Bootloader state - HDA mode soft reset\n"));
1017                 } else if (bootloader_state ==
1018                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1019                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1020                                 "Bootloader state-HDA mode critical error\n"));
1021                 }
1022                 return -EBUSY;
1023         }
1024
1025         /* check the firmware status after reset */
1026         if (-1 == check_fw_ready(pm8001_ha)) {
1027                 PM8001_FAIL_DBG(pm8001_ha,
1028                         pm8001_printk("Firmware is not ready!\n"));
1029                 /* check iButton feature support for motherboard controller */
1030                 if (pm8001_ha->pdev->subsystem_vendor !=
1031                         PCI_VENDOR_ID_ADAPTEC2 &&
1032                         pm8001_ha->pdev->subsystem_vendor != 0) {
1033                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1034                                         MSGU_HOST_SCRATCH_PAD_6);
1035                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1036                                         MSGU_HOST_SCRATCH_PAD_7);
1037                         if (!ibutton0 && !ibutton1) {
1038                                 PM8001_FAIL_DBG(pm8001_ha,
1039                                         pm8001_printk("iButton Feature is"
1040                                         " not Available!!!\n"));
1041                                 return -EBUSY;
1042                         }
1043                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1044                                 PM8001_FAIL_DBG(pm8001_ha,
1045                                         pm8001_printk("CRC Check for iButton"
1046                                         " Feature Failed!!!\n"));
1047                                 return -EBUSY;
1048                         }
1049                 }
1050         }
1051         PM8001_INIT_DBG(pm8001_ha,
1052                 pm8001_printk("SPCv soft reset Complete\n"));
1053         return 0;
1054 }
1055
1056 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1057 {
1058          u32 i;
1059
1060         PM8001_INIT_DBG(pm8001_ha,
1061                 pm8001_printk("chip reset start\n"));
1062
1063         /* do SPCv chip reset. */
1064         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1065         PM8001_INIT_DBG(pm8001_ha,
1066                 pm8001_printk("SPC soft reset Complete\n"));
1067
1068         /* Check this ..whether delay is required or no */
1069         /* delay 10 usec */
1070         udelay(10);
1071
1072         /* wait for 20 msec until the firmware gets reloaded */
1073         i = 20;
1074         do {
1075                 mdelay(1);
1076         } while ((--i) != 0);
1077
1078         PM8001_INIT_DBG(pm8001_ha,
1079                 pm8001_printk("chip reset finished\n"));
1080 }
1081
1082 /**
1083  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1084  * @pm8001_ha: our hba card information
1085  */
1086 static void
1087 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1088 {
1089         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1090         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1091 }
1092
1093 /**
1094  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1095  * @pm8001_ha: our hba card information
1096  */
1097 static void
1098 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1099 {
1100         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1101 }
1102
1103 /**
1104  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1105  * @pm8001_ha: our hba card information
1106  */
1107 static void
1108 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1109 {
1110 #ifdef PM8001_USE_MSIX
1111         u32 mask;
1112         mask = (u32)(1 << vec);
1113
1114         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1115         return;
1116 #endif
1117         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1118
1119 }
1120
1121 /**
1122  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1123  * @pm8001_ha: our hba card information
1124  */
1125 static void
1126 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1127 {
1128 #ifdef PM8001_USE_MSIX
1129         u32 mask;
1130         if (vec == 0xFF)
1131                 mask = 0xFFFFFFFF;
1132         else
1133                 mask = (u32)(1 << vec);
1134         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1135         return;
1136 #endif
1137         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1138 }
1139
1140 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1141                 struct pm8001_device *pm8001_ha_dev)
1142 {
1143         int res;
1144         u32 ccb_tag;
1145         struct pm8001_ccb_info *ccb;
1146         struct sas_task *task = NULL;
1147         struct task_abort_req task_abort;
1148         struct inbound_queue_table *circularQ;
1149         u32 opc = OPC_INB_SATA_ABORT;
1150         int ret;
1151
1152         if (!pm8001_ha_dev) {
1153                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1154                 return;
1155         }
1156
1157         task = sas_alloc_slow_task(GFP_ATOMIC);
1158
1159         if (!task) {
1160                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1161                                                 "allocate task\n"));
1162                 return;
1163         }
1164
1165         task->task_done = pm8001_task_done;
1166
1167         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1168         if (res)
1169                 return;
1170
1171         ccb = &pm8001_ha->ccb_info[ccb_tag];
1172         ccb->device = pm8001_ha_dev;
1173         ccb->ccb_tag = ccb_tag;
1174         ccb->task = task;
1175
1176         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1177
1178         memset(&task_abort, 0, sizeof(task_abort));
1179         task_abort.abort_all = cpu_to_le32(1);
1180         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1181         task_abort.tag = cpu_to_le32(ccb_tag);
1182
1183         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1184
1185 }
1186
1187 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1188                 struct pm8001_device *pm8001_ha_dev)
1189 {
1190         struct sata_start_req sata_cmd;
1191         int res;
1192         u32 ccb_tag;
1193         struct pm8001_ccb_info *ccb;
1194         struct sas_task *task = NULL;
1195         struct host_to_dev_fis fis;
1196         struct domain_device *dev;
1197         struct inbound_queue_table *circularQ;
1198         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1199
1200         task = sas_alloc_slow_task(GFP_ATOMIC);
1201
1202         if (!task) {
1203                 PM8001_FAIL_DBG(pm8001_ha,
1204                         pm8001_printk("cannot allocate task !!!\n"));
1205                 return;
1206         }
1207         task->task_done = pm8001_task_done;
1208
1209         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1210         if (res) {
1211                 PM8001_FAIL_DBG(pm8001_ha,
1212                         pm8001_printk("cannot allocate tag !!!\n"));
1213                 return;
1214         }
1215
1216         /* allocate domain device by ourselves as libsas
1217          * is not going to provide any
1218         */
1219         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1220         if (!dev) {
1221                 PM8001_FAIL_DBG(pm8001_ha,
1222                         pm8001_printk("Domain device cannot be allocated\n"));
1223                 sas_free_task(task);
1224                 return;
1225         } else {
1226                 task->dev = dev;
1227                 task->dev->lldd_dev = pm8001_ha_dev;
1228         }
1229
1230         ccb = &pm8001_ha->ccb_info[ccb_tag];
1231         ccb->device = pm8001_ha_dev;
1232         ccb->ccb_tag = ccb_tag;
1233         ccb->task = task;
1234         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1235         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1236
1237         memset(&sata_cmd, 0, sizeof(sata_cmd));
1238         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1239
1240         /* construct read log FIS */
1241         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1242         fis.fis_type = 0x27;
1243         fis.flags = 0x80;
1244         fis.command = ATA_CMD_READ_LOG_EXT;
1245         fis.lbal = 0x10;
1246         fis.sector_count = 0x1;
1247
1248         sata_cmd.tag = cpu_to_le32(ccb_tag);
1249         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1250         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1251         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1252
1253         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1254
1255 }
1256
1257 /**
1258  * mpi_ssp_completion- process the event that FW response to the SSP request.
1259  * @pm8001_ha: our hba card information
1260  * @piomb: the message contents of this outbound message.
1261  *
1262  * When FW has completed a ssp request for example a IO request, after it has
1263  * filled the SG data with the data, it will trigger this event represent
1264  * that he has finished the job,please check the coresponding buffer.
1265  * So we will tell the caller who maybe waiting the result to tell upper layer
1266  * that the task has been finished.
1267  */
1268 static void
1269 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1270 {
1271         struct sas_task *t;
1272         struct pm8001_ccb_info *ccb;
1273         unsigned long flags;
1274         u32 status;
1275         u32 param;
1276         u32 tag;
1277         struct ssp_completion_resp *psspPayload;
1278         struct task_status_struct *ts;
1279         struct ssp_response_iu *iu;
1280         struct pm8001_device *pm8001_dev;
1281         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1282         status = le32_to_cpu(psspPayload->status);
1283         tag = le32_to_cpu(psspPayload->tag);
1284         ccb = &pm8001_ha->ccb_info[tag];
1285         if ((status == IO_ABORTED) && ccb->open_retry) {
1286                 /* Being completed by another */
1287                 ccb->open_retry = 0;
1288                 return;
1289         }
1290         pm8001_dev = ccb->device;
1291         param = le32_to_cpu(psspPayload->param);
1292         t = ccb->task;
1293
1294         if (status && status != IO_UNDERFLOW)
1295                 PM8001_FAIL_DBG(pm8001_ha,
1296                         pm8001_printk("sas IO status 0x%x\n", status));
1297         if (unlikely(!t || !t->lldd_task || !t->dev))
1298                 return;
1299         ts = &t->task_status;
1300         /* Print sas address of IO failed device */
1301         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1302                 (status != IO_UNDERFLOW))
1303                 PM8001_FAIL_DBG(pm8001_ha,
1304                         pm8001_printk("SAS Address of IO Failure Drive"
1305                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1306
1307         switch (status) {
1308         case IO_SUCCESS:
1309                 PM8001_IO_DBG(pm8001_ha,
1310                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1311                                 param));
1312                 if (param == 0) {
1313                         ts->resp = SAS_TASK_COMPLETE;
1314                         ts->stat = SAM_STAT_GOOD;
1315                 } else {
1316                         ts->resp = SAS_TASK_COMPLETE;
1317                         ts->stat = SAS_PROTO_RESPONSE;
1318                         ts->residual = param;
1319                         iu = &psspPayload->ssp_resp_iu;
1320                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1321                 }
1322                 if (pm8001_dev)
1323                         pm8001_dev->running_req--;
1324                 break;
1325         case IO_ABORTED:
1326                 PM8001_IO_DBG(pm8001_ha,
1327                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1328                 ts->resp = SAS_TASK_COMPLETE;
1329                 ts->stat = SAS_ABORTED_TASK;
1330                 break;
1331         case IO_UNDERFLOW:
1332                 /* SSP Completion with error */
1333                 PM8001_IO_DBG(pm8001_ha,
1334                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1335                                 param));
1336                 ts->resp = SAS_TASK_COMPLETE;
1337                 ts->stat = SAS_DATA_UNDERRUN;
1338                 ts->residual = param;
1339                 if (pm8001_dev)
1340                         pm8001_dev->running_req--;
1341                 break;
1342         case IO_NO_DEVICE:
1343                 PM8001_IO_DBG(pm8001_ha,
1344                         pm8001_printk("IO_NO_DEVICE\n"));
1345                 ts->resp = SAS_TASK_UNDELIVERED;
1346                 ts->stat = SAS_PHY_DOWN;
1347                 break;
1348         case IO_XFER_ERROR_BREAK:
1349                 PM8001_IO_DBG(pm8001_ha,
1350                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1351                 ts->resp = SAS_TASK_COMPLETE;
1352                 ts->stat = SAS_OPEN_REJECT;
1353                 /* Force the midlayer to retry */
1354                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1355                 break;
1356         case IO_XFER_ERROR_PHY_NOT_READY:
1357                 PM8001_IO_DBG(pm8001_ha,
1358                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1359                 ts->resp = SAS_TASK_COMPLETE;
1360                 ts->stat = SAS_OPEN_REJECT;
1361                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1362                 break;
1363         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1364                 PM8001_IO_DBG(pm8001_ha,
1365                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1366                 ts->resp = SAS_TASK_COMPLETE;
1367                 ts->stat = SAS_OPEN_REJECT;
1368                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1369                 break;
1370         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1371                 PM8001_IO_DBG(pm8001_ha,
1372                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1373                 ts->resp = SAS_TASK_COMPLETE;
1374                 ts->stat = SAS_OPEN_REJECT;
1375                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1376                 break;
1377         case IO_OPEN_CNX_ERROR_BREAK:
1378                 PM8001_IO_DBG(pm8001_ha,
1379                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1380                 ts->resp = SAS_TASK_COMPLETE;
1381                 ts->stat = SAS_OPEN_REJECT;
1382                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1383                 break;
1384         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1385         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1386         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1387         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1388         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1389         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1390                 PM8001_IO_DBG(pm8001_ha,
1391                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1392                 ts->resp = SAS_TASK_COMPLETE;
1393                 ts->stat = SAS_OPEN_REJECT;
1394                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1395                 if (!t->uldd_task)
1396                         pm8001_handle_event(pm8001_ha,
1397                                 pm8001_dev,
1398                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1399                 break;
1400         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1401                 PM8001_IO_DBG(pm8001_ha,
1402                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1403                 ts->resp = SAS_TASK_COMPLETE;
1404                 ts->stat = SAS_OPEN_REJECT;
1405                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1406                 break;
1407         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1408                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1409                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1410                 ts->resp = SAS_TASK_COMPLETE;
1411                 ts->stat = SAS_OPEN_REJECT;
1412                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1413                 break;
1414         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1415                 PM8001_IO_DBG(pm8001_ha,
1416                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1417                 ts->resp = SAS_TASK_UNDELIVERED;
1418                 ts->stat = SAS_OPEN_REJECT;
1419                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1420                 break;
1421         case IO_XFER_ERROR_NAK_RECEIVED:
1422                 PM8001_IO_DBG(pm8001_ha,
1423                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1424                 ts->resp = SAS_TASK_COMPLETE;
1425                 ts->stat = SAS_OPEN_REJECT;
1426                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1427                 break;
1428         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1429                 PM8001_IO_DBG(pm8001_ha,
1430                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1431                 ts->resp = SAS_TASK_COMPLETE;
1432                 ts->stat = SAS_NAK_R_ERR;
1433                 break;
1434         case IO_XFER_ERROR_DMA:
1435                 PM8001_IO_DBG(pm8001_ha,
1436                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1437                 ts->resp = SAS_TASK_COMPLETE;
1438                 ts->stat = SAS_OPEN_REJECT;
1439                 break;
1440         case IO_XFER_OPEN_RETRY_TIMEOUT:
1441                 PM8001_IO_DBG(pm8001_ha,
1442                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1443                 ts->resp = SAS_TASK_COMPLETE;
1444                 ts->stat = SAS_OPEN_REJECT;
1445                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1446                 break;
1447         case IO_XFER_ERROR_OFFSET_MISMATCH:
1448                 PM8001_IO_DBG(pm8001_ha,
1449                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1450                 ts->resp = SAS_TASK_COMPLETE;
1451                 ts->stat = SAS_OPEN_REJECT;
1452                 break;
1453         case IO_PORT_IN_RESET:
1454                 PM8001_IO_DBG(pm8001_ha,
1455                         pm8001_printk("IO_PORT_IN_RESET\n"));
1456                 ts->resp = SAS_TASK_COMPLETE;
1457                 ts->stat = SAS_OPEN_REJECT;
1458                 break;
1459         case IO_DS_NON_OPERATIONAL:
1460                 PM8001_IO_DBG(pm8001_ha,
1461                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1462                 ts->resp = SAS_TASK_COMPLETE;
1463                 ts->stat = SAS_OPEN_REJECT;
1464                 if (!t->uldd_task)
1465                         pm8001_handle_event(pm8001_ha,
1466                                 pm8001_dev,
1467                                 IO_DS_NON_OPERATIONAL);
1468                 break;
1469         case IO_DS_IN_RECOVERY:
1470                 PM8001_IO_DBG(pm8001_ha,
1471                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1472                 ts->resp = SAS_TASK_COMPLETE;
1473                 ts->stat = SAS_OPEN_REJECT;
1474                 break;
1475         case IO_TM_TAG_NOT_FOUND:
1476                 PM8001_IO_DBG(pm8001_ha,
1477                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1478                 ts->resp = SAS_TASK_COMPLETE;
1479                 ts->stat = SAS_OPEN_REJECT;
1480                 break;
1481         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1482                 PM8001_IO_DBG(pm8001_ha,
1483                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1484                 ts->resp = SAS_TASK_COMPLETE;
1485                 ts->stat = SAS_OPEN_REJECT;
1486                 break;
1487         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1488                 PM8001_IO_DBG(pm8001_ha,
1489                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1490                 ts->resp = SAS_TASK_COMPLETE;
1491                 ts->stat = SAS_OPEN_REJECT;
1492                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1493                 break;
1494         default:
1495                 PM8001_IO_DBG(pm8001_ha,
1496                         pm8001_printk("Unknown status 0x%x\n", status));
1497                 /* not allowed case. Therefore, return failed status */
1498                 ts->resp = SAS_TASK_COMPLETE;
1499                 ts->stat = SAS_OPEN_REJECT;
1500                 break;
1501         }
1502         PM8001_IO_DBG(pm8001_ha,
1503                 pm8001_printk("scsi_status = 0x%x\n ",
1504                 psspPayload->ssp_resp_iu.status));
1505         spin_lock_irqsave(&t->task_state_lock, flags);
1506         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1507         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1508         t->task_state_flags |= SAS_TASK_STATE_DONE;
1509         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1510                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1511                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1512                         "task 0x%p done with io_status 0x%x resp 0x%x "
1513                         "stat 0x%x but aborted by upper layer!\n",
1514                         t, status, ts->resp, ts->stat));
1515                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1516         } else {
1517                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1518                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1519                 mb();/* in order to force CPU ordering */
1520                 t->task_done(t);
1521         }
1522 }
1523
1524 /*See the comments for mpi_ssp_completion */
1525 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1526 {
1527         struct sas_task *t;
1528         unsigned long flags;
1529         struct task_status_struct *ts;
1530         struct pm8001_ccb_info *ccb;
1531         struct pm8001_device *pm8001_dev;
1532         struct ssp_event_resp *psspPayload =
1533                 (struct ssp_event_resp *)(piomb + 4);
1534         u32 event = le32_to_cpu(psspPayload->event);
1535         u32 tag = le32_to_cpu(psspPayload->tag);
1536         u32 port_id = le32_to_cpu(psspPayload->port_id);
1537
1538         ccb = &pm8001_ha->ccb_info[tag];
1539         t = ccb->task;
1540         pm8001_dev = ccb->device;
1541         if (event)
1542                 PM8001_FAIL_DBG(pm8001_ha,
1543                         pm8001_printk("sas IO status 0x%x\n", event));
1544         if (unlikely(!t || !t->lldd_task || !t->dev))
1545                 return;
1546         ts = &t->task_status;
1547         PM8001_IO_DBG(pm8001_ha,
1548                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1549                                 port_id, tag, event));
1550         switch (event) {
1551         case IO_OVERFLOW:
1552                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1553                 ts->resp = SAS_TASK_COMPLETE;
1554                 ts->stat = SAS_DATA_OVERRUN;
1555                 ts->residual = 0;
1556                 if (pm8001_dev)
1557                         pm8001_dev->running_req--;
1558                 break;
1559         case IO_XFER_ERROR_BREAK:
1560                 PM8001_IO_DBG(pm8001_ha,
1561                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1562                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1563                 return;
1564         case IO_XFER_ERROR_PHY_NOT_READY:
1565                 PM8001_IO_DBG(pm8001_ha,
1566                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1567                 ts->resp = SAS_TASK_COMPLETE;
1568                 ts->stat = SAS_OPEN_REJECT;
1569                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1570                 break;
1571         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1572                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1573                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1574                 ts->resp = SAS_TASK_COMPLETE;
1575                 ts->stat = SAS_OPEN_REJECT;
1576                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1577                 break;
1578         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1579                 PM8001_IO_DBG(pm8001_ha,
1580                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1581                 ts->resp = SAS_TASK_COMPLETE;
1582                 ts->stat = SAS_OPEN_REJECT;
1583                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1584                 break;
1585         case IO_OPEN_CNX_ERROR_BREAK:
1586                 PM8001_IO_DBG(pm8001_ha,
1587                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1588                 ts->resp = SAS_TASK_COMPLETE;
1589                 ts->stat = SAS_OPEN_REJECT;
1590                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1591                 break;
1592         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1593         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1594         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1595         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1596         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1597         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1598                 PM8001_IO_DBG(pm8001_ha,
1599                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1600                 ts->resp = SAS_TASK_COMPLETE;
1601                 ts->stat = SAS_OPEN_REJECT;
1602                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1603                 if (!t->uldd_task)
1604                         pm8001_handle_event(pm8001_ha,
1605                                 pm8001_dev,
1606                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1607                 break;
1608         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1609                 PM8001_IO_DBG(pm8001_ha,
1610                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1611                 ts->resp = SAS_TASK_COMPLETE;
1612                 ts->stat = SAS_OPEN_REJECT;
1613                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1614                 break;
1615         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1616                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1617                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1618                 ts->resp = SAS_TASK_COMPLETE;
1619                 ts->stat = SAS_OPEN_REJECT;
1620                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1621                 break;
1622         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1623                 PM8001_IO_DBG(pm8001_ha,
1624                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1625                 ts->resp = SAS_TASK_COMPLETE;
1626                 ts->stat = SAS_OPEN_REJECT;
1627                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1628                 break;
1629         case IO_XFER_ERROR_NAK_RECEIVED:
1630                 PM8001_IO_DBG(pm8001_ha,
1631                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1632                 ts->resp = SAS_TASK_COMPLETE;
1633                 ts->stat = SAS_OPEN_REJECT;
1634                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1635                 break;
1636         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1637                 PM8001_IO_DBG(pm8001_ha,
1638                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1639                 ts->resp = SAS_TASK_COMPLETE;
1640                 ts->stat = SAS_NAK_R_ERR;
1641                 break;
1642         case IO_XFER_OPEN_RETRY_TIMEOUT:
1643                 PM8001_IO_DBG(pm8001_ha,
1644                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1645                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1646                 return;
1647         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1648                 PM8001_IO_DBG(pm8001_ha,
1649                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1650                 ts->resp = SAS_TASK_COMPLETE;
1651                 ts->stat = SAS_DATA_OVERRUN;
1652                 break;
1653         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1654                 PM8001_IO_DBG(pm8001_ha,
1655                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1656                 ts->resp = SAS_TASK_COMPLETE;
1657                 ts->stat = SAS_DATA_OVERRUN;
1658                 break;
1659         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1660                 PM8001_IO_DBG(pm8001_ha,
1661                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1662                 ts->resp = SAS_TASK_COMPLETE;
1663                 ts->stat = SAS_DATA_OVERRUN;
1664                 break;
1665         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1666                 PM8001_IO_DBG(pm8001_ha,
1667                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1668                 ts->resp = SAS_TASK_COMPLETE;
1669                 ts->stat = SAS_DATA_OVERRUN;
1670                 break;
1671         case IO_XFER_ERROR_OFFSET_MISMATCH:
1672                 PM8001_IO_DBG(pm8001_ha,
1673                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1674                 ts->resp = SAS_TASK_COMPLETE;
1675                 ts->stat = SAS_DATA_OVERRUN;
1676                 break;
1677         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1678                 PM8001_IO_DBG(pm8001_ha,
1679                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1680                 ts->resp = SAS_TASK_COMPLETE;
1681                 ts->stat = SAS_DATA_OVERRUN;
1682                 break;
1683         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1684                 PM8001_IO_DBG(pm8001_ha,
1685                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1686                 /* TBC: used default set values */
1687                 ts->resp = SAS_TASK_COMPLETE;
1688                 ts->stat = SAS_DATA_OVERRUN;
1689                 break;
1690         case IO_XFER_CMD_FRAME_ISSUED:
1691                 PM8001_IO_DBG(pm8001_ha,
1692                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1693                 return;
1694         default:
1695                 PM8001_IO_DBG(pm8001_ha,
1696                         pm8001_printk("Unknown status 0x%x\n", event));
1697                 /* not allowed case. Therefore, return failed status */
1698                 ts->resp = SAS_TASK_COMPLETE;
1699                 ts->stat = SAS_DATA_OVERRUN;
1700                 break;
1701         }
1702         spin_lock_irqsave(&t->task_state_lock, flags);
1703         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1704         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1705         t->task_state_flags |= SAS_TASK_STATE_DONE;
1706         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1707                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1708                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1709                         "task 0x%p done with event 0x%x resp 0x%x "
1710                         "stat 0x%x but aborted by upper layer!\n",
1711                         t, event, ts->resp, ts->stat));
1712                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1713         } else {
1714                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1715                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1716                 mb();/* in order to force CPU ordering */
1717                 t->task_done(t);
1718         }
1719 }
1720
1721 /*See the comments for mpi_ssp_completion */
1722 static void
1723 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1724 {
1725         struct sas_task *t;
1726         struct pm8001_ccb_info *ccb;
1727         u32 param;
1728         u32 status;
1729         u32 tag;
1730         int i, j;
1731         u8 sata_addr_low[4];
1732         u32 temp_sata_addr_low, temp_sata_addr_hi;
1733         u8 sata_addr_hi[4];
1734         struct sata_completion_resp *psataPayload;
1735         struct task_status_struct *ts;
1736         struct ata_task_resp *resp ;
1737         u32 *sata_resp;
1738         struct pm8001_device *pm8001_dev;
1739         unsigned long flags;
1740
1741         psataPayload = (struct sata_completion_resp *)(piomb + 4);
1742         status = le32_to_cpu(psataPayload->status);
1743         tag = le32_to_cpu(psataPayload->tag);
1744
1745         if (!tag) {
1746                 PM8001_FAIL_DBG(pm8001_ha,
1747                         pm8001_printk("tag null\n"));
1748                 return;
1749         }
1750         ccb = &pm8001_ha->ccb_info[tag];
1751         param = le32_to_cpu(psataPayload->param);
1752         if (ccb) {
1753                 t = ccb->task;
1754                 pm8001_dev = ccb->device;
1755         } else {
1756                 PM8001_FAIL_DBG(pm8001_ha,
1757                         pm8001_printk("ccb null\n"));
1758                 return;
1759         }
1760
1761         if (t) {
1762                 if (t->dev && (t->dev->lldd_dev))
1763                         pm8001_dev = t->dev->lldd_dev;
1764         } else {
1765                 PM8001_FAIL_DBG(pm8001_ha,
1766                         pm8001_printk("task null\n"));
1767                 return;
1768         }
1769
1770         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1771                 && unlikely(!t || !t->lldd_task || !t->dev)) {
1772                 PM8001_FAIL_DBG(pm8001_ha,
1773                         pm8001_printk("task or dev null\n"));
1774                 return;
1775         }
1776
1777         ts = &t->task_status;
1778         if (!ts) {
1779                 PM8001_FAIL_DBG(pm8001_ha,
1780                         pm8001_printk("ts null\n"));
1781                 return;
1782         }
1783         /* Print sas address of IO failed device */
1784         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1785                 (status != IO_UNDERFLOW)) {
1786                 if (!((t->dev->parent) &&
1787                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
1788                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
1789                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
1790                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
1791                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
1792                         memcpy(&temp_sata_addr_low, sata_addr_low,
1793                                 sizeof(sata_addr_low));
1794                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
1795                                 sizeof(sata_addr_hi));
1796                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
1797                                                 |((temp_sata_addr_hi << 8) &
1798                                                 0xff0000) |
1799                                                 ((temp_sata_addr_hi >> 8)
1800                                                 & 0xff00) |
1801                                                 ((temp_sata_addr_hi << 24) &
1802                                                 0xff000000));
1803                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
1804                                                 & 0xff) |
1805                                                 ((temp_sata_addr_low << 8)
1806                                                 & 0xff0000) |
1807                                                 ((temp_sata_addr_low >> 8)
1808                                                 & 0xff00) |
1809                                                 ((temp_sata_addr_low << 24)
1810                                                 & 0xff000000)) +
1811                                                 pm8001_dev->attached_phy +
1812                                                 0x10);
1813                         PM8001_FAIL_DBG(pm8001_ha,
1814                                 pm8001_printk("SAS Address of IO Failure Drive:"
1815                                 "%08x%08x", temp_sata_addr_hi,
1816                                         temp_sata_addr_low));
1817
1818                 } else {
1819                         PM8001_FAIL_DBG(pm8001_ha,
1820                                 pm8001_printk("SAS Address of IO Failure Drive:"
1821                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
1822                 }
1823         }
1824         switch (status) {
1825         case IO_SUCCESS:
1826                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1827                 if (param == 0) {
1828                         ts->resp = SAS_TASK_COMPLETE;
1829                         ts->stat = SAM_STAT_GOOD;
1830                         /* check if response is for SEND READ LOG */
1831                         if (pm8001_dev &&
1832                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
1833                                 /* set new bit for abort_all */
1834                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
1835                                 /* clear bit for read log */
1836                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
1837                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
1838                                 /* Free the tag */
1839                                 pm8001_tag_free(pm8001_ha, tag);
1840                                 sas_free_task(t);
1841                                 return;
1842                         }
1843                 } else {
1844                         u8 len;
1845                         ts->resp = SAS_TASK_COMPLETE;
1846                         ts->stat = SAS_PROTO_RESPONSE;
1847                         ts->residual = param;
1848                         PM8001_IO_DBG(pm8001_ha,
1849                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1850                                 param));
1851                         sata_resp = &psataPayload->sata_resp[0];
1852                         resp = (struct ata_task_resp *)ts->buf;
1853                         if (t->ata_task.dma_xfer == 0 &&
1854                         t->data_dir == PCI_DMA_FROMDEVICE) {
1855                                 len = sizeof(struct pio_setup_fis);
1856                                 PM8001_IO_DBG(pm8001_ha,
1857                                 pm8001_printk("PIO read len = %d\n", len));
1858                         } else if (t->ata_task.use_ncq) {
1859                                 len = sizeof(struct set_dev_bits_fis);
1860                                 PM8001_IO_DBG(pm8001_ha,
1861                                         pm8001_printk("FPDMA len = %d\n", len));
1862                         } else {
1863                                 len = sizeof(struct dev_to_host_fis);
1864                                 PM8001_IO_DBG(pm8001_ha,
1865                                 pm8001_printk("other len = %d\n", len));
1866                         }
1867                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1868                                 resp->frame_len = len;
1869                                 memcpy(&resp->ending_fis[0], sata_resp, len);
1870                                 ts->buf_valid_size = sizeof(*resp);
1871                         } else
1872                                 PM8001_IO_DBG(pm8001_ha,
1873                                         pm8001_printk("response to large\n"));
1874                 }
1875                 if (pm8001_dev)
1876                         pm8001_dev->running_req--;
1877                 break;
1878         case IO_ABORTED:
1879                 PM8001_IO_DBG(pm8001_ha,
1880                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1881                 ts->resp = SAS_TASK_COMPLETE;
1882                 ts->stat = SAS_ABORTED_TASK;
1883                 if (pm8001_dev)
1884                         pm8001_dev->running_req--;
1885                 break;
1886                 /* following cases are to do cases */
1887         case IO_UNDERFLOW:
1888                 /* SATA Completion with error */
1889                 PM8001_IO_DBG(pm8001_ha,
1890                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1891                 ts->resp = SAS_TASK_COMPLETE;
1892                 ts->stat = SAS_DATA_UNDERRUN;
1893                 ts->residual = param;
1894                 if (pm8001_dev)
1895                         pm8001_dev->running_req--;
1896                 break;
1897         case IO_NO_DEVICE:
1898                 PM8001_IO_DBG(pm8001_ha,
1899                         pm8001_printk("IO_NO_DEVICE\n"));
1900                 ts->resp = SAS_TASK_UNDELIVERED;
1901                 ts->stat = SAS_PHY_DOWN;
1902                 break;
1903         case IO_XFER_ERROR_BREAK:
1904                 PM8001_IO_DBG(pm8001_ha,
1905                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1906                 ts->resp = SAS_TASK_COMPLETE;
1907                 ts->stat = SAS_INTERRUPTED;
1908                 break;
1909         case IO_XFER_ERROR_PHY_NOT_READY:
1910                 PM8001_IO_DBG(pm8001_ha,
1911                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1912                 ts->resp = SAS_TASK_COMPLETE;
1913                 ts->stat = SAS_OPEN_REJECT;
1914                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1915                 break;
1916         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1917                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1918                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1919                 ts->resp = SAS_TASK_COMPLETE;
1920                 ts->stat = SAS_OPEN_REJECT;
1921                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1922                 break;
1923         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1924                 PM8001_IO_DBG(pm8001_ha,
1925                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1926                 ts->resp = SAS_TASK_COMPLETE;
1927                 ts->stat = SAS_OPEN_REJECT;
1928                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1929                 break;
1930         case IO_OPEN_CNX_ERROR_BREAK:
1931                 PM8001_IO_DBG(pm8001_ha,
1932                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1933                 ts->resp = SAS_TASK_COMPLETE;
1934                 ts->stat = SAS_OPEN_REJECT;
1935                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1936                 break;
1937         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1938         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1939         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1940         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1941         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1942         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1943                 PM8001_IO_DBG(pm8001_ha,
1944                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1945                 ts->resp = SAS_TASK_COMPLETE;
1946                 ts->stat = SAS_DEV_NO_RESPONSE;
1947                 if (!t->uldd_task) {
1948                         pm8001_handle_event(pm8001_ha,
1949                                 pm8001_dev,
1950                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1951                         ts->resp = SAS_TASK_UNDELIVERED;
1952                         ts->stat = SAS_QUEUE_FULL;
1953                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1954                         mb();/*in order to force CPU ordering*/
1955                         spin_unlock_irq(&pm8001_ha->lock);
1956                         t->task_done(t);
1957                         spin_lock_irq(&pm8001_ha->lock);
1958                         return;
1959                 }
1960                 break;
1961         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1962                 PM8001_IO_DBG(pm8001_ha,
1963                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1964                 ts->resp = SAS_TASK_UNDELIVERED;
1965                 ts->stat = SAS_OPEN_REJECT;
1966                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1967                 if (!t->uldd_task) {
1968                         pm8001_handle_event(pm8001_ha,
1969                                 pm8001_dev,
1970                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1971                         ts->resp = SAS_TASK_UNDELIVERED;
1972                         ts->stat = SAS_QUEUE_FULL;
1973                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1974                         mb();/*ditto*/
1975                         spin_unlock_irq(&pm8001_ha->lock);
1976                         t->task_done(t);
1977                         spin_lock_irq(&pm8001_ha->lock);
1978                         return;
1979                 }
1980                 break;
1981         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1982                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1983                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1984                 ts->resp = SAS_TASK_COMPLETE;
1985                 ts->stat = SAS_OPEN_REJECT;
1986                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1987                 break;
1988         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1989                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1990                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1991                 ts->resp = SAS_TASK_COMPLETE;
1992                 ts->stat = SAS_DEV_NO_RESPONSE;
1993                 if (!t->uldd_task) {
1994                         pm8001_handle_event(pm8001_ha,
1995                                 pm8001_dev,
1996                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1997                         ts->resp = SAS_TASK_UNDELIVERED;
1998                         ts->stat = SAS_QUEUE_FULL;
1999                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2000                         mb();/* ditto*/
2001                         spin_unlock_irq(&pm8001_ha->lock);
2002                         t->task_done(t);
2003                         spin_lock_irq(&pm8001_ha->lock);
2004                         return;
2005                 }
2006                 break;
2007         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2008                 PM8001_IO_DBG(pm8001_ha,
2009                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2010                 ts->resp = SAS_TASK_COMPLETE;
2011                 ts->stat = SAS_OPEN_REJECT;
2012                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2013                 break;
2014         case IO_XFER_ERROR_NAK_RECEIVED:
2015                 PM8001_IO_DBG(pm8001_ha,
2016                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2017                 ts->resp = SAS_TASK_COMPLETE;
2018                 ts->stat = SAS_NAK_R_ERR;
2019                 break;
2020         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2021                 PM8001_IO_DBG(pm8001_ha,
2022                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2023                 ts->resp = SAS_TASK_COMPLETE;
2024                 ts->stat = SAS_NAK_R_ERR;
2025                 break;
2026         case IO_XFER_ERROR_DMA:
2027                 PM8001_IO_DBG(pm8001_ha,
2028                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2029                 ts->resp = SAS_TASK_COMPLETE;
2030                 ts->stat = SAS_ABORTED_TASK;
2031                 break;
2032         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2033                 PM8001_IO_DBG(pm8001_ha,
2034                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2035                 ts->resp = SAS_TASK_UNDELIVERED;
2036                 ts->stat = SAS_DEV_NO_RESPONSE;
2037                 break;
2038         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2039                 PM8001_IO_DBG(pm8001_ha,
2040                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2041                 ts->resp = SAS_TASK_COMPLETE;
2042                 ts->stat = SAS_DATA_UNDERRUN;
2043                 break;
2044         case IO_XFER_OPEN_RETRY_TIMEOUT:
2045                 PM8001_IO_DBG(pm8001_ha,
2046                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2047                 ts->resp = SAS_TASK_COMPLETE;
2048                 ts->stat = SAS_OPEN_TO;
2049                 break;
2050         case IO_PORT_IN_RESET:
2051                 PM8001_IO_DBG(pm8001_ha,
2052                         pm8001_printk("IO_PORT_IN_RESET\n"));
2053                 ts->resp = SAS_TASK_COMPLETE;
2054                 ts->stat = SAS_DEV_NO_RESPONSE;
2055                 break;
2056         case IO_DS_NON_OPERATIONAL:
2057                 PM8001_IO_DBG(pm8001_ha,
2058                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2059                 ts->resp = SAS_TASK_COMPLETE;
2060                 ts->stat = SAS_DEV_NO_RESPONSE;
2061                 if (!t->uldd_task) {
2062                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2063                                         IO_DS_NON_OPERATIONAL);
2064                         ts->resp = SAS_TASK_UNDELIVERED;
2065                         ts->stat = SAS_QUEUE_FULL;
2066                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2067                         mb();/*ditto*/
2068                         spin_unlock_irq(&pm8001_ha->lock);
2069                         t->task_done(t);
2070                         spin_lock_irq(&pm8001_ha->lock);
2071                         return;
2072                 }
2073                 break;
2074         case IO_DS_IN_RECOVERY:
2075                 PM8001_IO_DBG(pm8001_ha,
2076                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2077                 ts->resp = SAS_TASK_COMPLETE;
2078                 ts->stat = SAS_DEV_NO_RESPONSE;
2079                 break;
2080         case IO_DS_IN_ERROR:
2081                 PM8001_IO_DBG(pm8001_ha,
2082                         pm8001_printk("IO_DS_IN_ERROR\n"));
2083                 ts->resp = SAS_TASK_COMPLETE;
2084                 ts->stat = SAS_DEV_NO_RESPONSE;
2085                 if (!t->uldd_task) {
2086                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2087                                         IO_DS_IN_ERROR);
2088                         ts->resp = SAS_TASK_UNDELIVERED;
2089                         ts->stat = SAS_QUEUE_FULL;
2090                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2091                         mb();/*ditto*/
2092                         spin_unlock_irq(&pm8001_ha->lock);
2093                         t->task_done(t);
2094                         spin_lock_irq(&pm8001_ha->lock);
2095                         return;
2096                 }
2097                 break;
2098         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2099                 PM8001_IO_DBG(pm8001_ha,
2100                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2101                 ts->resp = SAS_TASK_COMPLETE;
2102                 ts->stat = SAS_OPEN_REJECT;
2103                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2104         default:
2105                 PM8001_IO_DBG(pm8001_ha,
2106                         pm8001_printk("Unknown status 0x%x\n", status));
2107                 /* not allowed case. Therefore, return failed status */
2108                 ts->resp = SAS_TASK_COMPLETE;
2109                 ts->stat = SAS_DEV_NO_RESPONSE;
2110                 break;
2111         }
2112         spin_lock_irqsave(&t->task_state_lock, flags);
2113         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2114         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2115         t->task_state_flags |= SAS_TASK_STATE_DONE;
2116         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2117                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2118                 PM8001_FAIL_DBG(pm8001_ha,
2119                         pm8001_printk("task 0x%p done with io_status 0x%x"
2120                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2121                         t, status, ts->resp, ts->stat));
2122                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2123         } else if (t->uldd_task) {
2124                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2125                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2126                 mb();/* ditto */
2127                 spin_unlock_irq(&pm8001_ha->lock);
2128                 t->task_done(t);
2129                 spin_lock_irq(&pm8001_ha->lock);
2130         } else if (!t->uldd_task) {
2131                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2132                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2133                 mb();/*ditto*/
2134                 spin_unlock_irq(&pm8001_ha->lock);
2135                 t->task_done(t);
2136                 spin_lock_irq(&pm8001_ha->lock);
2137         }
2138 }
2139
2140 /*See the comments for mpi_ssp_completion */
2141 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2142 {
2143         struct sas_task *t;
2144         struct task_status_struct *ts;
2145         struct pm8001_ccb_info *ccb;
2146         struct pm8001_device *pm8001_dev;
2147         struct sata_event_resp *psataPayload =
2148                 (struct sata_event_resp *)(piomb + 4);
2149         u32 event = le32_to_cpu(psataPayload->event);
2150         u32 tag = le32_to_cpu(psataPayload->tag);
2151         u32 port_id = le32_to_cpu(psataPayload->port_id);
2152         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2153         unsigned long flags;
2154
2155         ccb = &pm8001_ha->ccb_info[tag];
2156
2157         if (ccb) {
2158                 t = ccb->task;
2159                 pm8001_dev = ccb->device;
2160         } else {
2161                 PM8001_FAIL_DBG(pm8001_ha,
2162                         pm8001_printk("No CCB !!!. returning\n"));
2163                 return;
2164         }
2165         if (event)
2166                 PM8001_FAIL_DBG(pm8001_ha,
2167                         pm8001_printk("SATA EVENT 0x%x\n", event));
2168
2169         /* Check if this is NCQ error */
2170         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2171                 /* find device using device id */
2172                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2173                 /* send read log extension */
2174                 if (pm8001_dev)
2175                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2176                 return;
2177         }
2178
2179         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2180                 PM8001_FAIL_DBG(pm8001_ha,
2181                         pm8001_printk("task or dev null\n"));
2182                 return;
2183         }
2184
2185         ts = &t->task_status;
2186         PM8001_IO_DBG(pm8001_ha,
2187                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2188                                 port_id, tag, event));
2189         switch (event) {
2190         case IO_OVERFLOW:
2191                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2192                 ts->resp = SAS_TASK_COMPLETE;
2193                 ts->stat = SAS_DATA_OVERRUN;
2194                 ts->residual = 0;
2195                 if (pm8001_dev)
2196                         pm8001_dev->running_req--;
2197                 break;
2198         case IO_XFER_ERROR_BREAK:
2199                 PM8001_IO_DBG(pm8001_ha,
2200                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2201                 ts->resp = SAS_TASK_COMPLETE;
2202                 ts->stat = SAS_INTERRUPTED;
2203                 break;
2204         case IO_XFER_ERROR_PHY_NOT_READY:
2205                 PM8001_IO_DBG(pm8001_ha,
2206                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2207                 ts->resp = SAS_TASK_COMPLETE;
2208                 ts->stat = SAS_OPEN_REJECT;
2209                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2210                 break;
2211         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2212                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2213                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2214                 ts->resp = SAS_TASK_COMPLETE;
2215                 ts->stat = SAS_OPEN_REJECT;
2216                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2217                 break;
2218         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2219                 PM8001_IO_DBG(pm8001_ha,
2220                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2221                 ts->resp = SAS_TASK_COMPLETE;
2222                 ts->stat = SAS_OPEN_REJECT;
2223                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2224                 break;
2225         case IO_OPEN_CNX_ERROR_BREAK:
2226                 PM8001_IO_DBG(pm8001_ha,
2227                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2228                 ts->resp = SAS_TASK_COMPLETE;
2229                 ts->stat = SAS_OPEN_REJECT;
2230                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2231                 break;
2232         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2233         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2234         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2235         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2236         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2237         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2238                 PM8001_FAIL_DBG(pm8001_ha,
2239                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2240                 ts->resp = SAS_TASK_UNDELIVERED;
2241                 ts->stat = SAS_DEV_NO_RESPONSE;
2242                 if (!t->uldd_task) {
2243                         pm8001_handle_event(pm8001_ha,
2244                                 pm8001_dev,
2245                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2246                         ts->resp = SAS_TASK_COMPLETE;
2247                         ts->stat = SAS_QUEUE_FULL;
2248                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2249                         mb();/*ditto*/
2250                         spin_unlock_irq(&pm8001_ha->lock);
2251                         t->task_done(t);
2252                         spin_lock_irq(&pm8001_ha->lock);
2253                         return;
2254                 }
2255                 break;
2256         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2257                 PM8001_IO_DBG(pm8001_ha,
2258                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2259                 ts->resp = SAS_TASK_UNDELIVERED;
2260                 ts->stat = SAS_OPEN_REJECT;
2261                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2262                 break;
2263         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2264                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2265                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2266                 ts->resp = SAS_TASK_COMPLETE;
2267                 ts->stat = SAS_OPEN_REJECT;
2268                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2269                 break;
2270         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2271                 PM8001_IO_DBG(pm8001_ha,
2272                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2273                 ts->resp = SAS_TASK_COMPLETE;
2274                 ts->stat = SAS_OPEN_REJECT;
2275                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2276                 break;
2277         case IO_XFER_ERROR_NAK_RECEIVED:
2278                 PM8001_IO_DBG(pm8001_ha,
2279                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2280                 ts->resp = SAS_TASK_COMPLETE;
2281                 ts->stat = SAS_NAK_R_ERR;
2282                 break;
2283         case IO_XFER_ERROR_PEER_ABORTED:
2284                 PM8001_IO_DBG(pm8001_ha,
2285                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2286                 ts->resp = SAS_TASK_COMPLETE;
2287                 ts->stat = SAS_NAK_R_ERR;
2288                 break;
2289         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2290                 PM8001_IO_DBG(pm8001_ha,
2291                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2292                 ts->resp = SAS_TASK_COMPLETE;
2293                 ts->stat = SAS_DATA_UNDERRUN;
2294                 break;
2295         case IO_XFER_OPEN_RETRY_TIMEOUT:
2296                 PM8001_IO_DBG(pm8001_ha,
2297                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2298                 ts->resp = SAS_TASK_COMPLETE;
2299                 ts->stat = SAS_OPEN_TO;
2300                 break;
2301         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2302                 PM8001_IO_DBG(pm8001_ha,
2303                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2304                 ts->resp = SAS_TASK_COMPLETE;
2305                 ts->stat = SAS_OPEN_TO;
2306                 break;
2307         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2308                 PM8001_IO_DBG(pm8001_ha,
2309                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2310                 ts->resp = SAS_TASK_COMPLETE;
2311                 ts->stat = SAS_OPEN_TO;
2312                 break;
2313         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2314                 PM8001_IO_DBG(pm8001_ha,
2315                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2316                 ts->resp = SAS_TASK_COMPLETE;
2317                 ts->stat = SAS_OPEN_TO;
2318                 break;
2319         case IO_XFER_ERROR_OFFSET_MISMATCH:
2320                 PM8001_IO_DBG(pm8001_ha,
2321                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2322                 ts->resp = SAS_TASK_COMPLETE;
2323                 ts->stat = SAS_OPEN_TO;
2324                 break;
2325         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2326                 PM8001_IO_DBG(pm8001_ha,
2327                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2328                 ts->resp = SAS_TASK_COMPLETE;
2329                 ts->stat = SAS_OPEN_TO;
2330                 break;
2331         case IO_XFER_CMD_FRAME_ISSUED:
2332                 PM8001_IO_DBG(pm8001_ha,
2333                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2334                 break;
2335         case IO_XFER_PIO_SETUP_ERROR:
2336                 PM8001_IO_DBG(pm8001_ha,
2337                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2338                 ts->resp = SAS_TASK_COMPLETE;
2339                 ts->stat = SAS_OPEN_TO;
2340                 break;
2341         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2342                 PM8001_FAIL_DBG(pm8001_ha,
2343                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2344                 /* TBC: used default set values */
2345                 ts->resp = SAS_TASK_COMPLETE;
2346                 ts->stat = SAS_OPEN_TO;
2347                 break;
2348         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2349                 PM8001_FAIL_DBG(pm8001_ha,
2350                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2351                 /* TBC: used default set values */
2352                 ts->resp = SAS_TASK_COMPLETE;
2353                 ts->stat = SAS_OPEN_TO;
2354                 break;
2355         default:
2356                 PM8001_IO_DBG(pm8001_ha,
2357                         pm8001_printk("Unknown status 0x%x\n", event));
2358                 /* not allowed case. Therefore, return failed status */
2359                 ts->resp = SAS_TASK_COMPLETE;
2360                 ts->stat = SAS_OPEN_TO;
2361                 break;
2362         }
2363         spin_lock_irqsave(&t->task_state_lock, flags);
2364         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2365         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2366         t->task_state_flags |= SAS_TASK_STATE_DONE;
2367         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2368                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2369                 PM8001_FAIL_DBG(pm8001_ha,
2370                         pm8001_printk("task 0x%p done with io_status 0x%x"
2371                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2372                         t, event, ts->resp, ts->stat));
2373                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2374         } else if (t->uldd_task) {
2375                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2376                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2377                 mb();/* ditto */
2378                 spin_unlock_irq(&pm8001_ha->lock);
2379                 t->task_done(t);
2380                 spin_lock_irq(&pm8001_ha->lock);
2381         } else if (!t->uldd_task) {
2382                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2383                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2384                 mb();/*ditto*/
2385                 spin_unlock_irq(&pm8001_ha->lock);
2386                 t->task_done(t);
2387                 spin_lock_irq(&pm8001_ha->lock);
2388         }
2389 }
2390
2391 /*See the comments for mpi_ssp_completion */
2392 static void
2393 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2394 {
2395         u32 param, i;
2396         struct sas_task *t;
2397         struct pm8001_ccb_info *ccb;
2398         unsigned long flags;
2399         u32 status;
2400         u32 tag;
2401         struct smp_completion_resp *psmpPayload;
2402         struct task_status_struct *ts;
2403         struct pm8001_device *pm8001_dev;
2404         char *pdma_respaddr = NULL;
2405
2406         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2407         status = le32_to_cpu(psmpPayload->status);
2408         tag = le32_to_cpu(psmpPayload->tag);
2409
2410         ccb = &pm8001_ha->ccb_info[tag];
2411         param = le32_to_cpu(psmpPayload->param);
2412         t = ccb->task;
2413         ts = &t->task_status;
2414         pm8001_dev = ccb->device;
2415         if (status)
2416                 PM8001_FAIL_DBG(pm8001_ha,
2417                         pm8001_printk("smp IO status 0x%x\n", status));
2418         if (unlikely(!t || !t->lldd_task || !t->dev))
2419                 return;
2420
2421         switch (status) {
2422
2423         case IO_SUCCESS:
2424                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2425                 ts->resp = SAS_TASK_COMPLETE;
2426                 ts->stat = SAM_STAT_GOOD;
2427                 if (pm8001_dev)
2428                         pm8001_dev->running_req--;
2429                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2430                         PM8001_IO_DBG(pm8001_ha,
2431                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2432                                                 param));
2433                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2434                                                 ((u64)sg_dma_address
2435                                                 (&t->smp_task.smp_resp))));
2436                         for (i = 0; i < param; i++) {
2437                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2438                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2439                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2440                                         i, *(pdma_respaddr+i),
2441                                         psmpPayload->_r_a[i]));
2442                         }
2443                 }
2444                 break;
2445         case IO_ABORTED:
2446                 PM8001_IO_DBG(pm8001_ha,
2447                         pm8001_printk("IO_ABORTED IOMB\n"));
2448                 ts->resp = SAS_TASK_COMPLETE;
2449                 ts->stat = SAS_ABORTED_TASK;
2450                 if (pm8001_dev)
2451                         pm8001_dev->running_req--;
2452                 break;
2453         case IO_OVERFLOW:
2454                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2455                 ts->resp = SAS_TASK_COMPLETE;
2456                 ts->stat = SAS_DATA_OVERRUN;
2457                 ts->residual = 0;
2458                 if (pm8001_dev)
2459                         pm8001_dev->running_req--;
2460                 break;
2461         case IO_NO_DEVICE:
2462                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2463                 ts->resp = SAS_TASK_COMPLETE;
2464                 ts->stat = SAS_PHY_DOWN;
2465                 break;
2466         case IO_ERROR_HW_TIMEOUT:
2467                 PM8001_IO_DBG(pm8001_ha,
2468                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2469                 ts->resp = SAS_TASK_COMPLETE;
2470                 ts->stat = SAM_STAT_BUSY;
2471                 break;
2472         case IO_XFER_ERROR_BREAK:
2473                 PM8001_IO_DBG(pm8001_ha,
2474                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2475                 ts->resp = SAS_TASK_COMPLETE;
2476                 ts->stat = SAM_STAT_BUSY;
2477                 break;
2478         case IO_XFER_ERROR_PHY_NOT_READY:
2479                 PM8001_IO_DBG(pm8001_ha,
2480                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2481                 ts->resp = SAS_TASK_COMPLETE;
2482                 ts->stat = SAM_STAT_BUSY;
2483                 break;
2484         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2485                 PM8001_IO_DBG(pm8001_ha,
2486                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2487                 ts->resp = SAS_TASK_COMPLETE;
2488                 ts->stat = SAS_OPEN_REJECT;
2489                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2490                 break;
2491         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2492                 PM8001_IO_DBG(pm8001_ha,
2493                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2494                 ts->resp = SAS_TASK_COMPLETE;
2495                 ts->stat = SAS_OPEN_REJECT;
2496                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2497                 break;
2498         case IO_OPEN_CNX_ERROR_BREAK:
2499                 PM8001_IO_DBG(pm8001_ha,
2500                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2501                 ts->resp = SAS_TASK_COMPLETE;
2502                 ts->stat = SAS_OPEN_REJECT;
2503                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2504                 break;
2505         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2506         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2507         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2508         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2509         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2510         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2511                 PM8001_IO_DBG(pm8001_ha,
2512                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2513                 ts->resp = SAS_TASK_COMPLETE;
2514                 ts->stat = SAS_OPEN_REJECT;
2515                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2516                 pm8001_handle_event(pm8001_ha,
2517                                 pm8001_dev,
2518                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2519                 break;
2520         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2521                 PM8001_IO_DBG(pm8001_ha,
2522                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2523                 ts->resp = SAS_TASK_COMPLETE;
2524                 ts->stat = SAS_OPEN_REJECT;
2525                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2526                 break;
2527         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2528                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2529                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2530                 ts->resp = SAS_TASK_COMPLETE;
2531                 ts->stat = SAS_OPEN_REJECT;
2532                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2533                 break;
2534         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2535                 PM8001_IO_DBG(pm8001_ha,
2536                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2537                 ts->resp = SAS_TASK_COMPLETE;
2538                 ts->stat = SAS_OPEN_REJECT;
2539                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2540                 break;
2541         case IO_XFER_ERROR_RX_FRAME:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_DEV_NO_RESPONSE;
2546                 break;
2547         case IO_XFER_OPEN_RETRY_TIMEOUT:
2548                 PM8001_IO_DBG(pm8001_ha,
2549                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2550                 ts->resp = SAS_TASK_COMPLETE;
2551                 ts->stat = SAS_OPEN_REJECT;
2552                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2553                 break;
2554         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2555                 PM8001_IO_DBG(pm8001_ha,
2556                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2557                 ts->resp = SAS_TASK_COMPLETE;
2558                 ts->stat = SAS_QUEUE_FULL;
2559                 break;
2560         case IO_PORT_IN_RESET:
2561                 PM8001_IO_DBG(pm8001_ha,
2562                         pm8001_printk("IO_PORT_IN_RESET\n"));
2563                 ts->resp = SAS_TASK_COMPLETE;
2564                 ts->stat = SAS_OPEN_REJECT;
2565                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2566                 break;
2567         case IO_DS_NON_OPERATIONAL:
2568                 PM8001_IO_DBG(pm8001_ha,
2569                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2570                 ts->resp = SAS_TASK_COMPLETE;
2571                 ts->stat = SAS_DEV_NO_RESPONSE;
2572                 break;
2573         case IO_DS_IN_RECOVERY:
2574                 PM8001_IO_DBG(pm8001_ha,
2575                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2576                 ts->resp = SAS_TASK_COMPLETE;
2577                 ts->stat = SAS_OPEN_REJECT;
2578                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2579                 break;
2580         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2581                 PM8001_IO_DBG(pm8001_ha,
2582                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2583                 ts->resp = SAS_TASK_COMPLETE;
2584                 ts->stat = SAS_OPEN_REJECT;
2585                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2586                 break;
2587         default:
2588                 PM8001_IO_DBG(pm8001_ha,
2589                         pm8001_printk("Unknown status 0x%x\n", status));
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_DEV_NO_RESPONSE;
2592                 /* not allowed case. Therefore, return failed status */
2593                 break;
2594         }
2595         spin_lock_irqsave(&t->task_state_lock, flags);
2596         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2597         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2598         t->task_state_flags |= SAS_TASK_STATE_DONE;
2599         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2600                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2601                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2602                         "task 0x%p done with io_status 0x%x resp 0x%x"
2603                         "stat 0x%x but aborted by upper layer!\n",
2604                         t, status, ts->resp, ts->stat));
2605                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2606         } else {
2607                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2608                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2609                 mb();/* in order to force CPU ordering */
2610                 t->task_done(t);
2611         }
2612 }
2613
2614 /**
2615  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2616  * @pm8001_ha: our hba card information
2617  * @Qnum: the outbound queue message number.
2618  * @SEA: source of event to ack
2619  * @port_id: port id.
2620  * @phyId: phy id.
2621  * @param0: parameter 0.
2622  * @param1: parameter 1.
2623  */
2624 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2625         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2626 {
2627         struct hw_event_ack_req  payload;
2628         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2629
2630         struct inbound_queue_table *circularQ;
2631
2632         memset((u8 *)&payload, 0, sizeof(payload));
2633         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2634         payload.tag = cpu_to_le32(1);
2635         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2636                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2637         payload.param0 = cpu_to_le32(param0);
2638         payload.param1 = cpu_to_le32(param1);
2639         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2640 }
2641
2642 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2643         u32 phyId, u32 phy_op);
2644
2645 /**
2646  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2647  * @pm8001_ha: our hba card information
2648  * @piomb: IO message buffer
2649  */
2650 static void
2651 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2652 {
2653         struct hw_event_resp *pPayload =
2654                 (struct hw_event_resp *)(piomb + 4);
2655         u32 lr_status_evt_portid =
2656                 le32_to_cpu(pPayload->lr_status_evt_portid);
2657         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2658
2659         u8 link_rate =
2660                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2661         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2662         u8 phy_id =
2663                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2664         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2665
2666         struct pm8001_port *port = &pm8001_ha->port[port_id];
2667         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2668         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2669         unsigned long flags;
2670         u8 deviceType = pPayload->sas_identify.dev_type;
2671         port->port_state = portstate;
2672         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2673                 "portid:%d; phyid:%d; linkrate:%d; "
2674                 "portstate:%x; devicetype:%x\n",
2675                 port_id, phy_id, link_rate, portstate, deviceType));
2676
2677         switch (deviceType) {
2678         case SAS_PHY_UNUSED:
2679                 PM8001_MSG_DBG(pm8001_ha,
2680                         pm8001_printk("device type no device.\n"));
2681                 break;
2682         case SAS_END_DEVICE:
2683                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2684                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2685                         PHY_NOTIFY_ENABLE_SPINUP);
2686                 port->port_attached = 1;
2687                 pm8001_get_lrate_mode(phy, link_rate);
2688                 break;
2689         case SAS_EDGE_EXPANDER_DEVICE:
2690                 PM8001_MSG_DBG(pm8001_ha,
2691                         pm8001_printk("expander device.\n"));
2692                 port->port_attached = 1;
2693                 pm8001_get_lrate_mode(phy, link_rate);
2694                 break;
2695         case SAS_FANOUT_EXPANDER_DEVICE:
2696                 PM8001_MSG_DBG(pm8001_ha,
2697                         pm8001_printk("fanout expander device.\n"));
2698                 port->port_attached = 1;
2699                 pm8001_get_lrate_mode(phy, link_rate);
2700                 break;
2701         default:
2702                 PM8001_MSG_DBG(pm8001_ha,
2703                         pm8001_printk("unknown device type(%x)\n", deviceType));
2704                 break;
2705         }
2706         phy->phy_type |= PORT_TYPE_SAS;
2707         phy->identify.device_type = deviceType;
2708         phy->phy_attached = 1;
2709         if (phy->identify.device_type == SAS_END_DEVICE)
2710                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2711         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2712                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2713         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2714         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2715         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2716         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2717                 sizeof(struct sas_identify_frame)-4);
2718         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2719         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2720         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2721         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2722                 mdelay(200);/*delay a moment to wait disk to spinup*/
2723         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2724 }
2725
2726 /**
2727  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2728  * @pm8001_ha: our hba card information
2729  * @piomb: IO message buffer
2730  */
2731 static void
2732 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2733 {
2734         struct hw_event_resp *pPayload =
2735                 (struct hw_event_resp *)(piomb + 4);
2736         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2737         u32 lr_status_evt_portid =
2738                 le32_to_cpu(pPayload->lr_status_evt_portid);
2739         u8 link_rate =
2740                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2741         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2742         u8 phy_id =
2743                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2744
2745         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2746
2747         struct pm8001_port *port = &pm8001_ha->port[port_id];
2748         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2749         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2750         unsigned long flags;
2751         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2752                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2753                                 port_id, phy_id, link_rate, portstate));
2754
2755         port->port_state = portstate;
2756         port->port_attached = 1;
2757         pm8001_get_lrate_mode(phy, link_rate);
2758         phy->phy_type |= PORT_TYPE_SATA;
2759         phy->phy_attached = 1;
2760         phy->sas_phy.oob_mode = SATA_OOB_MODE;
2761         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2762         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2763         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2764                 sizeof(struct dev_to_host_fis));
2765         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2766         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2767         phy->identify.device_type = SAS_SATA_DEV;
2768         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2769         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2770         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2771 }
2772
2773 /**
2774  * hw_event_phy_down -we should notify the libsas the phy is down.
2775  * @pm8001_ha: our hba card information
2776  * @piomb: IO message buffer
2777  */
2778 static void
2779 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2780 {
2781         struct hw_event_resp *pPayload =
2782                 (struct hw_event_resp *)(piomb + 4);
2783
2784         u32 lr_status_evt_portid =
2785                 le32_to_cpu(pPayload->lr_status_evt_portid);
2786         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2787         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2788         u8 phy_id =
2789                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2790         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2791
2792         struct pm8001_port *port = &pm8001_ha->port[port_id];
2793         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2794         port->port_state = portstate;
2795         phy->phy_type = 0;
2796         phy->identify.device_type = 0;
2797         phy->phy_attached = 0;
2798         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2799         switch (portstate) {
2800         case PORT_VALID:
2801                 break;
2802         case PORT_INVALID:
2803                 PM8001_MSG_DBG(pm8001_ha,
2804                         pm8001_printk(" PortInvalid portID %d\n", port_id));
2805                 PM8001_MSG_DBG(pm8001_ha,
2806                         pm8001_printk(" Last phy Down and port invalid\n"));
2807                 port->port_attached = 0;
2808                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2809                         port_id, phy_id, 0, 0);
2810                 break;
2811         case PORT_IN_RESET:
2812                 PM8001_MSG_DBG(pm8001_ha,
2813                         pm8001_printk(" Port In Reset portID %d\n", port_id));
2814                 break;
2815         case PORT_NOT_ESTABLISHED:
2816                 PM8001_MSG_DBG(pm8001_ha,
2817                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2818                 port->port_attached = 0;
2819                 break;
2820         case PORT_LOSTCOMM:
2821                 PM8001_MSG_DBG(pm8001_ha,
2822                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2823                 PM8001_MSG_DBG(pm8001_ha,
2824                         pm8001_printk(" Last phy Down and port invalid\n"));
2825                 port->port_attached = 0;
2826                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2827                         port_id, phy_id, 0, 0);
2828                 break;
2829         default:
2830                 port->port_attached = 0;
2831                 PM8001_MSG_DBG(pm8001_ha,
2832                         pm8001_printk(" phy Down and(default) = 0x%x\n",
2833                         portstate));
2834                 break;
2835
2836         }
2837 }
2838
2839 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2840 {
2841         struct phy_start_resp *pPayload =
2842                 (struct phy_start_resp *)(piomb + 4);
2843         u32 status =
2844                 le32_to_cpu(pPayload->status);
2845         u32 phy_id =
2846                 le32_to_cpu(pPayload->phyid);
2847         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2848
2849         PM8001_INIT_DBG(pm8001_ha,
2850                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2851                                 status, phy_id));
2852         if (status == 0) {
2853                 phy->phy_state = 1;
2854                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2855                         complete(phy->enable_completion);
2856         }
2857         return 0;
2858
2859 }
2860
2861 /**
2862  * mpi_thermal_hw_event -The hw event has come.
2863  * @pm8001_ha: our hba card information
2864  * @piomb: IO message buffer
2865  */
2866 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2867 {
2868         struct thermal_hw_event *pPayload =
2869                 (struct thermal_hw_event *)(piomb + 4);
2870
2871         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2872         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2873
2874         if (thermal_event & 0x40) {
2875                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2876                         "Thermal Event: Local high temperature violated!\n"));
2877                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2878                         "Thermal Event: Measured local high temperature %d\n",
2879                                 ((rht_lht & 0xFF00) >> 8)));
2880         }
2881         if (thermal_event & 0x10) {
2882                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2883                         "Thermal Event: Remote high temperature violated!\n"));
2884                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2885                         "Thermal Event: Measured remote high temperature %d\n",
2886                                 ((rht_lht & 0xFF000000) >> 24)));
2887         }
2888         return 0;
2889 }
2890
2891 /**
2892  * mpi_hw_event -The hw event has come.
2893  * @pm8001_ha: our hba card information
2894  * @piomb: IO message buffer
2895  */
2896 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2897 {
2898         unsigned long flags;
2899         struct hw_event_resp *pPayload =
2900                 (struct hw_event_resp *)(piomb + 4);
2901         u32 lr_status_evt_portid =
2902                 le32_to_cpu(pPayload->lr_status_evt_portid);
2903         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2904         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2905         u8 phy_id =
2906                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2907         u16 eventType =
2908                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2909         u8 status =
2910                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2911
2912         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2913         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2914         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2915         PM8001_MSG_DBG(pm8001_ha,
2916                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2917                                 port_id, phy_id, eventType, status));
2918
2919         switch (eventType) {
2920
2921         case HW_EVENT_SAS_PHY_UP:
2922                 PM8001_MSG_DBG(pm8001_ha,
2923                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2924                 hw_event_sas_phy_up(pm8001_ha, piomb);
2925                 break;
2926         case HW_EVENT_SATA_PHY_UP:
2927                 PM8001_MSG_DBG(pm8001_ha,
2928                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2929                 hw_event_sata_phy_up(pm8001_ha, piomb);
2930                 break;
2931         case HW_EVENT_SATA_SPINUP_HOLD:
2932                 PM8001_MSG_DBG(pm8001_ha,
2933                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2934                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2935                 break;
2936         case HW_EVENT_PHY_DOWN:
2937                 PM8001_MSG_DBG(pm8001_ha,
2938                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2939                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2940                 phy->phy_attached = 0;
2941                 phy->phy_state = 0;
2942                 hw_event_phy_down(pm8001_ha, piomb);
2943                 break;
2944         case HW_EVENT_PORT_INVALID:
2945                 PM8001_MSG_DBG(pm8001_ha,
2946                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2947                 sas_phy_disconnected(sas_phy);
2948                 phy->phy_attached = 0;
2949                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2950                 break;
2951         /* the broadcast change primitive received, tell the LIBSAS this event
2952         to revalidate the sas domain*/
2953         case HW_EVENT_BROADCAST_CHANGE:
2954                 PM8001_MSG_DBG(pm8001_ha,
2955                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2956                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2957                         port_id, phy_id, 1, 0);
2958                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2959                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2960                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2961                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2962                 break;
2963         case HW_EVENT_PHY_ERROR:
2964                 PM8001_MSG_DBG(pm8001_ha,
2965                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2966                 sas_phy_disconnected(&phy->sas_phy);
2967                 phy->phy_attached = 0;
2968                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2969                 break;
2970         case HW_EVENT_BROADCAST_EXP:
2971                 PM8001_MSG_DBG(pm8001_ha,
2972                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2973                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2974                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2975                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2976                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2977                 break;
2978         case HW_EVENT_LINK_ERR_INVALID_DWORD:
2979                 PM8001_MSG_DBG(pm8001_ha,
2980                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2981                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2982                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2983                 sas_phy_disconnected(sas_phy);
2984                 phy->phy_attached = 0;
2985                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2986                 break;
2987         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2988                 PM8001_MSG_DBG(pm8001_ha,
2989                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2990                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2991                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2992                         port_id, phy_id, 0, 0);
2993                 sas_phy_disconnected(sas_phy);
2994                 phy->phy_attached = 0;
2995                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2996                 break;
2997         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2998                 PM8001_MSG_DBG(pm8001_ha,
2999                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3000                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3001                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3002                         port_id, phy_id, 0, 0);
3003                 sas_phy_disconnected(sas_phy);
3004                 phy->phy_attached = 0;
3005                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3006                 break;
3007         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3008                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3009                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3010                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3011                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3012                         port_id, phy_id, 0, 0);
3013                 sas_phy_disconnected(sas_phy);
3014                 phy->phy_attached = 0;
3015                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3016                 break;
3017         case HW_EVENT_MALFUNCTION:
3018                 PM8001_MSG_DBG(pm8001_ha,
3019                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3020                 break;
3021         case HW_EVENT_BROADCAST_SES:
3022                 PM8001_MSG_DBG(pm8001_ha,
3023                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3024                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3025                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3026                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3027                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3028                 break;
3029         case HW_EVENT_INBOUND_CRC_ERROR:
3030                 PM8001_MSG_DBG(pm8001_ha,
3031                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3032                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3033                         HW_EVENT_INBOUND_CRC_ERROR,
3034                         port_id, phy_id, 0, 0);
3035                 break;
3036         case HW_EVENT_HARD_RESET_RECEIVED:
3037                 PM8001_MSG_DBG(pm8001_ha,
3038                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3039                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3040                 break;
3041         case HW_EVENT_ID_FRAME_TIMEOUT:
3042                 PM8001_MSG_DBG(pm8001_ha,
3043                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3044                 sas_phy_disconnected(sas_phy);
3045                 phy->phy_attached = 0;
3046                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3047                 break;
3048         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3049                 PM8001_MSG_DBG(pm8001_ha,
3050                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3051                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3052                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3053                         port_id, phy_id, 0, 0);
3054                 sas_phy_disconnected(sas_phy);
3055                 phy->phy_attached = 0;
3056                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3057                 break;
3058         case HW_EVENT_PORT_RESET_TIMER_TMO:
3059                 PM8001_MSG_DBG(pm8001_ha,
3060                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3061                 sas_phy_disconnected(sas_phy);
3062                 phy->phy_attached = 0;
3063                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3064                 break;
3065         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3066                 PM8001_MSG_DBG(pm8001_ha,
3067                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3068                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3069                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3070                         port_id, phy_id, 0, 0);
3071                 sas_phy_disconnected(sas_phy);
3072                 phy->phy_attached = 0;
3073                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3074                 break;
3075         case HW_EVENT_PORT_RECOVER:
3076                 PM8001_MSG_DBG(pm8001_ha,
3077                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3078                 break;
3079         case HW_EVENT_PORT_RESET_COMPLETE:
3080                 PM8001_MSG_DBG(pm8001_ha,
3081                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3082                 break;
3083         case EVENT_BROADCAST_ASYNCH_EVENT:
3084                 PM8001_MSG_DBG(pm8001_ha,
3085                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3086                 break;
3087         default:
3088                 PM8001_MSG_DBG(pm8001_ha,
3089                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3090                 break;
3091         }
3092         return 0;
3093 }
3094
3095 /**
3096  * mpi_phy_stop_resp - SPCv specific
3097  * @pm8001_ha: our hba card information
3098  * @piomb: IO message buffer
3099  */
3100 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3101 {
3102         struct phy_stop_resp *pPayload =
3103                 (struct phy_stop_resp *)(piomb + 4);
3104         u32 status =
3105                 le32_to_cpu(pPayload->status);
3106         u32 phyid =
3107                 le32_to_cpu(pPayload->phyid);
3108         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3109         PM8001_MSG_DBG(pm8001_ha,
3110                         pm8001_printk("phy:0x%x status:0x%x\n",
3111                                         phyid, status));
3112         if (status == 0)
3113                 phy->phy_state = 0;
3114         return 0;
3115 }
3116
3117 /**
3118  * mpi_set_controller_config_resp - SPCv specific
3119  * @pm8001_ha: our hba card information
3120  * @piomb: IO message buffer
3121  */
3122 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3123                         void *piomb)
3124 {
3125         struct set_ctrl_cfg_resp *pPayload =
3126                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3127         u32 status = le32_to_cpu(pPayload->status);
3128         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3129
3130         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3131                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3132                         status, err_qlfr_pgcd));
3133
3134         return 0;
3135 }
3136
3137 /**
3138  * mpi_get_controller_config_resp - SPCv specific
3139  * @pm8001_ha: our hba card information
3140  * @piomb: IO message buffer
3141  */
3142 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3143                         void *piomb)
3144 {
3145         PM8001_MSG_DBG(pm8001_ha,
3146                         pm8001_printk(" pm80xx_addition_functionality\n"));
3147
3148         return 0;
3149 }
3150
3151 /**
3152  * mpi_get_phy_profile_resp - SPCv specific
3153  * @pm8001_ha: our hba card information
3154  * @piomb: IO message buffer
3155  */
3156 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3157                         void *piomb)
3158 {
3159         PM8001_MSG_DBG(pm8001_ha,
3160                         pm8001_printk(" pm80xx_addition_functionality\n"));
3161
3162         return 0;
3163 }
3164
3165 /**
3166  * mpi_flash_op_ext_resp - SPCv specific
3167  * @pm8001_ha: our hba card information
3168  * @piomb: IO message buffer
3169  */
3170 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3171 {
3172         PM8001_MSG_DBG(pm8001_ha,
3173                         pm8001_printk(" pm80xx_addition_functionality\n"));
3174
3175         return 0;
3176 }
3177
3178 /**
3179  * mpi_set_phy_profile_resp - SPCv specific
3180  * @pm8001_ha: our hba card information
3181  * @piomb: IO message buffer
3182  */
3183 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3184                         void *piomb)
3185 {
3186         u8 page_code;
3187         struct set_phy_profile_resp *pPayload =
3188                 (struct set_phy_profile_resp *)(piomb + 4);
3189         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3190         u32 status = le32_to_cpu(pPayload->status);
3191
3192         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3193         if (status) {
3194                 /* status is FAILED */
3195                 PM8001_FAIL_DBG(pm8001_ha,
3196                         pm8001_printk("PhyProfile command failed  with status "
3197                         "0x%08X \n", status));
3198                 return -1;
3199         } else {
3200                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3201                         PM8001_FAIL_DBG(pm8001_ha,
3202                                 pm8001_printk("Invalid page code 0x%X\n",
3203                                         page_code));
3204                         return -1;
3205                 }
3206         }
3207         return 0;
3208 }
3209
3210 /**
3211  * mpi_kek_management_resp - SPCv specific
3212  * @pm8001_ha: our hba card information
3213  * @piomb: IO message buffer
3214  */
3215 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3216                         void *piomb)
3217 {
3218         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3219
3220         u32 status = le32_to_cpu(pPayload->status);
3221         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3222         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3223
3224         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3225                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3226                 status, kidx_new_curr_ksop, err_qlfr));
3227
3228         return 0;
3229 }
3230
3231 /**
3232  * mpi_dek_management_resp - SPCv specific
3233  * @pm8001_ha: our hba card information
3234  * @piomb: IO message buffer
3235  */
3236 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3237                         void *piomb)
3238 {
3239         PM8001_MSG_DBG(pm8001_ha,
3240                         pm8001_printk(" pm80xx_addition_functionality\n"));
3241
3242         return 0;
3243 }
3244
3245 /**
3246  * ssp_coalesced_comp_resp - SPCv specific
3247  * @pm8001_ha: our hba card information
3248  * @piomb: IO message buffer
3249  */
3250 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3251                         void *piomb)
3252 {
3253         PM8001_MSG_DBG(pm8001_ha,
3254                         pm8001_printk(" pm80xx_addition_functionality\n"));
3255
3256         return 0;
3257 }
3258
3259 /**
3260  * process_one_iomb - process one outbound Queue memory block
3261  * @pm8001_ha: our hba card information
3262  * @piomb: IO message buffer
3263  */
3264 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3265 {
3266         __le32 pHeader = *(__le32 *)piomb;
3267         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3268
3269         switch (opc) {
3270         case OPC_OUB_ECHO:
3271                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3272                 break;
3273         case OPC_OUB_HW_EVENT:
3274                 PM8001_MSG_DBG(pm8001_ha,
3275                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3276                 mpi_hw_event(pm8001_ha, piomb);
3277                 break;
3278         case OPC_OUB_THERM_HW_EVENT:
3279                 PM8001_MSG_DBG(pm8001_ha,
3280                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3281                 mpi_thermal_hw_event(pm8001_ha, piomb);
3282                 break;
3283         case OPC_OUB_SSP_COMP:
3284                 PM8001_MSG_DBG(pm8001_ha,
3285                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3286                 mpi_ssp_completion(pm8001_ha, piomb);
3287                 break;
3288         case OPC_OUB_SMP_COMP:
3289                 PM8001_MSG_DBG(pm8001_ha,
3290                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3291                 mpi_smp_completion(pm8001_ha, piomb);
3292                 break;
3293         case OPC_OUB_LOCAL_PHY_CNTRL:
3294                 PM8001_MSG_DBG(pm8001_ha,
3295                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3296                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3297                 break;
3298         case OPC_OUB_DEV_REGIST:
3299                 PM8001_MSG_DBG(pm8001_ha,
3300                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3301                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3302                 break;
3303         case OPC_OUB_DEREG_DEV:
3304                 PM8001_MSG_DBG(pm8001_ha,
3305                         pm8001_printk("unregister the device\n"));
3306                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3307                 break;
3308         case OPC_OUB_GET_DEV_HANDLE:
3309                 PM8001_MSG_DBG(pm8001_ha,
3310                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3311                 break;
3312         case OPC_OUB_SATA_COMP:
3313                 PM8001_MSG_DBG(pm8001_ha,
3314                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3315                 mpi_sata_completion(pm8001_ha, piomb);
3316                 break;
3317         case OPC_OUB_SATA_EVENT:
3318                 PM8001_MSG_DBG(pm8001_ha,
3319                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3320                 mpi_sata_event(pm8001_ha, piomb);
3321                 break;
3322         case OPC_OUB_SSP_EVENT:
3323                 PM8001_MSG_DBG(pm8001_ha,
3324                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3325                 mpi_ssp_event(pm8001_ha, piomb);
3326                 break;
3327         case OPC_OUB_DEV_HANDLE_ARRIV:
3328                 PM8001_MSG_DBG(pm8001_ha,
3329                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3330                 /*This is for target*/
3331                 break;
3332         case OPC_OUB_SSP_RECV_EVENT:
3333                 PM8001_MSG_DBG(pm8001_ha,
3334                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3335                 /*This is for target*/
3336                 break;
3337         case OPC_OUB_FW_FLASH_UPDATE:
3338                 PM8001_MSG_DBG(pm8001_ha,
3339                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3340                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3341                 break;
3342         case OPC_OUB_GPIO_RESPONSE:
3343                 PM8001_MSG_DBG(pm8001_ha,
3344                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3345                 break;
3346         case OPC_OUB_GPIO_EVENT:
3347                 PM8001_MSG_DBG(pm8001_ha,
3348                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3349                 break;
3350         case OPC_OUB_GENERAL_EVENT:
3351                 PM8001_MSG_DBG(pm8001_ha,
3352                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3353                 pm8001_mpi_general_event(pm8001_ha, piomb);
3354                 break;
3355         case OPC_OUB_SSP_ABORT_RSP:
3356                 PM8001_MSG_DBG(pm8001_ha,
3357                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3358                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3359                 break;
3360         case OPC_OUB_SATA_ABORT_RSP:
3361                 PM8001_MSG_DBG(pm8001_ha,
3362                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3363                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3364                 break;
3365         case OPC_OUB_SAS_DIAG_MODE_START_END:
3366                 PM8001_MSG_DBG(pm8001_ha,
3367                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3368                 break;
3369         case OPC_OUB_SAS_DIAG_EXECUTE:
3370                 PM8001_MSG_DBG(pm8001_ha,
3371                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3372                 break;
3373         case OPC_OUB_GET_TIME_STAMP:
3374                 PM8001_MSG_DBG(pm8001_ha,
3375                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3376                 break;
3377         case OPC_OUB_SAS_HW_EVENT_ACK:
3378                 PM8001_MSG_DBG(pm8001_ha,
3379                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3380                 break;
3381         case OPC_OUB_PORT_CONTROL:
3382                 PM8001_MSG_DBG(pm8001_ha,
3383                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3384                 break;
3385         case OPC_OUB_SMP_ABORT_RSP:
3386                 PM8001_MSG_DBG(pm8001_ha,
3387                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3388                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3389                 break;
3390         case OPC_OUB_GET_NVMD_DATA:
3391                 PM8001_MSG_DBG(pm8001_ha,
3392                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3393                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3394                 break;
3395         case OPC_OUB_SET_NVMD_DATA:
3396                 PM8001_MSG_DBG(pm8001_ha,
3397                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3398                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3399                 break;
3400         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3401                 PM8001_MSG_DBG(pm8001_ha,
3402                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3403                 break;
3404         case OPC_OUB_SET_DEVICE_STATE:
3405                 PM8001_MSG_DBG(pm8001_ha,
3406                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3407                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3408                 break;
3409         case OPC_OUB_GET_DEVICE_STATE:
3410                 PM8001_MSG_DBG(pm8001_ha,
3411                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3412                 break;
3413         case OPC_OUB_SET_DEV_INFO:
3414                 PM8001_MSG_DBG(pm8001_ha,
3415                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3416                 break;
3417         /* spcv specifc commands */
3418         case OPC_OUB_PHY_START_RESP:
3419                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3420                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3421                 mpi_phy_start_resp(pm8001_ha, piomb);
3422                 break;
3423         case OPC_OUB_PHY_STOP_RESP:
3424                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3425                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3426                 mpi_phy_stop_resp(pm8001_ha, piomb);
3427                 break;
3428         case OPC_OUB_SET_CONTROLLER_CONFIG:
3429                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3430                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3431                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3432                 break;
3433         case OPC_OUB_GET_CONTROLLER_CONFIG:
3434                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3435                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3436                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3437                 break;
3438         case OPC_OUB_GET_PHY_PROFILE:
3439                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3440                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3441                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3442                 break;
3443         case OPC_OUB_FLASH_OP_EXT:
3444                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3445                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3446                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3447                 break;
3448         case OPC_OUB_SET_PHY_PROFILE:
3449                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3450                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3451                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3452                 break;
3453         case OPC_OUB_KEK_MANAGEMENT_RESP:
3454                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3455                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3456                 mpi_kek_management_resp(pm8001_ha, piomb);
3457                 break;
3458         case OPC_OUB_DEK_MANAGEMENT_RESP:
3459                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3460                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3461                 mpi_dek_management_resp(pm8001_ha, piomb);
3462                 break;
3463         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3464                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3465                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3466                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3467                 break;
3468         default:
3469                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3470                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3471                 break;
3472         }
3473 }
3474
3475 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3476 {
3477         struct outbound_queue_table *circularQ;
3478         void *pMsg1 = NULL;
3479         u8 uninitialized_var(bc);
3480         u32 ret = MPI_IO_STATUS_FAIL;
3481         unsigned long flags;
3482
3483         spin_lock_irqsave(&pm8001_ha->lock, flags);
3484         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3485         do {
3486                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3487                 if (MPI_IO_STATUS_SUCCESS == ret) {
3488                         /* process the outbound message */
3489                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3490                         /* free the message from the outbound circular buffer */
3491                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3492                                                         circularQ, bc);
3493                 }
3494                 if (MPI_IO_STATUS_BUSY == ret) {
3495                         /* Update the producer index from SPC */
3496                         circularQ->producer_index =
3497                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3498                         if (le32_to_cpu(circularQ->producer_index) ==
3499                                 circularQ->consumer_idx)
3500                                 /* OQ is empty */
3501                                 break;
3502                 }
3503         } while (1);
3504         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3505         return ret;
3506 }
3507
3508 /* PCI_DMA_... to our direction translation. */
3509 static const u8 data_dir_flags[] = {
3510         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3511         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3512         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3513         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3514 };
3515
3516 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3517                         struct smp_req *psmp_cmd, int mode, int length)
3518 {
3519         psmp_cmd->tag = hTag;
3520         psmp_cmd->device_id = cpu_to_le32(deviceID);
3521         if (mode == SMP_DIRECT) {
3522                 length = length - 4; /* subtract crc */
3523                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3524         } else {
3525                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3526         }
3527 }
3528
3529 /**
3530  * pm8001_chip_smp_req - send a SMP task to FW
3531  * @pm8001_ha: our hba card information.
3532  * @ccb: the ccb information this request used.
3533  */
3534 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3535         struct pm8001_ccb_info *ccb)
3536 {
3537         int elem, rc;
3538         struct sas_task *task = ccb->task;
3539         struct domain_device *dev = task->dev;
3540         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3541         struct scatterlist *sg_req, *sg_resp;
3542         u32 req_len, resp_len;
3543         struct smp_req smp_cmd;
3544         u32 opc;
3545         struct inbound_queue_table *circularQ;
3546         char *preq_dma_addr = NULL;
3547         __le64 tmp_addr;
3548         u32 i, length;
3549
3550         memset(&smp_cmd, 0, sizeof(smp_cmd));
3551         /*
3552          * DMA-map SMP request, response buffers
3553          */
3554         sg_req = &task->smp_task.smp_req;
3555         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3556         if (!elem)
3557                 return -ENOMEM;
3558         req_len = sg_dma_len(sg_req);
3559
3560         sg_resp = &task->smp_task.smp_resp;
3561         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3562         if (!elem) {
3563                 rc = -ENOMEM;
3564                 goto err_out;
3565         }
3566         resp_len = sg_dma_len(sg_resp);
3567         /* must be in dwords */
3568         if ((req_len & 0x3) || (resp_len & 0x3)) {
3569                 rc = -EINVAL;
3570                 goto err_out_2;
3571         }
3572
3573         opc = OPC_INB_SMP_REQUEST;
3574         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3575         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3576
3577         length = sg_req->length;
3578         PM8001_IO_DBG(pm8001_ha,
3579                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3580         if (!(length - 8))
3581                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3582         else
3583                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3584
3585
3586         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3587         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3588
3589         /* INDIRECT MODE command settings. Use DMA */
3590         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3591                 PM8001_IO_DBG(pm8001_ha,
3592                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3593                 /* for SPCv indirect mode. Place the top 4 bytes of
3594                  * SMP Request header here. */
3595                 for (i = 0; i < 4; i++)
3596                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3597                 /* exclude top 4 bytes for SMP req header */
3598                 smp_cmd.long_smp_req.long_req_addr =
3599                         cpu_to_le64((u64)sg_dma_address
3600                                 (&task->smp_task.smp_req) + 4);
3601                 /* exclude 4 bytes for SMP req header and CRC */
3602                 smp_cmd.long_smp_req.long_req_size =
3603                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3604                 smp_cmd.long_smp_req.long_resp_addr =
3605                                 cpu_to_le64((u64)sg_dma_address
3606                                         (&task->smp_task.smp_resp));
3607                 smp_cmd.long_smp_req.long_resp_size =
3608                                 cpu_to_le32((u32)sg_dma_len
3609                                         (&task->smp_task.smp_resp)-4);
3610         } else { /* DIRECT MODE */
3611                 smp_cmd.long_smp_req.long_req_addr =
3612                         cpu_to_le64((u64)sg_dma_address
3613                                         (&task->smp_task.smp_req));
3614                 smp_cmd.long_smp_req.long_req_size =
3615                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3616                 smp_cmd.long_smp_req.long_resp_addr =
3617                         cpu_to_le64((u64)sg_dma_address
3618                                 (&task->smp_task.smp_resp));
3619                 smp_cmd.long_smp_req.long_resp_size =
3620                         cpu_to_le32
3621                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3622         }
3623         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3624                 PM8001_IO_DBG(pm8001_ha,
3625                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3626                 for (i = 0; i < length; i++)
3627                         if (i < 16) {
3628                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3629                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3630                                         "Byte[%d]:%x (DMA data:%x)\n",
3631                                         i, smp_cmd.smp_req16[i],
3632                                         *(preq_dma_addr)));
3633                         } else {
3634                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3635                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3636                                         "Byte[%d]:%x (DMA data:%x)\n",
3637                                         i, smp_cmd.smp_req[i],
3638                                         *(preq_dma_addr)));
3639                         }
3640         }
3641
3642         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3643                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3644         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3645         return 0;
3646
3647 err_out_2:
3648         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3649                         PCI_DMA_FROMDEVICE);
3650 err_out:
3651         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3652                         PCI_DMA_TODEVICE);
3653         return rc;
3654 }
3655
3656 static int check_enc_sas_cmd(struct sas_task *task)
3657 {
3658         u8 cmd = task->ssp_task.cmd->cmnd[0];
3659
3660         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3661                 return 1;
3662         else
3663                 return 0;
3664 }
3665
3666 static int check_enc_sat_cmd(struct sas_task *task)
3667 {
3668         int ret = 0;
3669         switch (task->ata_task.fis.command) {
3670         case ATA_CMD_FPDMA_READ:
3671         case ATA_CMD_READ_EXT:
3672         case ATA_CMD_READ:
3673         case ATA_CMD_FPDMA_WRITE:
3674         case ATA_CMD_WRITE_EXT:
3675         case ATA_CMD_WRITE:
3676         case ATA_CMD_PIO_READ:
3677         case ATA_CMD_PIO_READ_EXT:
3678         case ATA_CMD_PIO_WRITE:
3679         case ATA_CMD_PIO_WRITE_EXT:
3680                 ret = 1;
3681                 break;
3682         default:
3683                 ret = 0;
3684                 break;
3685         }
3686         return ret;
3687 }
3688
3689 /**
3690  * pm80xx_chip_ssp_io_req - send a SSP task to FW
3691  * @pm8001_ha: our hba card information.
3692  * @ccb: the ccb information this request used.
3693  */
3694 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3695         struct pm8001_ccb_info *ccb)
3696 {
3697         struct sas_task *task = ccb->task;
3698         struct domain_device *dev = task->dev;
3699         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3700         struct ssp_ini_io_start_req ssp_cmd;
3701         u32 tag = ccb->ccb_tag;
3702         int ret;
3703         u64 phys_addr, start_addr, end_addr;
3704         u32 end_addr_high, end_addr_low;
3705         struct inbound_queue_table *circularQ;
3706         u32 q_index;
3707         u32 opc = OPC_INB_SSPINIIOSTART;
3708         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3709         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3710         /* data address domain added for spcv; set to 0 by host,
3711          * used internally by controller
3712          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3713          */
3714         ssp_cmd.dad_dir_m_tlr =
3715                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3716         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3717         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3718         ssp_cmd.tag = cpu_to_le32(tag);
3719         if (task->ssp_task.enable_first_burst)
3720                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3721         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3722         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3723         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3724                        task->ssp_task.cmd->cmd_len);
3725         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3726         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3727
3728         /* Check if encryption is set */
3729         if (pm8001_ha->chip->encrypt &&
3730                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3731                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3732                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3733                         task->ssp_task.cmd->cmnd[0]));
3734                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3735                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3736                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3737                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3738
3739                 /* fill in PRD (scatter/gather) table, if any */
3740                 if (task->num_scatter > 1) {
3741                         pm8001_chip_make_sg(task->scatter,
3742                                                 ccb->n_elem, ccb->buf_prd);
3743                         phys_addr = ccb->ccb_dma_handle +
3744                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3745                         ssp_cmd.enc_addr_low =
3746                                 cpu_to_le32(lower_32_bits(phys_addr));
3747                         ssp_cmd.enc_addr_high =
3748                                 cpu_to_le32(upper_32_bits(phys_addr));
3749                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3750                 } else if (task->num_scatter == 1) {
3751                         u64 dma_addr = sg_dma_address(task->scatter);
3752                         ssp_cmd.enc_addr_low =
3753                                 cpu_to_le32(lower_32_bits(dma_addr));
3754                         ssp_cmd.enc_addr_high =
3755                                 cpu_to_le32(upper_32_bits(dma_addr));
3756                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3757                         ssp_cmd.enc_esgl = 0;
3758                         /* Check 4G Boundary */
3759                         start_addr = cpu_to_le64(dma_addr);
3760                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3761                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3762                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3763                         if (end_addr_high != ssp_cmd.enc_addr_high) {
3764                                 PM8001_FAIL_DBG(pm8001_ha,
3765                                         pm8001_printk("The sg list address "
3766                                         "start_addr=0x%016llx data_len=0x%x "
3767                                         "end_addr_high=0x%08x end_addr_low="
3768                                         "0x%08x has crossed 4G boundary\n",
3769                                                 start_addr, ssp_cmd.enc_len,
3770                                                 end_addr_high, end_addr_low));
3771                                 pm8001_chip_make_sg(task->scatter, 1,
3772                                         ccb->buf_prd);
3773                                 phys_addr = ccb->ccb_dma_handle +
3774                                         offsetof(struct pm8001_ccb_info,
3775                                                 buf_prd[0]);
3776                                 ssp_cmd.enc_addr_low =
3777                                         cpu_to_le32(lower_32_bits(phys_addr));
3778                                 ssp_cmd.enc_addr_high =
3779                                         cpu_to_le32(upper_32_bits(phys_addr));
3780                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3781                         }
3782                 } else if (task->num_scatter == 0) {
3783                         ssp_cmd.enc_addr_low = 0;
3784                         ssp_cmd.enc_addr_high = 0;
3785                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3786                         ssp_cmd.enc_esgl = 0;
3787                 }
3788                 /* XTS mode. All other fields are 0 */
3789                 ssp_cmd.key_cmode = 0x6 << 4;
3790                 /* set tweak values. Should be the start lba */
3791                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3792                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
3793                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
3794                                                 (task->ssp_task.cmd->cmnd[5]));
3795         } else {
3796                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3797                         "Sending Normal SAS command 0x%x inb q %x\n",
3798                         task->ssp_task.cmd->cmnd[0], q_index));
3799                 /* fill in PRD (scatter/gather) table, if any */
3800                 if (task->num_scatter > 1) {
3801                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3802                                         ccb->buf_prd);
3803                         phys_addr = ccb->ccb_dma_handle +
3804                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3805                         ssp_cmd.addr_low =
3806                                 cpu_to_le32(lower_32_bits(phys_addr));
3807                         ssp_cmd.addr_high =
3808                                 cpu_to_le32(upper_32_bits(phys_addr));
3809                         ssp_cmd.esgl = cpu_to_le32(1<<31);
3810                 } else if (task->num_scatter == 1) {
3811                         u64 dma_addr = sg_dma_address(task->scatter);
3812                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3813                         ssp_cmd.addr_high =
3814                                 cpu_to_le32(upper_32_bits(dma_addr));
3815                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3816                         ssp_cmd.esgl = 0;
3817                         /* Check 4G Boundary */
3818                         start_addr = cpu_to_le64(dma_addr);
3819                         end_addr = (start_addr + ssp_cmd.len) - 1;
3820                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3821                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3822                         if (end_addr_high != ssp_cmd.addr_high) {
3823                                 PM8001_FAIL_DBG(pm8001_ha,
3824                                         pm8001_printk("The sg list address "
3825                                         "start_addr=0x%016llx data_len=0x%x "
3826                                         "end_addr_high=0x%08x end_addr_low="
3827                                         "0x%08x has crossed 4G boundary\n",
3828                                                  start_addr, ssp_cmd.len,
3829                                                  end_addr_high, end_addr_low));
3830                                 pm8001_chip_make_sg(task->scatter, 1,
3831                                         ccb->buf_prd);
3832                                 phys_addr = ccb->ccb_dma_handle +
3833                                         offsetof(struct pm8001_ccb_info,
3834                                                  buf_prd[0]);
3835                                 ssp_cmd.addr_low =
3836                                         cpu_to_le32(lower_32_bits(phys_addr));
3837                                 ssp_cmd.addr_high =
3838                                         cpu_to_le32(upper_32_bits(phys_addr));
3839                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
3840                         }
3841                 } else if (task->num_scatter == 0) {
3842                         ssp_cmd.addr_low = 0;
3843                         ssp_cmd.addr_high = 0;
3844                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3845                         ssp_cmd.esgl = 0;
3846                 }
3847         }
3848         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
3849         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3850                                                 &ssp_cmd, q_index);
3851         return ret;
3852 }
3853
3854 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3855         struct pm8001_ccb_info *ccb)
3856 {
3857         struct sas_task *task = ccb->task;
3858         struct domain_device *dev = task->dev;
3859         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3860         u32 tag = ccb->ccb_tag;
3861         int ret;
3862         u32 q_index;
3863         struct sata_start_req sata_cmd;
3864         u32 hdr_tag, ncg_tag = 0;
3865         u64 phys_addr, start_addr, end_addr;
3866         u32 end_addr_high, end_addr_low;
3867         u32 ATAP = 0x0;
3868         u32 dir;
3869         struct inbound_queue_table *circularQ;
3870         unsigned long flags;
3871         u32 opc = OPC_INB_SATA_HOST_OPSTART;
3872         memset(&sata_cmd, 0, sizeof(sata_cmd));
3873         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3874         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3875
3876         if (task->data_dir == PCI_DMA_NONE) {
3877                 ATAP = 0x04; /* no data*/
3878                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3879         } else if (likely(!task->ata_task.device_control_reg_update)) {
3880                 if (task->ata_task.dma_xfer) {
3881                         ATAP = 0x06; /* DMA */
3882                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3883                 } else {
3884                         ATAP = 0x05; /* PIO*/
3885                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3886                 }
3887                 if (task->ata_task.use_ncq &&
3888                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3889                         ATAP = 0x07; /* FPDMA */
3890                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3891                 }
3892         }
3893         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
3894                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
3895                 ncg_tag = hdr_tag;
3896         }
3897         dir = data_dir_flags[task->data_dir] << 8;
3898         sata_cmd.tag = cpu_to_le32(tag);
3899         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3900         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3901
3902         sata_cmd.sata_fis = task->ata_task.fis;
3903         if (likely(!task->ata_task.device_control_reg_update))
3904                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3905         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3906
3907         /* Check if encryption is set */
3908         if (pm8001_ha->chip->encrypt &&
3909                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3910                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3911                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3912                         sata_cmd.sata_fis.command));
3913                 opc = OPC_INB_SATA_DIF_ENC_IO;
3914
3915                 /* set encryption bit */
3916                 sata_cmd.ncqtag_atap_dir_m_dad =
3917                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
3918                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3919                                                         /* dad (bit 0-1) is 0 */
3920                 /* fill in PRD (scatter/gather) table, if any */
3921                 if (task->num_scatter > 1) {
3922                         pm8001_chip_make_sg(task->scatter,
3923                                                 ccb->n_elem, ccb->buf_prd);
3924                         phys_addr = ccb->ccb_dma_handle +
3925                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3926                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3927                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3928                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3929                 } else if (task->num_scatter == 1) {
3930                         u64 dma_addr = sg_dma_address(task->scatter);
3931                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3932                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3933                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3934                         sata_cmd.enc_esgl = 0;
3935                         /* Check 4G Boundary */
3936                         start_addr = cpu_to_le64(dma_addr);
3937                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
3938                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3939                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3940                         if (end_addr_high != sata_cmd.enc_addr_high) {
3941                                 PM8001_FAIL_DBG(pm8001_ha,
3942                                         pm8001_printk("The sg list address "
3943                                         "start_addr=0x%016llx data_len=0x%x "
3944                                         "end_addr_high=0x%08x end_addr_low"
3945                                         "=0x%08x has crossed 4G boundary\n",
3946                                                 start_addr, sata_cmd.enc_len,
3947                                                 end_addr_high, end_addr_low));
3948                                 pm8001_chip_make_sg(task->scatter, 1,
3949                                         ccb->buf_prd);
3950                                 phys_addr = ccb->ccb_dma_handle +
3951                                                 offsetof(struct pm8001_ccb_info,
3952                                                 buf_prd[0]);
3953                                 sata_cmd.enc_addr_low =
3954                                         lower_32_bits(phys_addr);
3955                                 sata_cmd.enc_addr_high =
3956                                         upper_32_bits(phys_addr);
3957                                 sata_cmd.enc_esgl =
3958                                         cpu_to_le32(1 << 31);
3959                         }
3960                 } else if (task->num_scatter == 0) {
3961                         sata_cmd.enc_addr_low = 0;
3962                         sata_cmd.enc_addr_high = 0;
3963                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3964                         sata_cmd.enc_esgl = 0;
3965                 }
3966                 /* XTS mode. All other fields are 0 */
3967                 sata_cmd.key_index_mode = 0x6 << 4;
3968                 /* set tweak values. Should be the start lba */
3969                 sata_cmd.twk_val0 =
3970                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3971                                         (sata_cmd.sata_fis.lbah << 16) |
3972                                         (sata_cmd.sata_fis.lbam << 8) |
3973                                         (sata_cmd.sata_fis.lbal));
3974                 sata_cmd.twk_val1 =
3975                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3976                                          (sata_cmd.sata_fis.lbam_exp));
3977         } else {
3978                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3979                         "Sending Normal SATA command 0x%x inb %x\n",
3980                         sata_cmd.sata_fis.command, q_index));
3981                 /* dad (bit 0-1) is 0 */
3982                 sata_cmd.ncqtag_atap_dir_m_dad =
3983                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
3984                                         ((ATAP & 0x3f) << 10) | dir);
3985
3986                 /* fill in PRD (scatter/gather) table, if any */
3987                 if (task->num_scatter > 1) {
3988                         pm8001_chip_make_sg(task->scatter,
3989                                         ccb->n_elem, ccb->buf_prd);
3990                         phys_addr = ccb->ccb_dma_handle +
3991                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3992                         sata_cmd.addr_low = lower_32_bits(phys_addr);
3993                         sata_cmd.addr_high = upper_32_bits(phys_addr);
3994                         sata_cmd.esgl = cpu_to_le32(1 << 31);
3995                 } else if (task->num_scatter == 1) {
3996                         u64 dma_addr = sg_dma_address(task->scatter);
3997                         sata_cmd.addr_low = lower_32_bits(dma_addr);
3998                         sata_cmd.addr_high = upper_32_bits(dma_addr);
3999                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4000                         sata_cmd.esgl = 0;
4001                         /* Check 4G Boundary */
4002                         start_addr = cpu_to_le64(dma_addr);
4003                         end_addr = (start_addr + sata_cmd.len) - 1;
4004                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4005                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4006                         if (end_addr_high != sata_cmd.addr_high) {
4007                                 PM8001_FAIL_DBG(pm8001_ha,
4008                                         pm8001_printk("The sg list address "
4009                                         "start_addr=0x%016llx data_len=0x%x"
4010                                         "end_addr_high=0x%08x end_addr_low="
4011                                         "0x%08x has crossed 4G boundary\n",
4012                                                 start_addr, sata_cmd.len,
4013                                                 end_addr_high, end_addr_low));
4014                                 pm8001_chip_make_sg(task->scatter, 1,
4015                                         ccb->buf_prd);
4016                                 phys_addr = ccb->ccb_dma_handle +
4017                                         offsetof(struct pm8001_ccb_info,
4018                                         buf_prd[0]);
4019                                 sata_cmd.addr_low =
4020                                         lower_32_bits(phys_addr);
4021                                 sata_cmd.addr_high =
4022                                         upper_32_bits(phys_addr);
4023                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4024                         }
4025                 } else if (task->num_scatter == 0) {
4026                         sata_cmd.addr_low = 0;
4027                         sata_cmd.addr_high = 0;
4028                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4029                         sata_cmd.esgl = 0;
4030                 }
4031                         /* scsi cdb */
4032                         sata_cmd.atapi_scsi_cdb[0] =
4033                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4034                                 (task->ata_task.atapi_packet[1] << 8) |
4035                                 (task->ata_task.atapi_packet[2] << 16) |
4036                                 (task->ata_task.atapi_packet[3] << 24)));
4037                         sata_cmd.atapi_scsi_cdb[1] =
4038                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4039                                 (task->ata_task.atapi_packet[5] << 8) |
4040                                 (task->ata_task.atapi_packet[6] << 16) |
4041                                 (task->ata_task.atapi_packet[7] << 24)));
4042                         sata_cmd.atapi_scsi_cdb[2] =
4043                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4044                                 (task->ata_task.atapi_packet[9] << 8) |
4045                                 (task->ata_task.atapi_packet[10] << 16) |
4046                                 (task->ata_task.atapi_packet[11] << 24)));
4047                         sata_cmd.atapi_scsi_cdb[3] =
4048                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4049                                 (task->ata_task.atapi_packet[13] << 8) |
4050                                 (task->ata_task.atapi_packet[14] << 16) |
4051                                 (task->ata_task.atapi_packet[15] << 24)));
4052         }
4053
4054         /* Check for read log for failed drive and return */
4055         if (sata_cmd.sata_fis.command == 0x2f) {
4056                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4057                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4058                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4059                         struct task_status_struct *ts;
4060
4061                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4062                         ts = &task->task_status;
4063
4064                         spin_lock_irqsave(&task->task_state_lock, flags);
4065                         ts->resp = SAS_TASK_COMPLETE;
4066                         ts->stat = SAM_STAT_GOOD;
4067                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4068                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4069                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4070                         if (unlikely((task->task_state_flags &
4071                                         SAS_TASK_STATE_ABORTED))) {
4072                                 spin_unlock_irqrestore(&task->task_state_lock,
4073                                                         flags);
4074                                 PM8001_FAIL_DBG(pm8001_ha,
4075                                         pm8001_printk("task 0x%p resp 0x%x "
4076                                         " stat 0x%x but aborted by upper layer "
4077                                         "\n", task, ts->resp, ts->stat));
4078                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4079                                 return 0;
4080                         } else if (task->uldd_task) {
4081                                 spin_unlock_irqrestore(&task->task_state_lock,
4082                                                         flags);
4083                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4084                                 mb();/* ditto */
4085                                 spin_unlock_irq(&pm8001_ha->lock);
4086                                 task->task_done(task);
4087                                 spin_lock_irq(&pm8001_ha->lock);
4088                                 return 0;
4089                         } else if (!task->uldd_task) {
4090                                 spin_unlock_irqrestore(&task->task_state_lock,
4091                                                         flags);
4092                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4093                                 mb();/*ditto*/
4094                                 spin_unlock_irq(&pm8001_ha->lock);
4095                                 task->task_done(task);
4096                                 spin_lock_irq(&pm8001_ha->lock);
4097                                 return 0;
4098                         }
4099                 }
4100         }
4101         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4102         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4103                                                 &sata_cmd, q_index);
4104         return ret;
4105 }
4106
4107 /**
4108  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4109  * @pm8001_ha: our hba card information.
4110  * @num: the inbound queue number
4111  * @phy_id: the phy id which we wanted to start up.
4112  */
4113 static int
4114 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4115 {
4116         struct phy_start_req payload;
4117         struct inbound_queue_table *circularQ;
4118         int ret;
4119         u32 tag = 0x01;
4120         u32 opcode = OPC_INB_PHYSTART;
4121         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4122         memset(&payload, 0, sizeof(payload));
4123         payload.tag = cpu_to_le32(tag);
4124
4125         PM8001_INIT_DBG(pm8001_ha,
4126                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4127         /*
4128          ** [0:7]       PHY Identifier
4129          ** [8:11]      link rate 1.5G, 3G, 6G
4130          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4131          ** [14]        0b disable spin up hold; 1b enable spin up hold
4132          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4133          */
4134         if (!IS_SPCV_12G(pm8001_ha->pdev))
4135                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4136                                 LINKMODE_AUTO | LINKRATE_15 |
4137                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4138         else
4139                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4140                                 LINKMODE_AUTO | LINKRATE_15 |
4141                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4142                                 phy_id);
4143
4144         /* SSC Disable and SAS Analog ST configuration */
4145         /**
4146         payload.ase_sh_lm_slr_phyid =
4147                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4148                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4149                 phy_id);
4150         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4151         **/
4152
4153         payload.sas_identify.dev_type = SAS_END_DEVICE;
4154         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4155         memcpy(payload.sas_identify.sas_addr,
4156                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4157         payload.sas_identify.phy_id = phy_id;
4158         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4159         return ret;
4160 }
4161
4162 /**
4163  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4164  * @pm8001_ha: our hba card information.
4165  * @num: the inbound queue number
4166  * @phy_id: the phy id which we wanted to start up.
4167  */
4168 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4169         u8 phy_id)
4170 {
4171         struct phy_stop_req payload;
4172         struct inbound_queue_table *circularQ;
4173         int ret;
4174         u32 tag = 0x01;
4175         u32 opcode = OPC_INB_PHYSTOP;
4176         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4177         memset(&payload, 0, sizeof(payload));
4178         payload.tag = cpu_to_le32(tag);
4179         payload.phy_id = cpu_to_le32(phy_id);
4180         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4181         return ret;
4182 }
4183
4184 /**
4185  * see comments on pm8001_mpi_reg_resp.
4186  */
4187 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4188         struct pm8001_device *pm8001_dev, u32 flag)
4189 {
4190         struct reg_dev_req payload;
4191         u32     opc;
4192         u32 stp_sspsmp_sata = 0x4;
4193         struct inbound_queue_table *circularQ;
4194         u32 linkrate, phy_id;
4195         int rc, tag = 0xdeadbeef;
4196         struct pm8001_ccb_info *ccb;
4197         u8 retryFlag = 0x1;
4198         u16 firstBurstSize = 0;
4199         u16 ITNT = 2000;
4200         struct domain_device *dev = pm8001_dev->sas_device;
4201         struct domain_device *parent_dev = dev->parent;
4202         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4203
4204         memset(&payload, 0, sizeof(payload));
4205         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4206         if (rc)
4207                 return rc;
4208         ccb = &pm8001_ha->ccb_info[tag];
4209         ccb->device = pm8001_dev;
4210         ccb->ccb_tag = tag;
4211         payload.tag = cpu_to_le32(tag);
4212
4213         if (flag == 1) {
4214                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4215         } else {
4216                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4217                         stp_sspsmp_sata = 0x00; /* stp*/
4218                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4219                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4220                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4221                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4222         }
4223         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4224                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4225         else
4226                 phy_id = pm8001_dev->attached_phy;
4227
4228         opc = OPC_INB_REG_DEV;
4229
4230         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4231                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4232
4233         payload.phyid_portid =
4234                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4235                 ((phy_id & 0xFF) << 8));
4236
4237         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4238                 ((linkrate & 0x0F) << 24) |
4239                 ((stp_sspsmp_sata & 0x03) << 28));
4240         payload.firstburstsize_ITNexustimeout =
4241                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4242
4243         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4244                 SAS_ADDR_SIZE);
4245
4246         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4247
4248         return rc;
4249 }
4250
4251 /**
4252  * pm80xx_chip_phy_ctl_req - support the local phy operation
4253  * @pm8001_ha: our hba card information.
4254  * @num: the inbound queue number
4255  * @phy_id: the phy id which we wanted to operate
4256  * @phy_op:
4257  */
4258 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4259         u32 phyId, u32 phy_op)
4260 {
4261         struct local_phy_ctl_req payload;
4262         struct inbound_queue_table *circularQ;
4263         int ret;
4264         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4265         memset(&payload, 0, sizeof(payload));
4266         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4267         payload.tag = cpu_to_le32(1);
4268         payload.phyop_phyid =
4269                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4270         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4271         return ret;
4272 }
4273
4274 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4275 {
4276         u32 value;
4277 #ifdef PM8001_USE_MSIX
4278         return 1;
4279 #endif
4280         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4281         if (value)
4282                 return 1;
4283         return 0;
4284
4285 }
4286
4287 /**
4288  * pm8001_chip_isr - PM8001 isr handler.
4289  * @pm8001_ha: our hba card information.
4290  * @irq: irq number.
4291  * @stat: stat.
4292  */
4293 static irqreturn_t
4294 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4295 {
4296         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4297         process_oq(pm8001_ha, vec);
4298         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4299         return IRQ_HANDLED;
4300 }
4301
4302 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4303         u32 operation, u32 phyid, u32 length, u32 *buf)
4304 {
4305         u32 tag , i, j = 0;
4306         int rc;
4307         struct set_phy_profile_req payload;
4308         struct inbound_queue_table *circularQ;
4309         u32 opc = OPC_INB_SET_PHY_PROFILE;
4310
4311         memset(&payload, 0, sizeof(payload));
4312         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4313         if (rc)
4314                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4315         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4316         payload.tag = cpu_to_le32(tag);
4317         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4318         PM8001_INIT_DBG(pm8001_ha,
4319                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4320                         payload.ppc_phyid, length));
4321         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4322                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4323                 j++;
4324         }
4325         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4326 }
4327
4328 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4329         u32 length, u8 *buf)
4330 {
4331         u32 page_code, i;
4332
4333         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4334         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4335                 mpi_set_phy_profile_req(pm8001_ha,
4336                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4337                 length = length + PHY_DWORD_LENGTH;
4338         }
4339         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4340 }
4341 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4342         .name                   = "pmc80xx",
4343         .chip_init              = pm80xx_chip_init,
4344         .chip_soft_rst          = pm80xx_chip_soft_rst,
4345         .chip_rst               = pm80xx_hw_chip_rst,
4346         .chip_iounmap           = pm8001_chip_iounmap,
4347         .isr                    = pm80xx_chip_isr,
4348         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4349         .isr_process_oq         = process_oq,
4350         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4351         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4352         .make_prd               = pm8001_chip_make_sg,
4353         .smp_req                = pm80xx_chip_smp_req,
4354         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4355         .sata_req               = pm80xx_chip_sata_req,
4356         .phy_start_req          = pm80xx_chip_phy_start_req,
4357         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4358         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4359         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4360         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4361         .task_abort             = pm8001_chip_abort_task,
4362         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4363         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4364         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4365         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4366         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4367 };