drivers/scsi/mpt3sas/mpt3sas_base.c

   1 /*
   2  * This is the Fusion MPT base driver providing common API layer interface
   3  * for access to MPT (Message Passing Technology) firmware.
   4  *
   5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
   6  * Copyright (C) 2012-2014  LSI Corporation
   7  * Copyright (C) 2013-2014 Avago Technologies
   8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * NO WARRANTY
  21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25  * solely responsible for determining the appropriateness of using and
  26  * distributing the Program and assumes all risks associated with its
  27  * exercise of rights under this Agreement, including but not limited to
  28  * the risks and costs of program errors, damage to or loss of data,
  29  * programs or equipment, and unavailability or interruption of operations.
  30
  31  * DISCLAIMER OF LIABILITY
  32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  43  * USA.
  44  */
  45
  46 #include <linux/kernel.h>
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/init.h>
  50 #include <linux/slab.h>
  51 #include <linux/types.h>
  52 #include <linux/pci.h>
  53 #include <linux/kdev_t.h>
  54 #include <linux/blkdev.h>
  55 #include <linux/delay.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/dma-mapping.h>
  58 #include <linux/io.h>
  59 #include <linux/time.h>
  60 #include <linux/kthread.h>
  61 #include <linux/aer.h>
  62
  63
  64 #include "mpt3sas_base.h"
  65
  66 static MPT_CALLBACK     mpt_callbacks[MPT_MAX_CALLBACKS];
  67
  68
  69 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  70
  71  /* maximum controller queue depth */
  72 #define MAX_HBA_QUEUE_DEPTH     30000
  73 #define MAX_CHAIN_DEPTH         100000
  74 static int max_queue_depth = -1;
  75 module_param(max_queue_depth, int, 0);
  76 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  77
  78 static int max_sgl_entries = -1;
  79 module_param(max_sgl_entries, int, 0);
  80 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  81
  82 static int msix_disable = -1;
  83 module_param(msix_disable, int, 0);
  84 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  85
  86 static int max_msix_vectors = -1;
  87 module_param(max_msix_vectors, int, 0);
  88 MODULE_PARM_DESC(max_msix_vectors,
  89         " max msix vectors");
  90
  91 static int mpt3sas_fwfault_debug;
  92 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
  93         " enable detection of firmware fault and halt firmware - (default=0)");
  94
  95 static int
  96 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
  97
  98 /**
  99  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
 100  *
 101  */
 102 static int
 103 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
 104 {
 105         int ret = param_set_int(val, kp);
 106         struct MPT3SAS_ADAPTER *ioc;
 107
 108         if (ret)
 109                 return ret;
 110
 111         /* global ioc spinlock to protect controller list on list operations */
 112         pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
 113         spin_lock(&gioc_lock);
 114         list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
 115                 ioc->fwfault_debug = mpt3sas_fwfault_debug;
 116         spin_unlock(&gioc_lock);
 117         return 0;
 118 }
 119 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
 120         param_get_int, &mpt3sas_fwfault_debug, 0644);
 121
 122 /**
 123  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
 124  * @arg: input argument, used to derive ioc
 125  *
 126  * Return 0 if controller is removed from pci subsystem.
 127  * Return -1 for other case.
 128  */
 129 static int mpt3sas_remove_dead_ioc_func(void *arg)
 130 {
 131         struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
 132         struct pci_dev *pdev;
 133
 134         if ((ioc == NULL))
 135                 return -1;
 136
 137         pdev = ioc->pdev;
 138         if ((pdev == NULL))
 139                 return -1;
 140         pci_stop_and_remove_bus_device_locked(pdev);
 141         return 0;
 142 }
 143
 144 /**
 145  * _base_fault_reset_work - workq handling ioc fault conditions
 146  * @work: input argument, used to derive ioc
 147  * Context: sleep.
 148  *
 149  * Return nothing.
 150  */
 151 static void
 152 _base_fault_reset_work(struct work_struct *work)
 153 {
 154         struct MPT3SAS_ADAPTER *ioc =
 155             container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
 156         unsigned long    flags;
 157         u32 doorbell;
 158         int rc;
 159         struct task_struct *p;
 160
 161
 162         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 163         if (ioc->shost_recovery || ioc->pci_error_recovery)
 164                 goto rearm_timer;
 165         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 166
 167         doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 168         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
 169                 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
 170                     ioc->name);
 171
 172                 /* It may be possible that EEH recovery can resolve some of
 173                  * pci bus failure issues rather removing the dead ioc function
 174                  * by considering controller is in a non-operational state. So
 175                  * here priority is given to the EEH recovery. If it doesn't
 176                  * not resolve this issue, mpt3sas driver will consider this
 177                  * controller to non-operational state and remove the dead ioc
 178                  * function.
 179                  */
 180                 if (ioc->non_operational_loop++ < 5) {
 181                         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
 182                                                          flags);
 183                         goto rearm_timer;
 184                 }
 185
 186                 /*
 187                  * Call _scsih_flush_pending_cmds callback so that we flush all
 188                  * pending commands back to OS. This call is required to aovid
 189                  * deadlock at block layer. Dead IOC will fail to do diag reset,
 190                  * and this call is safe since dead ioc will never return any
 191                  * command back from HW.
 192                  */
 193                 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
 194                 /*
 195                  * Set remove_host flag early since kernel thread will
 196                  * take some time to execute.
 197                  */
 198                 ioc->remove_host = 1;
 199                 /*Remove the Dead Host */
 200                 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
 201                     "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
 202                 if (IS_ERR(p))
 203                         pr_err(MPT3SAS_FMT
 204                         "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
 205                         ioc->name, __func__);
 206                 else
 207                         pr_err(MPT3SAS_FMT
 208                         "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
 209                         ioc->name, __func__);
 210                 return; /* don't rearm timer */
 211         }
 212
 213         ioc->non_operational_loop = 0;
 214
 215         if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
 216                 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
 217                     FORCE_BIG_HAMMER);
 218                 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
 219                     __func__, (rc == 0) ? "success" : "failed");
 220                 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 221                 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
 222                         mpt3sas_base_fault_info(ioc, doorbell &
 223                             MPI2_DOORBELL_DATA_MASK);
 224                 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
 225                     MPI2_IOC_STATE_OPERATIONAL)
 226                         return; /* don't rearm timer */
 227         }
 228
 229         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 230  rearm_timer:
 231         if (ioc->fault_reset_work_q)
 232                 queue_delayed_work(ioc->fault_reset_work_q,
 233                     &ioc->fault_reset_work,
 234                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 235         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 236 }
 237
 238 /**
 239  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
 240  * @ioc: per adapter object
 241  * Context: sleep.
 242  *
 243  * Return nothing.
 244  */
 245 void
 246 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
 247 {
 248         unsigned long    flags;
 249
 250         if (ioc->fault_reset_work_q)
 251                 return;
 252
 253         /* initialize fault polling */
 254
 255         INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
 256         snprintf(ioc->fault_reset_work_q_name,
 257             sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
 258             ioc->driver_name, ioc->id);
 259         ioc->fault_reset_work_q =
 260                 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
 261         if (!ioc->fault_reset_work_q) {
 262                 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
 263                     ioc->name, __func__, __LINE__);
 264                         return;
 265         }
 266         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 267         if (ioc->fault_reset_work_q)
 268                 queue_delayed_work(ioc->fault_reset_work_q,
 269                     &ioc->fault_reset_work,
 270                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 271         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 272 }
 273
 274 /**
 275  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
 276  * @ioc: per adapter object
 277  * Context: sleep.
 278  *
 279  * Return nothing.
 280  */
 281 void
 282 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
 283 {
 284         unsigned long flags;
 285         struct workqueue_struct *wq;
 286
 287         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 288         wq = ioc->fault_reset_work_q;
 289         ioc->fault_reset_work_q = NULL;
 290         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 291         if (wq) {
 292                 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
 293                         flush_workqueue(wq);
 294                 destroy_workqueue(wq);
 295         }
 296 }
 297
 298 /**
 299  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
 300  * @ioc: per adapter object
 301  * @fault_code: fault code
 302  *
 303  * Return nothing.
 304  */
 305 void
 306 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
 307 {
 308         pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
 309             ioc->name, fault_code);
 310 }
 311
 312 /**
 313  * mpt3sas_halt_firmware - halt's mpt controller firmware
 314  * @ioc: per adapter object
 315  *
 316  * For debugging timeout related issues.  Writing 0xCOFFEE00
 317  * to the doorbell register will halt controller firmware. With
 318  * the purpose to stop both driver and firmware, the enduser can
 319  * obtain a ring buffer from controller UART.
 320  */
 321 void
 322 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
 323 {
 324         u32 doorbell;
 325
 326         if (!ioc->fwfault_debug)
 327                 return;
 328
 329         dump_stack();
 330
 331         doorbell = readl(&ioc->chip->Doorbell);
 332         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
 333                 mpt3sas_base_fault_info(ioc , doorbell);
 334         else {
 335                 writel(0xC0FFEE00, &ioc->chip->Doorbell);
 336                 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
 337                         ioc->name);
 338         }
 339
 340         if (ioc->fwfault_debug == 2)
 341                 for (;;)
 342                         ;
 343         else
 344                 panic("panic in %s\n", __func__);
 345 }
 346
 347 /**
 348  * _base_sas_ioc_info - verbose translation of the ioc status
 349  * @ioc: per adapter object
 350  * @mpi_reply: reply mf payload returned from firmware
 351  * @request_hdr: request mf
 352  *
 353  * Return nothing.
 354  */
 355 static void
 356 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
 357         MPI2RequestHeader_t *request_hdr)
 358 {
 359         u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
 360             MPI2_IOCSTATUS_MASK;
 361         char *desc = NULL;
 362         u16 frame_sz;
 363         char *func_str = NULL;
 364
 365         /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
 366         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
 367             request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
 368             request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
 369                 return;
 370
 371         if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
 372                 return;
 373
 374         switch (ioc_status) {
 375
 376 /****************************************************************************
 377 *  Common IOCStatus values for all replies
 378 ****************************************************************************/
 379
 380         case MPI2_IOCSTATUS_INVALID_FUNCTION:
 381                 desc = "invalid function";
 382                 break;
 383         case MPI2_IOCSTATUS_BUSY:
 384                 desc = "busy";
 385                 break;
 386         case MPI2_IOCSTATUS_INVALID_SGL:
 387                 desc = "invalid sgl";
 388                 break;
 389         case MPI2_IOCSTATUS_INTERNAL_ERROR:
 390                 desc = "internal error";
 391                 break;
 392         case MPI2_IOCSTATUS_INVALID_VPID:
 393                 desc = "invalid vpid";
 394                 break;
 395         case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
 396                 desc = "insufficient resources";
 397                 break;
 398         case MPI2_IOCSTATUS_INVALID_FIELD:
 399                 desc = "invalid field";
 400                 break;
 401         case MPI2_IOCSTATUS_INVALID_STATE:
 402                 desc = "invalid state";
 403                 break;
 404         case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
 405                 desc = "op state not supported";
 406                 break;
 407
 408 /****************************************************************************
 409 *  Config IOCStatus values
 410 ****************************************************************************/
 411
 412         case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
 413                 desc = "config invalid action";
 414                 break;
 415         case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
 416                 desc = "config invalid type";
 417                 break;
 418         case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
 419                 desc = "config invalid page";
 420                 break;
 421         case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
 422                 desc = "config invalid data";
 423                 break;
 424         case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
 425                 desc = "config no defaults";
 426                 break;
 427         case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
 428                 desc = "config cant commit";
 429                 break;
 430
 431 /****************************************************************************
 432 *  SCSI IO Reply
 433 ****************************************************************************/
 434
 435         case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
 436         case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
 437         case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
 438         case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
 439         case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
 440         case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
 441         case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
 442         case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
 443         case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
 444         case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
 445         case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
 446         case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
 447                 break;
 448
 449 /****************************************************************************
 450 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
 451 ****************************************************************************/
 452
 453         case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
 454                 desc = "eedp guard error";
 455                 break;
 456         case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
 457                 desc = "eedp ref tag error";
 458                 break;
 459         case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
 460                 desc = "eedp app tag error";
 461                 break;
 462
 463 /****************************************************************************
 464 *  SCSI Target values
 465 ****************************************************************************/
 466
 467         case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
 468                 desc = "target invalid io index";
 469                 break;
 470         case MPI2_IOCSTATUS_TARGET_ABORTED:
 471                 desc = "target aborted";
 472                 break;
 473         case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
 474                 desc = "target no conn retryable";
 475                 break;
 476         case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
 477                 desc = "target no connection";
 478                 break;
 479         case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
 480                 desc = "target xfer count mismatch";
 481                 break;
 482         case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
 483                 desc = "target data offset error";
 484                 break;
 485         case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
 486                 desc = "target too much write data";
 487                 break;
 488         case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
 489                 desc = "target iu too short";
 490                 break;
 491         case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
 492                 desc = "target ack nak timeout";
 493                 break;
 494         case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
 495                 desc = "target nak received";
 496                 break;
 497
 498 /****************************************************************************
 499 *  Serial Attached SCSI values
 500 ****************************************************************************/
 501
 502         case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
 503                 desc = "smp request failed";
 504                 break;
 505         case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
 506                 desc = "smp data overrun";
 507                 break;
 508
 509 /****************************************************************************
 510 *  Diagnostic Buffer Post / Diagnostic Release values
 511 ****************************************************************************/
 512
 513         case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
 514                 desc = "diagnostic released";
 515                 break;
 516         default:
 517                 break;
 518         }
 519
 520         if (!desc)
 521                 return;
 522
 523         switch (request_hdr->Function) {
 524         case MPI2_FUNCTION_CONFIG:
 525                 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
 526                 func_str = "config_page";
 527                 break;
 528         case MPI2_FUNCTION_SCSI_TASK_MGMT:
 529                 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
 530                 func_str = "task_mgmt";
 531                 break;
 532         case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
 533                 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
 534                 func_str = "sas_iounit_ctl";
 535                 break;
 536         case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
 537                 frame_sz = sizeof(Mpi2SepRequest_t);
 538                 func_str = "enclosure";
 539                 break;
 540         case MPI2_FUNCTION_IOC_INIT:
 541                 frame_sz = sizeof(Mpi2IOCInitRequest_t);
 542                 func_str = "ioc_init";
 543                 break;
 544         case MPI2_FUNCTION_PORT_ENABLE:
 545                 frame_sz = sizeof(Mpi2PortEnableRequest_t);
 546                 func_str = "port_enable";
 547                 break;
 548         case MPI2_FUNCTION_SMP_PASSTHROUGH:
 549                 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
 550                 func_str = "smp_passthru";
 551                 break;
 552         default:
 553                 frame_sz = 32;
 554                 func_str = "unknown";
 555                 break;
 556         }
 557
 558         pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
 559                 ioc->name, desc, ioc_status, request_hdr, func_str);
 560
 561         _debug_dump_mf(request_hdr, frame_sz/4);
 562 }
 563
 564 /**
 565  * _base_display_event_data - verbose translation of firmware asyn events
 566  * @ioc: per adapter object
 567  * @mpi_reply: reply mf payload returned from firmware
 568  *
 569  * Return nothing.
 570  */
 571 static void
 572 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
 573         Mpi2EventNotificationReply_t *mpi_reply)
 574 {
 575         char *desc = NULL;
 576         u16 event;
 577
 578         if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
 579                 return;
 580
 581         event = le16_to_cpu(mpi_reply->Event);
 582
 583         switch (event) {
 584         case MPI2_EVENT_LOG_DATA:
 585                 desc = "Log Data";
 586                 break;
 587         case MPI2_EVENT_STATE_CHANGE:
 588                 desc = "Status Change";
 589                 break;
 590         case MPI2_EVENT_HARD_RESET_RECEIVED:
 591                 desc = "Hard Reset Received";
 592                 break;
 593         case MPI2_EVENT_EVENT_CHANGE:
 594                 desc = "Event Change";
 595                 break;
 596         case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
 597                 desc = "Device Status Change";
 598                 break;
 599         case MPI2_EVENT_IR_OPERATION_STATUS:
 600                 if (!ioc->hide_ir_msg)
 601                         desc = "IR Operation Status";
 602                 break;
 603         case MPI2_EVENT_SAS_DISCOVERY:
 604         {
 605                 Mpi2EventDataSasDiscovery_t *event_data =
 606                     (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
 607                 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
 608                     (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
 609                     "start" : "stop");
 610                 if (event_data->DiscoveryStatus)
 611                         pr_info("discovery_status(0x%08x)",
 612                             le32_to_cpu(event_data->DiscoveryStatus));
 613                         pr_info("\n");
 614                 return;
 615         }
 616         case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
 617                 desc = "SAS Broadcast Primitive";
 618                 break;
 619         case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 620                 desc = "SAS Init Device Status Change";
 621                 break;
 622         case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
 623                 desc = "SAS Init Table Overflow";
 624                 break;
 625         case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 626                 desc = "SAS Topology Change List";
 627                 break;
 628         case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
 629                 desc = "SAS Enclosure Device Status Change";
 630                 break;
 631         case MPI2_EVENT_IR_VOLUME:
 632                 if (!ioc->hide_ir_msg)
 633                         desc = "IR Volume";
 634                 break;
 635         case MPI2_EVENT_IR_PHYSICAL_DISK:
 636                 if (!ioc->hide_ir_msg)
 637                         desc = "IR Physical Disk";
 638                 break;
 639         case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
 640                 if (!ioc->hide_ir_msg)
 641                         desc = "IR Configuration Change List";
 642                 break;
 643         case MPI2_EVENT_LOG_ENTRY_ADDED:
 644                 if (!ioc->hide_ir_msg)
 645                         desc = "Log Entry Added";
 646                 break;
 647         case MPI2_EVENT_TEMP_THRESHOLD:
 648                 desc = "Temperature Threshold";
 649                 break;
 650         }
 651
 652         if (!desc)
 653                 return;
 654
 655         pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
 656 }
 657
 658 /**
 659  * _base_sas_log_info - verbose translation of firmware log info
 660  * @ioc: per adapter object
 661  * @log_info: log info
 662  *
 663  * Return nothing.
 664  */
 665 static void
 666 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
 667 {
 668         union loginfo_type {
 669                 u32     loginfo;
 670                 struct {
 671                         u32     subcode:16;
 672                         u32     code:8;
 673                         u32     originator:4;
 674                         u32     bus_type:4;
 675                 } dw;
 676         };
 677         union loginfo_type sas_loginfo;
 678         char *originator_str = NULL;
 679
 680         sas_loginfo.loginfo = log_info;
 681         if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
 682                 return;
 683
 684         /* each nexus loss loginfo */
 685         if (log_info == 0x31170000)
 686                 return;
 687
 688         /* eat the loginfos associated with task aborts */
 689         if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
 690             0x31140000 || log_info == 0x31130000))
 691                 return;
 692
 693         switch (sas_loginfo.dw.originator) {
 694         case 0:
 695                 originator_str = "IOP";
 696                 break;
 697         case 1:
 698                 originator_str = "PL";
 699                 break;
 700         case 2:
 701                 if (!ioc->hide_ir_msg)
 702                         originator_str = "IR";
 703                 else
 704                         originator_str = "WarpDrive";
 705                 break;
 706         }
 707
 708         pr_warn(MPT3SAS_FMT
 709                 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
 710                 ioc->name, log_info,
 711              originator_str, sas_loginfo.dw.code,
 712              sas_loginfo.dw.subcode);
 713 }
 714
 715 /**
 716  * _base_display_reply_info -
 717  * @ioc: per adapter object
 718  * @smid: system request message index
 719  * @msix_index: MSIX table index supplied by the OS
 720  * @reply: reply message frame(lower 32bit addr)
 721  *
 722  * Return nothing.
 723  */
 724 static void
 725 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
 726         u32 reply)
 727 {
 728         MPI2DefaultReply_t *mpi_reply;
 729         u16 ioc_status;
 730         u32 loginfo = 0;
 731
 732         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 733         if (unlikely(!mpi_reply)) {
 734                 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
 735                     ioc->name, __FILE__, __LINE__, __func__);
 736                 return;
 737         }
 738         ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
 739
 740         if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
 741             (ioc->logging_level & MPT_DEBUG_REPLY)) {
 742                 _base_sas_ioc_info(ioc , mpi_reply,
 743                    mpt3sas_base_get_msg_frame(ioc, smid));
 744         }
 745
 746         if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
 747                 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
 748                 _base_sas_log_info(ioc, loginfo);
 749         }
 750
 751         if (ioc_status || loginfo) {
 752                 ioc_status &= MPI2_IOCSTATUS_MASK;
 753                 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
 754         }
 755 }
 756
 757 /**
 758  * mpt3sas_base_done - base internal command completion routine
 759  * @ioc: per adapter object
 760  * @smid: system request message index
 761  * @msix_index: MSIX table index supplied by the OS
 762  * @reply: reply message frame(lower 32bit addr)
 763  *
 764  * Return 1 meaning mf should be freed from _base_interrupt
 765  *        0 means the mf is freed from this function.
 766  */
 767 u8
 768 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
 769         u32 reply)
 770 {
 771         MPI2DefaultReply_t *mpi_reply;
 772
 773         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 774         if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
 775                 return 1;
 776
 777         if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
 778                 return 1;
 779
 780         ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
 781         if (mpi_reply) {
 782                 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
 783                 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
 784         }
 785         ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
 786
 787         complete(&ioc->base_cmds.done);
 788         return 1;
 789 }
 790
 791 /**
 792  * _base_async_event - main callback handler for firmware asyn events
 793  * @ioc: per adapter object
 794  * @msix_index: MSIX table index supplied by the OS
 795  * @reply: reply message frame(lower 32bit addr)
 796  *
 797  * Return 1 meaning mf should be freed from _base_interrupt
 798  *        0 means the mf is freed from this function.
 799  */
 800 static u8
 801 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
 802 {
 803         Mpi2EventNotificationReply_t *mpi_reply;
 804         Mpi2EventAckRequest_t *ack_request;
 805         u16 smid;
 806
 807         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 808         if (!mpi_reply)
 809                 return 1;
 810         if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
 811                 return 1;
 812
 813         _base_display_event_data(ioc, mpi_reply);
 814
 815         if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
 816                 goto out;
 817         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
 818         if (!smid) {
 819                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
 820                     ioc->name, __func__);
 821                 goto out;
 822         }
 823
 824         ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
 825         memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
 826         ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
 827         ack_request->Event = mpi_reply->Event;
 828         ack_request->EventContext = mpi_reply->EventContext;
 829         ack_request->VF_ID = 0;  /* TODO */
 830         ack_request->VP_ID = 0;
 831         mpt3sas_base_put_smid_default(ioc, smid);
 832
 833  out:
 834
 835         /* scsih callback handler */
 836         mpt3sas_scsih_event_callback(ioc, msix_index, reply);
 837
 838         /* ctl callback handler */
 839         mpt3sas_ctl_event_callback(ioc, msix_index, reply);
 840
 841         return 1;
 842 }
 843
 844 /**
 845  * _base_get_cb_idx - obtain the callback index
 846  * @ioc: per adapter object
 847  * @smid: system request message index
 848  *
 849  * Return callback index.
 850  */
 851 static u8
 852 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 853 {
 854         int i;
 855         u8 cb_idx;
 856
 857         if (smid < ioc->hi_priority_smid) {
 858                 i = smid - 1;
 859                 cb_idx = ioc->scsi_lookup[i].cb_idx;
 860         } else if (smid < ioc->internal_smid) {
 861                 i = smid - ioc->hi_priority_smid;
 862                 cb_idx = ioc->hpr_lookup[i].cb_idx;
 863         } else if (smid <= ioc->hba_queue_depth) {
 864                 i = smid - ioc->internal_smid;
 865                 cb_idx = ioc->internal_lookup[i].cb_idx;
 866         } else
 867                 cb_idx = 0xFF;
 868         return cb_idx;
 869 }
 870
 871 /**
 872  * _base_mask_interrupts - disable interrupts
 873  * @ioc: per adapter object
 874  *
 875  * Disabling ResetIRQ, Reply and Doorbell Interrupts
 876  *
 877  * Return nothing.
 878  */
 879 static void
 880 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
 881 {
 882         u32 him_register;
 883
 884         ioc->mask_interrupts = 1;
 885         him_register = readl(&ioc->chip->HostInterruptMask);
 886         him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
 887         writel(him_register, &ioc->chip->HostInterruptMask);
 888         readl(&ioc->chip->HostInterruptMask);
 889 }
 890
 891 /**
 892  * _base_unmask_interrupts - enable interrupts
 893  * @ioc: per adapter object
 894  *
 895  * Enabling only Reply Interrupts
 896  *
 897  * Return nothing.
 898  */
 899 static void
 900 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
 901 {
 902         u32 him_register;
 903
 904         him_register = readl(&ioc->chip->HostInterruptMask);
 905         him_register &= ~MPI2_HIM_RIM;
 906         writel(him_register, &ioc->chip->HostInterruptMask);
 907         ioc->mask_interrupts = 0;
 908 }
 909
 910 union reply_descriptor {
 911         u64 word;
 912         struct {
 913                 u32 low;
 914                 u32 high;
 915         } u;
 916 };
 917
 918 /**
 919  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
 920  * @irq: irq number (not used)
 921  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
 922  * @r: pt_regs pointer (not used)
 923  *
 924  * Return IRQ_HANDLE if processed, else IRQ_NONE.
 925  */
 926 static irqreturn_t
 927 _base_interrupt(int irq, void *bus_id)
 928 {
 929         struct adapter_reply_queue *reply_q = bus_id;
 930         union reply_descriptor rd;
 931         u32 completed_cmds;
 932         u8 request_desript_type;
 933         u16 smid;
 934         u8 cb_idx;
 935         u32 reply;
 936         u8 msix_index = reply_q->msix_index;
 937         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
 938         Mpi2ReplyDescriptorsUnion_t *rpf;
 939         u8 rc;
 940
 941         if (ioc->mask_interrupts)
 942                 return IRQ_NONE;
 943
 944         if (!atomic_add_unless(&reply_q->busy, 1, 1))
 945                 return IRQ_NONE;
 946
 947         rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
 948         request_desript_type = rpf->Default.ReplyFlags
 949              & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
 950         if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
 951                 atomic_dec(&reply_q->busy);
 952                 return IRQ_NONE;
 953         }
 954
 955         completed_cmds = 0;
 956         cb_idx = 0xFF;
 957         do {
 958                 rd.word = le64_to_cpu(rpf->Words);
 959                 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
 960                         goto out;
 961                 reply = 0;
 962                 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
 963                 if (request_desript_type ==
 964                     MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
 965                     request_desript_type ==
 966                     MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
 967                         cb_idx = _base_get_cb_idx(ioc, smid);
 968                         if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
 969                             (likely(mpt_callbacks[cb_idx] != NULL))) {
 970                                 rc = mpt_callbacks[cb_idx](ioc, smid,
 971                                     msix_index, 0);
 972                                 if (rc)
 973                                         mpt3sas_base_free_smid(ioc, smid);
 974                         }
 975                 } else if (request_desript_type ==
 976                     MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
 977                         reply = le32_to_cpu(
 978                             rpf->AddressReply.ReplyFrameAddress);
 979                         if (reply > ioc->reply_dma_max_address ||
 980                             reply < ioc->reply_dma_min_address)
 981                                 reply = 0;
 982                         if (smid) {
 983                                 cb_idx = _base_get_cb_idx(ioc, smid);
 984                                 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
 985                                     (likely(mpt_callbacks[cb_idx] != NULL))) {
 986                                         rc = mpt_callbacks[cb_idx](ioc, smid,
 987                                             msix_index, reply);
 988                                         if (reply)
 989                                                 _base_display_reply_info(ioc,
 990                                                     smid, msix_index, reply);
 991                                         if (rc)
 992                                                 mpt3sas_base_free_smid(ioc,
 993                                                     smid);
 994                                 }
 995                         } else {
 996                                 _base_async_event(ioc, msix_index, reply);
 997                         }
 998
 999                         /* reply free queue handling */
1000                         if (reply) {
1001                                 ioc->reply_free_host_index =
1002                                     (ioc->reply_free_host_index ==
1003                                     (ioc->reply_free_queue_depth - 1)) ?
1004                                     0 : ioc->reply_free_host_index + 1;
1005                                 ioc->reply_free[ioc->reply_free_host_index] =
1006                                     cpu_to_le32(reply);
1007                                 wmb();
1008                                 writel(ioc->reply_free_host_index,
1009                                     &ioc->chip->ReplyFreeHostIndex);
1010                         }
1011                 }
1012
1013                 rpf->Words = cpu_to_le64(ULLONG_MAX);
1014                 reply_q->reply_post_host_index =
1015                     (reply_q->reply_post_host_index ==
1016                     (ioc->reply_post_queue_depth - 1)) ? 0 :
1017                     reply_q->reply_post_host_index + 1;
1018                 request_desript_type =
1019                     reply_q->reply_post_free[reply_q->reply_post_host_index].
1020                     Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1021                 completed_cmds++;
1022                 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1023                         goto out;
1024                 if (!reply_q->reply_post_host_index)
1025                         rpf = reply_q->reply_post_free;
1026                 else
1027                         rpf++;
1028         } while (1);
1029
1030  out:
1031
1032         if (!completed_cmds) {
1033                 atomic_dec(&reply_q->busy);
1034                 return IRQ_NONE;
1035         }
1036
1037         wmb();
1038         if (ioc->is_warpdrive) {
1039                 writel(reply_q->reply_post_host_index,
1040                 ioc->reply_post_host_index[msix_index]);
1041                 atomic_dec(&reply_q->busy);
1042                 return IRQ_HANDLED;
1043         }
1044
1045         /* Update Reply Post Host Index.
1046          * For those HBA's which support combined reply queue feature
1047          * 1. Get the correct Supplemental Reply Post Host Index Register.
1048          *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1049          *    Index Register address bank i.e replyPostRegisterIndex[],
1050          * 2. Then update this register with new reply host index value
1051          *    in ReplyPostIndex field and the MSIxIndex field with
1052          *    msix_index value reduced to a value between 0 and 7,
1053          *    using a modulo 8 operation. Since each Supplemental Reply Post
1054          *    Host Index Register supports 8 MSI-X vectors.
1055          *
1056          * For other HBA's just update the Reply Post Host Index register with
1057          * new reply host index value in ReplyPostIndex Field and msix_index
1058          * value in MSIxIndex field.
1059          */
1060         if (ioc->msix96_vector)
1061                 writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1062                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1063                         ioc->replyPostRegisterIndex[msix_index/8]);
1064         else
1065                 writel(reply_q->reply_post_host_index | (msix_index <<
1066                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1067                         &ioc->chip->ReplyPostHostIndex);
1068         atomic_dec(&reply_q->busy);
1069         return IRQ_HANDLED;
1070 }
1071
1072 /**
1073  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1074  * @ioc: per adapter object
1075  *
1076  */
1077 static inline int
1078 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1079 {
1080         return (ioc->facts.IOCCapabilities &
1081             MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1082 }
1083
1084 /**
1085  * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1086  * @ioc: per adapter object
1087  * Context: ISR conext
1088  *
1089  * Called when a Task Management request has completed. We want
1090  * to flush the other reply queues so all the outstanding IO has been
1091  * completed back to OS before we process the TM completetion.
1092  *
1093  * Return nothing.
1094  */
1095 void
1096 mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1097 {
1098         struct adapter_reply_queue *reply_q;
1099
1100         /* If MSIX capability is turned off
1101          * then multi-queues are not enabled
1102          */
1103         if (!_base_is_controller_msix_enabled(ioc))
1104                 return;
1105
1106         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1107                 if (ioc->shost_recovery)
1108                         return;
1109                 /* TMs are on msix_index == 0 */
1110                 if (reply_q->msix_index == 0)
1111                         continue;
1112                 _base_interrupt(reply_q->vector, (void *)reply_q);
1113         }
1114 }
1115
1116 /**
1117  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1118  * @cb_idx: callback index
1119  *
1120  * Return nothing.
1121  */
1122 void
1123 mpt3sas_base_release_callback_handler(u8 cb_idx)
1124 {
1125         mpt_callbacks[cb_idx] = NULL;
1126 }
1127
1128 /**
1129  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1130  * @cb_func: callback function
1131  *
1132  * Returns cb_func.
1133  */
1134 u8
1135 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1136 {
1137         u8 cb_idx;
1138
1139         for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1140                 if (mpt_callbacks[cb_idx] == NULL)
1141                         break;
1142
1143         mpt_callbacks[cb_idx] = cb_func;
1144         return cb_idx;
1145 }
1146
1147 /**
1148  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1149  *
1150  * Return nothing.
1151  */
1152 void
1153 mpt3sas_base_initialize_callback_handler(void)
1154 {
1155         u8 cb_idx;
1156
1157         for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1158                 mpt3sas_base_release_callback_handler(cb_idx);
1159 }
1160
1161
1162 /**
1163  * _base_build_zero_len_sge - build zero length sg entry
1164  * @ioc: per adapter object
1165  * @paddr: virtual address for SGE
1166  *
1167  * Create a zero length scatter gather entry to insure the IOCs hardware has
1168  * something to use if the target device goes brain dead and tries
1169  * to send data even when none is asked for.
1170  *
1171  * Return nothing.
1172  */
1173 static void
1174 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1175 {
1176         u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1177             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1178             MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1179             MPI2_SGE_FLAGS_SHIFT);
1180         ioc->base_add_sg_single(paddr, flags_length, -1);
1181 }
1182
1183 /**
1184  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1185  * @paddr: virtual address for SGE
1186  * @flags_length: SGE flags and data transfer length
1187  * @dma_addr: Physical address
1188  *
1189  * Return nothing.
1190  */
1191 static void
1192 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1193 {
1194         Mpi2SGESimple32_t *sgel = paddr;
1195
1196         flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1197             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1198         sgel->FlagsLength = cpu_to_le32(flags_length);
1199         sgel->Address = cpu_to_le32(dma_addr);
1200 }
1201
1202
1203 /**
1204  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1205  * @paddr: virtual address for SGE
1206  * @flags_length: SGE flags and data transfer length
1207  * @dma_addr: Physical address
1208  *
1209  * Return nothing.
1210  */
1211 static void
1212 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1213 {
1214         Mpi2SGESimple64_t *sgel = paddr;
1215
1216         flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1217             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1218         sgel->FlagsLength = cpu_to_le32(flags_length);
1219         sgel->Address = cpu_to_le64(dma_addr);
1220 }
1221
1222 /**
1223  * _base_get_chain_buffer_tracker - obtain chain tracker
1224  * @ioc: per adapter object
1225  * @smid: smid associated to an IO request
1226  *
1227  * Returns chain tracker(from ioc->free_chain_list)
1228  */
1229 static struct chain_tracker *
1230 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1231 {
1232         struct chain_tracker *chain_req;
1233         unsigned long flags;
1234
1235         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1236         if (list_empty(&ioc->free_chain_list)) {
1237                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1238                 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1239                         "chain buffers not available\n", ioc->name));
1240                 return NULL;
1241         }
1242         chain_req = list_entry(ioc->free_chain_list.next,
1243             struct chain_tracker, tracker_list);
1244         list_del_init(&chain_req->tracker_list);
1245         list_add_tail(&chain_req->tracker_list,
1246             &ioc->scsi_lookup[smid - 1].chain_list);
1247         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1248         return chain_req;
1249 }
1250
1251
1252 /**
1253  * _base_build_sg - build generic sg
1254  * @ioc: per adapter object
1255  * @psge: virtual address for SGE
1256  * @data_out_dma: physical address for WRITES
1257  * @data_out_sz: data xfer size for WRITES
1258  * @data_in_dma: physical address for READS
1259  * @data_in_sz: data xfer size for READS
1260  *
1261  * Return nothing.
1262  */
1263 static void
1264 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1265         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1266         size_t data_in_sz)
1267 {
1268         u32 sgl_flags;
1269
1270         if (!data_out_sz && !data_in_sz) {
1271                 _base_build_zero_len_sge(ioc, psge);
1272                 return;
1273         }
1274
1275         if (data_out_sz && data_in_sz) {
1276                 /* WRITE sgel first */
1277                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1278                     MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1279                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1280                 ioc->base_add_sg_single(psge, sgl_flags |
1281                     data_out_sz, data_out_dma);
1282
1283                 /* incr sgel */
1284                 psge += ioc->sge_size;
1285
1286                 /* READ sgel last */
1287                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1288                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1289                     MPI2_SGE_FLAGS_END_OF_LIST);
1290                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1291                 ioc->base_add_sg_single(psge, sgl_flags |
1292                     data_in_sz, data_in_dma);
1293         } else if (data_out_sz) /* WRITE */ {
1294                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1295                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1296                     MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1297                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1298                 ioc->base_add_sg_single(psge, sgl_flags |
1299                     data_out_sz, data_out_dma);
1300         } else if (data_in_sz) /* READ */ {
1301                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1302                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1303                     MPI2_SGE_FLAGS_END_OF_LIST);
1304                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1305                 ioc->base_add_sg_single(psge, sgl_flags |
1306                     data_in_sz, data_in_dma);
1307         }
1308 }
1309
1310 /* IEEE format sgls */
1311
1312 /**
1313  * _base_add_sg_single_ieee - add sg element for IEEE format
1314  * @paddr: virtual address for SGE
1315  * @flags: SGE flags
1316  * @chain_offset: number of 128 byte elements from start of segment
1317  * @length: data transfer length
1318  * @dma_addr: Physical address
1319  *
1320  * Return nothing.
1321  */
1322 static void
1323 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1324         dma_addr_t dma_addr)
1325 {
1326         Mpi25IeeeSgeChain64_t *sgel = paddr;
1327
1328         sgel->Flags = flags;
1329         sgel->NextChainOffset = chain_offset;
1330         sgel->Length = cpu_to_le32(length);
1331         sgel->Address = cpu_to_le64(dma_addr);
1332 }
1333
1334 /**
1335  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1336  * @ioc: per adapter object
1337  * @paddr: virtual address for SGE
1338  *
1339  * Create a zero length scatter gather entry to insure the IOCs hardware has
1340  * something to use if the target device goes brain dead and tries
1341  * to send data even when none is asked for.
1342  *
1343  * Return nothing.
1344  */
1345 static void
1346 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1347 {
1348         u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1349                 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1350                 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1351         _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1352 }
1353
1354 /**
1355  * _base_build_sg_scmd - main sg creation routine
1356  * @ioc: per adapter object
1357  * @scmd: scsi command
1358  * @smid: system request message index
1359  * Context: none.
1360  *
1361  * The main routine that builds scatter gather table from a given
1362  * scsi request sent via the .queuecommand main handler.
1363  *
1364  * Returns 0 success, anything else error
1365  */
1366 static int
1367 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1368                 struct scsi_cmnd *scmd, u16 smid)
1369 {
1370         Mpi2SCSIIORequest_t *mpi_request;
1371         dma_addr_t chain_dma;
1372         struct scatterlist *sg_scmd;
1373         void *sg_local, *chain;
1374         u32 chain_offset;
1375         u32 chain_length;
1376         u32 chain_flags;
1377         int sges_left;
1378         u32 sges_in_segment;
1379         u32 sgl_flags;
1380         u32 sgl_flags_last_element;
1381         u32 sgl_flags_end_buffer;
1382         struct chain_tracker *chain_req;
1383
1384         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1385
1386         /* init scatter gather flags */
1387         sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1388         if (scmd->sc_data_direction == DMA_TO_DEVICE)
1389                 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1390         sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1391             << MPI2_SGE_FLAGS_SHIFT;
1392         sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1393             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1394             << MPI2_SGE_FLAGS_SHIFT;
1395         sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1396
1397         sg_scmd = scsi_sglist(scmd);
1398         sges_left = scsi_dma_map(scmd);
1399         if (sges_left < 0) {
1400                 sdev_printk(KERN_ERR, scmd->device,
1401                  "pci_map_sg failed: request for %d bytes!\n",
1402                  scsi_bufflen(scmd));
1403                 return -ENOMEM;
1404         }
1405
1406         sg_local = &mpi_request->SGL;
1407         sges_in_segment = ioc->max_sges_in_main_message;
1408         if (sges_left <= sges_in_segment)
1409                 goto fill_in_last_segment;
1410
1411         mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1412             (sges_in_segment * ioc->sge_size))/4;
1413
1414         /* fill in main message segment when there is a chain following */
1415         while (sges_in_segment) {
1416                 if (sges_in_segment == 1)
1417                         ioc->base_add_sg_single(sg_local,
1418                             sgl_flags_last_element | sg_dma_len(sg_scmd),
1419                             sg_dma_address(sg_scmd));
1420                 else
1421                         ioc->base_add_sg_single(sg_local, sgl_flags |
1422                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1423                 sg_scmd = sg_next(sg_scmd);
1424                 sg_local += ioc->sge_size;
1425                 sges_left--;
1426                 sges_in_segment--;
1427         }
1428
1429         /* initializing the chain flags and pointers */
1430         chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1431         chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1432         if (!chain_req)
1433                 return -1;
1434         chain = chain_req->chain_buffer;
1435         chain_dma = chain_req->chain_buffer_dma;
1436         do {
1437                 sges_in_segment = (sges_left <=
1438                     ioc->max_sges_in_chain_message) ? sges_left :
1439                     ioc->max_sges_in_chain_message;
1440                 chain_offset = (sges_left == sges_in_segment) ?
1441                     0 : (sges_in_segment * ioc->sge_size)/4;
1442                 chain_length = sges_in_segment * ioc->sge_size;
1443                 if (chain_offset) {
1444                         chain_offset = chain_offset <<
1445                             MPI2_SGE_CHAIN_OFFSET_SHIFT;
1446                         chain_length += ioc->sge_size;
1447                 }
1448                 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1449                     chain_length, chain_dma);
1450                 sg_local = chain;
1451                 if (!chain_offset)
1452                         goto fill_in_last_segment;
1453
1454                 /* fill in chain segments */
1455                 while (sges_in_segment) {
1456                         if (sges_in_segment == 1)
1457                                 ioc->base_add_sg_single(sg_local,
1458                                     sgl_flags_last_element |
1459                                     sg_dma_len(sg_scmd),
1460                                     sg_dma_address(sg_scmd));
1461                         else
1462                                 ioc->base_add_sg_single(sg_local, sgl_flags |
1463                                     sg_dma_len(sg_scmd),
1464                                     sg_dma_address(sg_scmd));
1465                         sg_scmd = sg_next(sg_scmd);
1466                         sg_local += ioc->sge_size;
1467                         sges_left--;
1468                         sges_in_segment--;
1469                 }
1470
1471                 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1472                 if (!chain_req)
1473                         return -1;
1474                 chain = chain_req->chain_buffer;
1475                 chain_dma = chain_req->chain_buffer_dma;
1476         } while (1);
1477
1478
1479  fill_in_last_segment:
1480
1481         /* fill the last segment */
1482         while (sges_left) {
1483                 if (sges_left == 1)
1484                         ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1485                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1486                 else
1487                         ioc->base_add_sg_single(sg_local, sgl_flags |
1488                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1489                 sg_scmd = sg_next(sg_scmd);
1490                 sg_local += ioc->sge_size;
1491                 sges_left--;
1492         }
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1499  * @ioc: per adapter object
1500  * @scmd: scsi command
1501  * @smid: system request message index
1502  * Context: none.
1503  *
1504  * The main routine that builds scatter gather table from a given
1505  * scsi request sent via the .queuecommand main handler.
1506  *
1507  * Returns 0 success, anything else error
1508  */
1509 static int
1510 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1511         struct scsi_cmnd *scmd, u16 smid)
1512 {
1513         Mpi2SCSIIORequest_t *mpi_request;
1514         dma_addr_t chain_dma;
1515         struct scatterlist *sg_scmd;
1516         void *sg_local, *chain;
1517         u32 chain_offset;
1518         u32 chain_length;
1519         int sges_left;
1520         u32 sges_in_segment;
1521         u8 simple_sgl_flags;
1522         u8 simple_sgl_flags_last;
1523         u8 chain_sgl_flags;
1524         struct chain_tracker *chain_req;
1525
1526         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1527
1528         /* init scatter gather flags */
1529         simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1530             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1531         simple_sgl_flags_last = simple_sgl_flags |
1532             MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1533         chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1534             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1535
1536         sg_scmd = scsi_sglist(scmd);
1537         sges_left = scsi_dma_map(scmd);
1538         if (sges_left < 0) {
1539                 sdev_printk(KERN_ERR, scmd->device,
1540                         "pci_map_sg failed: request for %d bytes!\n",
1541                         scsi_bufflen(scmd));
1542                 return -ENOMEM;
1543         }
1544
1545         sg_local = &mpi_request->SGL;
1546         sges_in_segment = (ioc->request_sz -
1547             offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1548         if (sges_left <= sges_in_segment)
1549                 goto fill_in_last_segment;
1550
1551         mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1552             (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1553
1554         /* fill in main message segment when there is a chain following */
1555         while (sges_in_segment > 1) {
1556                 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1557                     sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1558                 sg_scmd = sg_next(sg_scmd);
1559                 sg_local += ioc->sge_size_ieee;
1560                 sges_left--;
1561                 sges_in_segment--;
1562         }
1563
1564         /* initializing the pointers */
1565         chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1566         if (!chain_req)
1567                 return -1;
1568         chain = chain_req->chain_buffer;
1569         chain_dma = chain_req->chain_buffer_dma;
1570         do {
1571                 sges_in_segment = (sges_left <=
1572                     ioc->max_sges_in_chain_message) ? sges_left :
1573                     ioc->max_sges_in_chain_message;
1574                 chain_offset = (sges_left == sges_in_segment) ?
1575                     0 : sges_in_segment;
1576                 chain_length = sges_in_segment * ioc->sge_size_ieee;
1577                 if (chain_offset)
1578                         chain_length += ioc->sge_size_ieee;
1579                 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1580                     chain_offset, chain_length, chain_dma);
1581
1582                 sg_local = chain;
1583                 if (!chain_offset)
1584                         goto fill_in_last_segment;
1585
1586                 /* fill in chain segments */
1587                 while (sges_in_segment) {
1588                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1589                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1590                         sg_scmd = sg_next(sg_scmd);
1591                         sg_local += ioc->sge_size_ieee;
1592                         sges_left--;
1593                         sges_in_segment--;
1594                 }
1595
1596                 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1597                 if (!chain_req)
1598                         return -1;
1599                 chain = chain_req->chain_buffer;
1600                 chain_dma = chain_req->chain_buffer_dma;
1601         } while (1);
1602
1603
1604  fill_in_last_segment:
1605
1606         /* fill the last segment */
1607         while (sges_left > 0) {
1608                 if (sges_left == 1)
1609                         _base_add_sg_single_ieee(sg_local,
1610                             simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1611                             sg_dma_address(sg_scmd));
1612                 else
1613                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1614                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1615                 sg_scmd = sg_next(sg_scmd);
1616                 sg_local += ioc->sge_size_ieee;
1617                 sges_left--;
1618         }
1619
1620         return 0;
1621 }
1622
1623 /**
1624  * _base_build_sg_ieee - build generic sg for IEEE format
1625  * @ioc: per adapter object
1626  * @psge: virtual address for SGE
1627  * @data_out_dma: physical address for WRITES
1628  * @data_out_sz: data xfer size for WRITES
1629  * @data_in_dma: physical address for READS
1630  * @data_in_sz: data xfer size for READS
1631  *
1632  * Return nothing.
1633  */
1634 static void
1635 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1636         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1637         size_t data_in_sz)
1638 {
1639         u8 sgl_flags;
1640
1641         if (!data_out_sz && !data_in_sz) {
1642                 _base_build_zero_len_sge_ieee(ioc, psge);
1643                 return;
1644         }
1645
1646         if (data_out_sz && data_in_sz) {
1647                 /* WRITE sgel first */
1648                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1649                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1650                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1651                     data_out_dma);
1652
1653                 /* incr sgel */
1654                 psge += ioc->sge_size_ieee;
1655
1656                 /* READ sgel last */
1657                 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1658                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1659                     data_in_dma);
1660         } else if (data_out_sz) /* WRITE */ {
1661                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1662                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1663                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1664                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1665                     data_out_dma);
1666         } else if (data_in_sz) /* READ */ {
1667                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1668                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1669                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1670                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1671                     data_in_dma);
1672         }
1673 }
1674
1675 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1676
1677 /**
1678  * _base_config_dma_addressing - set dma addressing
1679  * @ioc: per adapter object
1680  * @pdev: PCI device struct
1681  *
1682  * Returns 0 for success, non-zero for failure.
1683  */
1684 static int
1685 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1686 {
1687         struct sysinfo s;
1688         u64 consistent_dma_mask;
1689
1690         if (ioc->dma_mask)
1691                 consistent_dma_mask = DMA_BIT_MASK(64);
1692         else
1693                 consistent_dma_mask = DMA_BIT_MASK(32);
1694
1695         if (sizeof(dma_addr_t) > 4) {
1696                 const uint64_t required_mask =
1697                     dma_get_required_mask(&pdev->dev);
1698                 if ((required_mask > DMA_BIT_MASK(32)) &&
1699                     !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1700                     !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1701                         ioc->base_add_sg_single = &_base_add_sg_single_64;
1702                         ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1703                         ioc->dma_mask = 64;
1704                         goto out;
1705                 }
1706         }
1707
1708         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1709             && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1710                 ioc->base_add_sg_single = &_base_add_sg_single_32;
1711                 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1712                 ioc->dma_mask = 32;
1713         } else
1714                 return -ENODEV;
1715
1716  out:
1717         si_meminfo(&s);
1718         pr_info(MPT3SAS_FMT
1719                 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1720                 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1721
1722         return 0;
1723 }
1724
1725 static int
1726 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1727                                       struct pci_dev *pdev)
1728 {
1729         if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1730                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1731                         return -ENODEV;
1732         }
1733         return 0;
1734 }
1735
1736 /**
1737  * _base_check_enable_msix - checks MSIX capabable.
1738  * @ioc: per adapter object
1739  *
1740  * Check to see if card is capable of MSIX, and set number
1741  * of available msix vectors
1742  */
1743 static int
1744 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1745 {
1746         int base;
1747         u16 message_control;
1748
1749         /* Check whether controller SAS2008 B0 controller,
1750          * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1751          */
1752         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1753             ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1754                 return -EINVAL;
1755         }
1756
1757         base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1758         if (!base) {
1759                 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1760                         ioc->name));
1761                 return -EINVAL;
1762         }
1763
1764         /* get msix vector count */
1765         /* NUMA_IO not supported for older controllers */
1766         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1767             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1768             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1769             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1770             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1771             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1772             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1773                 ioc->msix_vector_count = 1;
1774         else {
1775                 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1776                 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1777         }
1778         dinitprintk(ioc, pr_info(MPT3SAS_FMT
1779                 "msix is supported, vector_count(%d)\n",
1780                 ioc->name, ioc->msix_vector_count));
1781         return 0;
1782 }
1783
1784 /**
1785  * _base_free_irq - free irq
1786  * @ioc: per adapter object
1787  *
1788  * Freeing respective reply_queue from the list.
1789  */
1790 static void
1791 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1792 {
1793         struct adapter_reply_queue *reply_q, *next;
1794
1795         if (list_empty(&ioc->reply_queue_list))
1796                 return;
1797
1798         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1799                 list_del(&reply_q->list);
1800                 irq_set_affinity_hint(reply_q->vector, NULL);
1801                 free_cpumask_var(reply_q->affinity_hint);
1802                 synchronize_irq(reply_q->vector);
1803                 free_irq(reply_q->vector, reply_q);
1804                 kfree(reply_q);
1805         }
1806 }
1807
1808 /**
1809  * _base_request_irq - request irq
1810  * @ioc: per adapter object
1811  * @index: msix index into vector table
1812  * @vector: irq vector
1813  *
1814  * Inserting respective reply_queue into the list.
1815  */
1816 static int
1817 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1818 {
1819         struct adapter_reply_queue *reply_q;
1820         int r;
1821
1822         reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1823         if (!reply_q) {
1824                 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1825                     ioc->name, (int)sizeof(struct adapter_reply_queue));
1826                 return -ENOMEM;
1827         }
1828         reply_q->ioc = ioc;
1829         reply_q->msix_index = index;
1830         reply_q->vector = vector;
1831
1832         if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1833                 return -ENOMEM;
1834         cpumask_clear(reply_q->affinity_hint);
1835
1836         atomic_set(&reply_q->busy, 0);
1837         if (ioc->msix_enable)
1838                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1839                     ioc->driver_name, ioc->id, index);
1840         else
1841                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1842                     ioc->driver_name, ioc->id);
1843         r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1844             reply_q);
1845         if (r) {
1846                 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1847                     reply_q->name, vector);
1848                 kfree(reply_q);
1849                 return -EBUSY;
1850         }
1851
1852         INIT_LIST_HEAD(&reply_q->list);
1853         list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1854         return 0;
1855 }
1856
1857 /**
1858  * _base_assign_reply_queues - assigning msix index for each cpu
1859  * @ioc: per adapter object
1860  *
1861  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1862  *
1863  * It would nice if we could call irq_set_affinity, however it is not
1864  * an exported symbol
1865  */
1866 static void
1867 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1868 {
1869         unsigned int cpu, nr_cpus, nr_msix, index = 0;
1870         struct adapter_reply_queue *reply_q;
1871
1872         if (!_base_is_controller_msix_enabled(ioc))
1873                 return;
1874
1875         memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1876
1877         nr_cpus = num_online_cpus();
1878         nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1879                                                ioc->facts.MaxMSIxVectors);
1880         if (!nr_msix)
1881                 return;
1882
1883         cpu = cpumask_first(cpu_online_mask);
1884
1885         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1886
1887                 unsigned int i, group = nr_cpus / nr_msix;
1888
1889                 if (cpu >= nr_cpus)
1890                         break;
1891
1892                 if (index < nr_cpus % nr_msix)
1893                         group++;
1894
1895                 for (i = 0 ; i < group ; i++) {
1896                         ioc->cpu_msix_table[cpu] = index;
1897                         cpumask_or(reply_q->affinity_hint,
1898                                    reply_q->affinity_hint, get_cpu_mask(cpu));
1899                         cpu = cpumask_next(cpu, cpu_online_mask);
1900                 }
1901
1902                 if (irq_set_affinity_hint(reply_q->vector,
1903                                            reply_q->affinity_hint))
1904                         dinitprintk(ioc, pr_info(MPT3SAS_FMT
1905                             "error setting affinity hint for irq vector %d\n",
1906                             ioc->name, reply_q->vector));
1907                 index++;
1908         }
1909 }
1910
1911 /**
1912  * _base_disable_msix - disables msix
1913  * @ioc: per adapter object
1914  *
1915  */
1916 static void
1917 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1918 {
1919         if (!ioc->msix_enable)
1920                 return;
1921         pci_disable_msix(ioc->pdev);
1922         ioc->msix_enable = 0;
1923 }
1924
1925 /**
1926  * _base_enable_msix - enables msix, failback to io_apic
1927  * @ioc: per adapter object
1928  *
1929  */
1930 static int
1931 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1932 {
1933         struct msix_entry *entries, *a;
1934         int r;
1935         int i;
1936         u8 try_msix = 0;
1937
1938         if (msix_disable == -1 || msix_disable == 0)
1939                 try_msix = 1;
1940
1941         if (!try_msix)
1942                 goto try_ioapic;
1943
1944         if (_base_check_enable_msix(ioc) != 0)
1945                 goto try_ioapic;
1946
1947         ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1948             ioc->msix_vector_count);
1949
1950         printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1951           ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1952           ioc->cpu_count, max_msix_vectors);
1953
1954         if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1955                 max_msix_vectors = 8;
1956
1957         if (max_msix_vectors > 0) {
1958                 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1959                         ioc->reply_queue_count);
1960                 ioc->msix_vector_count = ioc->reply_queue_count;
1961         } else if (max_msix_vectors == 0)
1962                 goto try_ioapic;
1963
1964         entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1965             GFP_KERNEL);
1966         if (!entries) {
1967                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1968                         "kcalloc failed @ at %s:%d/%s() !!!\n",
1969                         ioc->name, __FILE__, __LINE__, __func__));
1970                 goto try_ioapic;
1971         }
1972
1973         for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1974                 a->entry = i;
1975
1976         r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
1977         if (r) {
1978                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1979                         "pci_enable_msix_exact failed (r=%d) !!!\n",
1980                         ioc->name, r));
1981                 kfree(entries);
1982                 goto try_ioapic;
1983         }
1984
1985         ioc->msix_enable = 1;
1986         for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1987                 r = _base_request_irq(ioc, i, a->vector);
1988                 if (r) {
1989                         _base_free_irq(ioc);
1990                         _base_disable_msix(ioc);
1991                         kfree(entries);
1992                         goto try_ioapic;
1993                 }
1994         }
1995
1996         kfree(entries);
1997         return 0;
1998
1999 /* failback to io_apic interrupt routing */
2000  try_ioapic:
2001
2002         ioc->reply_queue_count = 1;
2003         r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2004
2005         return r;
2006 }
2007
2008 /**
2009  * mpt3sas_base_unmap_resources - free controller resources
2010  * @ioc: per adapter object
2011  */
2012 void
2013 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2014 {
2015         struct pci_dev *pdev = ioc->pdev;
2016
2017         dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2018                 ioc->name, __func__));
2019
2020         _base_free_irq(ioc);
2021         _base_disable_msix(ioc);
2022
2023         if (ioc->msix96_vector)
2024                 kfree(ioc->replyPostRegisterIndex);
2025
2026         if (ioc->chip_phys) {
2027                 iounmap(ioc->chip);
2028                 ioc->chip_phys = 0;
2029         }
2030
2031         if (pci_is_enabled(pdev)) {
2032                 pci_release_selected_regions(ioc->pdev, ioc->bars);
2033                 pci_disable_pcie_error_reporting(pdev);
2034                 pci_disable_device(pdev);
2035         }
2036 }
2037
2038 /**
2039  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2040  * @ioc: per adapter object
2041  *
2042  * Returns 0 for success, non-zero for failure.
2043  */
2044 int
2045 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2046 {
2047         struct pci_dev *pdev = ioc->pdev;
2048         u32 memap_sz;
2049         u32 pio_sz;
2050         int i, r = 0;
2051         u64 pio_chip = 0;
2052         u64 chip_phys = 0;
2053         struct adapter_reply_queue *reply_q;
2054
2055         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2056             ioc->name, __func__));
2057
2058         ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2059         if (pci_enable_device_mem(pdev)) {
2060                 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2061                         ioc->name);
2062                 ioc->bars = 0;
2063                 return -ENODEV;
2064         }
2065
2066
2067         if (pci_request_selected_regions(pdev, ioc->bars,
2068             ioc->driver_name)) {
2069                 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2070                         ioc->name);
2071                 ioc->bars = 0;
2072                 r = -ENODEV;
2073                 goto out_fail;
2074         }
2075
2076 /* AER (Advanced Error Reporting) hooks */
2077         pci_enable_pcie_error_reporting(pdev);
2078
2079         pci_set_master(pdev);
2080
2081
2082         if (_base_config_dma_addressing(ioc, pdev) != 0) {
2083                 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2084                     ioc->name, pci_name(pdev));
2085                 r = -ENODEV;
2086                 goto out_fail;
2087         }
2088
2089         for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2090              (!memap_sz || !pio_sz); i++) {
2091                 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2092                         if (pio_sz)
2093                                 continue;
2094                         pio_chip = (u64)pci_resource_start(pdev, i);
2095                         pio_sz = pci_resource_len(pdev, i);
2096                 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2097                         if (memap_sz)
2098                                 continue;
2099                         ioc->chip_phys = pci_resource_start(pdev, i);
2100                         chip_phys = (u64)ioc->chip_phys;
2101                         memap_sz = pci_resource_len(pdev, i);
2102                         ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2103                 }
2104         }
2105
2106         if (ioc->chip == NULL) {
2107                 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2108                         " or resource not found\n", ioc->name);
2109                 r = -EINVAL;
2110                 goto out_fail;
2111         }
2112
2113         _base_mask_interrupts(ioc);
2114
2115         r = _base_get_ioc_facts(ioc, CAN_SLEEP);
2116         if (r)
2117                 goto out_fail;
2118
2119         if (!ioc->rdpq_array_enable_assigned) {
2120                 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2121                 ioc->rdpq_array_enable_assigned = 1;
2122         }
2123
2124         r = _base_enable_msix(ioc);
2125         if (r)
2126                 goto out_fail;
2127
2128         /* Use the Combined reply queue feature only for SAS3 C0 & higher
2129          * revision HBAs and also only when reply queue count is greater than 8
2130          */
2131         if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2132                 /* Determine the Supplemental Reply Post Host Index Registers
2133                  * Addresse. Supplemental Reply Post Host Index Registers
2134                  * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2135                  * each register is at offset bytes of
2136                  * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2137                  */
2138                 ioc->replyPostRegisterIndex = kcalloc(
2139                      MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2140                      sizeof(resource_size_t *), GFP_KERNEL);
2141                 if (!ioc->replyPostRegisterIndex) {
2142                         dfailprintk(ioc, printk(MPT3SAS_FMT
2143                         "allocation for reply Post Register Index failed!!!\n",
2144                                                                    ioc->name));
2145                         r = -ENOMEM;
2146                         goto out_fail;
2147                 }
2148
2149                 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2150                         ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2151                              ((u8 *)&ioc->chip->Doorbell +
2152                              MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2153                              (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2154                 }
2155         } else
2156                 ioc->msix96_vector = 0;
2157
2158         if (ioc->is_warpdrive) {
2159                 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
2160                     &ioc->chip->ReplyPostHostIndex;
2161
2162                 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
2163                         ioc->reply_post_host_index[i] =
2164                         (resource_size_t __iomem *)
2165                         ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
2166                         * 4)));
2167         }
2168
2169         list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2170                 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2171                     reply_q->name,  ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2172                     "IO-APIC enabled"), reply_q->vector);
2173
2174         pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2175             ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2176         pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2177             ioc->name, (unsigned long long)pio_chip, pio_sz);
2178
2179         /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2180         pci_save_state(pdev);
2181         return 0;
2182
2183  out_fail:
2184         mpt3sas_base_unmap_resources(ioc);
2185         return r;
2186 }
2187
2188 /**
2189  * mpt3sas_base_get_msg_frame - obtain request mf pointer
2190  * @ioc: per adapter object
2191  * @smid: system request message index(smid zero is invalid)
2192  *
2193  * Returns virt pointer to message frame.
2194  */
2195 void *
2196 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2197 {
2198         return (void *)(ioc->request + (smid * ioc->request_sz));
2199 }
2200
2201 /**
2202  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2203  * @ioc: per adapter object
2204  * @smid: system request message index
2205  *
2206  * Returns virt pointer to sense buffer.
2207  */
2208 void *
2209 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2210 {
2211         return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2212 }
2213
2214 /**
2215  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2216  * @ioc: per adapter object
2217  * @smid: system request message index
2218  *
2219  * Returns phys pointer to the low 32bit address of the sense buffer.
2220  */
2221 __le32
2222 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2223 {
2224         return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2225             SCSI_SENSE_BUFFERSIZE));
2226 }
2227
2228 /**
2229  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2230  * @ioc: per adapter object
2231  * @phys_addr: lower 32 physical addr of the reply
2232  *
2233  * Converts 32bit lower physical addr into a virt address.
2234  */
2235 void *
2236 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2237 {
2238         if (!phys_addr)
2239                 return NULL;
2240         return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2241 }
2242
2243 /**
2244  * mpt3sas_base_get_smid - obtain a free smid from internal queue
2245  * @ioc: per adapter object
2246  * @cb_idx: callback index
2247  *
2248  * Returns smid (zero is invalid)
2249  */
2250 u16
2251 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2252 {
2253         unsigned long flags;
2254         struct request_tracker *request;
2255         u16 smid;
2256
2257         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2258         if (list_empty(&ioc->internal_free_list)) {
2259                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2260                 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2261                     ioc->name, __func__);
2262                 return 0;
2263         }
2264
2265         request = list_entry(ioc->internal_free_list.next,
2266             struct request_tracker, tracker_list);
2267         request->cb_idx = cb_idx;
2268         smid = request->smid;
2269         list_del(&request->tracker_list);
2270         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2271         return smid;
2272 }
2273
2274 /**
2275  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2276  * @ioc: per adapter object
2277  * @cb_idx: callback index
2278  * @scmd: pointer to scsi command object
2279  *
2280  * Returns smid (zero is invalid)
2281  */
2282 u16
2283 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2284         struct scsi_cmnd *scmd)
2285 {
2286         unsigned long flags;
2287         struct scsiio_tracker *request;
2288         u16 smid;
2289
2290         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2291         if (list_empty(&ioc->free_list)) {
2292                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2293                 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2294                     ioc->name, __func__);
2295                 return 0;
2296         }
2297
2298         request = list_entry(ioc->free_list.next,
2299             struct scsiio_tracker, tracker_list);
2300         request->scmd = scmd;
2301         request->cb_idx = cb_idx;
2302         smid = request->smid;
2303         list_del(&request->tracker_list);
2304         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2305         return smid;
2306 }
2307
2308 /**
2309  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2310  * @ioc: per adapter object
2311  * @cb_idx: callback index
2312  *
2313  * Returns smid (zero is invalid)
2314  */
2315 u16
2316 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2317 {
2318         unsigned long flags;
2319         struct request_tracker *request;
2320         u16 smid;
2321
2322         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2323         if (list_empty(&ioc->hpr_free_list)) {
2324                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2325                 return 0;
2326         }
2327
2328         request = list_entry(ioc->hpr_free_list.next,
2329             struct request_tracker, tracker_list);
2330         request->cb_idx = cb_idx;
2331         smid = request->smid;
2332         list_del(&request->tracker_list);
2333         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2334         return smid;
2335 }
2336
2337 /**
2338  * mpt3sas_base_free_smid - put smid back on free_list
2339  * @ioc: per adapter object
2340  * @smid: system request message index
2341  *
2342  * Return nothing.
2343  */
2344 void
2345 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2346 {
2347         unsigned long flags;
2348         int i;
2349         struct chain_tracker *chain_req, *next;
2350
2351         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2352         if (smid < ioc->hi_priority_smid) {
2353                 /* scsiio queue */
2354                 i = smid - 1;
2355                 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2356                         list_for_each_entry_safe(chain_req, next,
2357                             &ioc->scsi_lookup[i].chain_list, tracker_list) {
2358                                 list_del_init(&chain_req->tracker_list);
2359                                 list_add(&chain_req->tracker_list,
2360                                     &ioc->free_chain_list);
2361                         }
2362                 }
2363                 ioc->scsi_lookup[i].cb_idx = 0xFF;
2364                 ioc->scsi_lookup[i].scmd = NULL;
2365                 ioc->scsi_lookup[i].direct_io = 0;
2366                 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2367                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2368
2369                 /*
2370                  * See _wait_for_commands_to_complete() call with regards
2371                  * to this code.
2372                  */
2373                 if (ioc->shost_recovery && ioc->pending_io_count) {
2374                         if (ioc->pending_io_count == 1)
2375                                 wake_up(&ioc->reset_wq);
2376                         ioc->pending_io_count--;
2377                 }
2378                 return;
2379         } else if (smid < ioc->internal_smid) {
2380                 /* hi-priority */
2381                 i = smid - ioc->hi_priority_smid;
2382                 ioc->hpr_lookup[i].cb_idx = 0xFF;
2383                 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2384         } else if (smid <= ioc->hba_queue_depth) {
2385                 /* internal queue */
2386                 i = smid - ioc->internal_smid;
2387                 ioc->internal_lookup[i].cb_idx = 0xFF;
2388                 list_add(&ioc->internal_lookup[i].tracker_list,
2389                     &ioc->internal_free_list);
2390         }
2391         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2392 }
2393
2394 /**
2395  * _base_writeq - 64 bit write to MMIO
2396  * @ioc: per adapter object
2397  * @b: data payload
2398  * @addr: address in MMIO space
2399  * @writeq_lock: spin lock
2400  *
2401  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2402  * care of 32 bit environment where its not quarenteed to send the entire word
2403  * in one transfer.
2404  */
2405 #if defined(writeq) && defined(CONFIG_64BIT)
2406 static inline void
2407 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2408 {
2409         writeq(cpu_to_le64(b), addr);
2410 }
2411 #else
2412 static inline void
2413 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2414 {
2415         unsigned long flags;
2416         __u64 data_out = cpu_to_le64(b);
2417
2418         spin_lock_irqsave(writeq_lock, flags);
2419         writel((u32)(data_out), addr);
2420         writel((u32)(data_out >> 32), (addr + 4));
2421         spin_unlock_irqrestore(writeq_lock, flags);
2422 }
2423 #endif
2424
2425 static inline u8
2426 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2427 {
2428         return ioc->cpu_msix_table[raw_smp_processor_id()];
2429 }
2430
2431 /**
2432  * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2433  * @ioc: per adapter object
2434  * @smid: system request message index
2435  * @handle: device handle
2436  *
2437  * Return nothing.
2438  */
2439 void
2440 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2441 {
2442         Mpi2RequestDescriptorUnion_t descriptor;
2443         u64 *request = (u64 *)&descriptor;
2444
2445
2446         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2447         descriptor.SCSIIO.MSIxIndex =  _base_get_msix_index(ioc);
2448         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2449         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2450         descriptor.SCSIIO.LMID = 0;
2451         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2452             &ioc->scsi_lookup_lock);
2453 }
2454
2455 /**
2456  * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2457  * @ioc: per adapter object
2458  * @smid: system request message index
2459  * @handle: device handle
2460  *
2461  * Return nothing.
2462  */
2463 void
2464 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2465         u16 handle)
2466 {
2467         Mpi2RequestDescriptorUnion_t descriptor;
2468         u64 *request = (u64 *)&descriptor;
2469
2470         descriptor.SCSIIO.RequestFlags =
2471             MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2472         descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2473         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2474         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2475         descriptor.SCSIIO.LMID = 0;
2476         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2477             &ioc->scsi_lookup_lock);
2478 }
2479
2480 /**
2481  * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2482  * @ioc: per adapter object
2483  * @smid: system request message index
2484  *
2485  * Return nothing.
2486  */
2487 void
2488 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2489 {
2490         Mpi2RequestDescriptorUnion_t descriptor;
2491         u64 *request = (u64 *)&descriptor;
2492
2493         descriptor.HighPriority.RequestFlags =
2494             MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2495         descriptor.HighPriority.MSIxIndex =  0;
2496         descriptor.HighPriority.SMID = cpu_to_le16(smid);
2497         descriptor.HighPriority.LMID = 0;
2498         descriptor.HighPriority.Reserved1 = 0;
2499         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2500             &ioc->scsi_lookup_lock);
2501 }
2502
2503 /**
2504  * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2505  * @ioc: per adapter object
2506  * @smid: system request message index
2507  *
2508  * Return nothing.
2509  */
2510 void
2511 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2512 {
2513         Mpi2RequestDescriptorUnion_t descriptor;
2514         u64 *request = (u64 *)&descriptor;
2515
2516         descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2517         descriptor.Default.MSIxIndex =  _base_get_msix_index(ioc);
2518         descriptor.Default.SMID = cpu_to_le16(smid);
2519         descriptor.Default.LMID = 0;
2520         descriptor.Default.DescriptorTypeDependent = 0;
2521         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2522             &ioc->scsi_lookup_lock);
2523 }
2524
2525 /**
2526  * _base_display_OEMs_branding - Display branding string
2527  * @ioc: per adapter object
2528  *
2529  * Return nothing.
2530  */
2531 static void
2532 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
2533 {
2534         if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2535                 return;
2536
2537         switch (ioc->pdev->subsystem_vendor) {
2538         case PCI_VENDOR_ID_INTEL:
2539                 switch (ioc->pdev->device) {
2540                 case MPI2_MFGPAGE_DEVID_SAS2008:
2541                         switch (ioc->pdev->subsystem_device) {
2542                         case MPT2SAS_INTEL_RMS2LL080_SSDID:
2543                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2544                                     MPT2SAS_INTEL_RMS2LL080_BRANDING);
2545                                 break;
2546                         case MPT2SAS_INTEL_RMS2LL040_SSDID:
2547                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2548                                     MPT2SAS_INTEL_RMS2LL040_BRANDING);
2549                                 break;
2550                         case MPT2SAS_INTEL_SSD910_SSDID:
2551                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2552                                     MPT2SAS_INTEL_SSD910_BRANDING);
2553                                 break;
2554                         default:
2555                                 pr_info(MPT3SAS_FMT
2556                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2557                                  ioc->name, ioc->pdev->subsystem_device);
2558                                 break;
2559                         }
2560                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2561                         switch (ioc->pdev->subsystem_device) {
2562                         case MPT2SAS_INTEL_RS25GB008_SSDID:
2563                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2564                                     MPT2SAS_INTEL_RS25GB008_BRANDING);
2565                                 break;
2566                         case MPT2SAS_INTEL_RMS25JB080_SSDID:
2567                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2568                                     MPT2SAS_INTEL_RMS25JB080_BRANDING);
2569                                 break;
2570                         case MPT2SAS_INTEL_RMS25JB040_SSDID:
2571                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2572                                     MPT2SAS_INTEL_RMS25JB040_BRANDING);
2573                                 break;
2574                         case MPT2SAS_INTEL_RMS25KB080_SSDID:
2575                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2576                                     MPT2SAS_INTEL_RMS25KB080_BRANDING);
2577                                 break;
2578                         case MPT2SAS_INTEL_RMS25KB040_SSDID:
2579                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2580                                     MPT2SAS_INTEL_RMS25KB040_BRANDING);
2581                                 break;
2582                         case MPT2SAS_INTEL_RMS25LB040_SSDID:
2583                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2584                                     MPT2SAS_INTEL_RMS25LB040_BRANDING);
2585                                 break;
2586                         case MPT2SAS_INTEL_RMS25LB080_SSDID:
2587                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2588                                     MPT2SAS_INTEL_RMS25LB080_BRANDING);
2589                                 break;
2590                         default:
2591                                 pr_info(MPT3SAS_FMT
2592                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2593                                  ioc->name, ioc->pdev->subsystem_device);
2594                                 break;
2595                         }
2596                 case MPI25_MFGPAGE_DEVID_SAS3008:
2597                         switch (ioc->pdev->subsystem_device) {
2598                         case MPT3SAS_INTEL_RMS3JC080_SSDID:
2599                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2600                                         MPT3SAS_INTEL_RMS3JC080_BRANDING);
2601                                 break;
2602
2603                         case MPT3SAS_INTEL_RS3GC008_SSDID:
2604                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2605                                         MPT3SAS_INTEL_RS3GC008_BRANDING);
2606                                 break;
2607                         case MPT3SAS_INTEL_RS3FC044_SSDID:
2608                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2609                                         MPT3SAS_INTEL_RS3FC044_BRANDING);
2610                                 break;
2611                         case MPT3SAS_INTEL_RS3UC080_SSDID:
2612                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2613                                         MPT3SAS_INTEL_RS3UC080_BRANDING);
2614                                 break;
2615                         default:
2616                                 pr_info(MPT3SAS_FMT
2617                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2618                                  ioc->name, ioc->pdev->subsystem_device);
2619                                 break;
2620                         }
2621                         break;
2622                 default:
2623                         pr_info(MPT3SAS_FMT
2624                          "Intel(R) Controller: Subsystem ID: 0x%X\n",
2625                          ioc->name, ioc->pdev->subsystem_device);
2626                         break;
2627                 }
2628                 break;
2629         case PCI_VENDOR_ID_DELL:
2630                 switch (ioc->pdev->device) {
2631                 case MPI2_MFGPAGE_DEVID_SAS2008:
2632                         switch (ioc->pdev->subsystem_device) {
2633                         case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2634                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2635                                  MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2636                                 break;
2637                         case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2638                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2639                                  MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2640                                 break;
2641                         case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2642                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2643                                  MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2644                                 break;
2645                         case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2646                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2647                                  MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2648                                 break;
2649                         case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2650                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2651                                  MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2652                                 break;
2653                         case MPT2SAS_DELL_PERC_H200_SSDID:
2654                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2655                                  MPT2SAS_DELL_PERC_H200_BRANDING);
2656                                 break;
2657                         case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2658                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2659                                  MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2660                                 break;
2661                         default:
2662                                 pr_info(MPT3SAS_FMT
2663                                    "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2664                                    ioc->name, ioc->pdev->subsystem_device);
2665                                 break;
2666                         }
2667                         break;
2668                 case MPI25_MFGPAGE_DEVID_SAS3008:
2669                         switch (ioc->pdev->subsystem_device) {
2670                         case MPT3SAS_DELL_12G_HBA_SSDID:
2671                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2672                                         MPT3SAS_DELL_12G_HBA_BRANDING);
2673                                 break;
2674                         default:
2675                                 pr_info(MPT3SAS_FMT
2676                                    "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2677                                    ioc->name, ioc->pdev->subsystem_device);
2678                                 break;
2679                         }
2680                         break;
2681                 default:
2682                         pr_info(MPT3SAS_FMT
2683                            "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
2684                            ioc->pdev->subsystem_device);
2685                         break;
2686                 }
2687                 break;
2688         case PCI_VENDOR_ID_CISCO:
2689                 switch (ioc->pdev->device) {
2690                 case MPI25_MFGPAGE_DEVID_SAS3008:
2691                         switch (ioc->pdev->subsystem_device) {
2692                         case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2693                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2694                                         MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2695                                 break;
2696                         case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2697                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2698                                         MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2699                                 break;
2700                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2701                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2702                                         MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2703                                 break;
2704                         default:
2705                                 pr_info(MPT3SAS_FMT
2706                                   "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2707                                   ioc->name, ioc->pdev->subsystem_device);
2708                                 break;
2709                         }
2710                         break;
2711                 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2712                         switch (ioc->pdev->subsystem_device) {
2713                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2714                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2715                                 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2716                                 break;
2717                         case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2718                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2719                                 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2720                                 );
2721                                 break;
2722                         default:
2723                                 pr_info(MPT3SAS_FMT
2724                                  "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2725                                  ioc->name, ioc->pdev->subsystem_device);
2726                                 break;
2727                         }
2728                         break;
2729                 default:
2730                         pr_info(MPT3SAS_FMT
2731                            "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2732                            ioc->name, ioc->pdev->subsystem_device);
2733                         break;
2734                 }
2735                 break;
2736         case MPT2SAS_HP_3PAR_SSVID:
2737                 switch (ioc->pdev->device) {
2738                 case MPI2_MFGPAGE_DEVID_SAS2004:
2739                         switch (ioc->pdev->subsystem_device) {
2740                         case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2741                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2742                                     MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2743                                 break;
2744                         default:
2745                                 pr_info(MPT3SAS_FMT
2746                                    "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2747                                    ioc->name, ioc->pdev->subsystem_device);
2748                                 break;
2749                         }
2750                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2751                         switch (ioc->pdev->subsystem_device) {
2752                         case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2753                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2754                                     MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2755                                 break;
2756                         case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2757                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2758                                     MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2759                                 break;
2760                         case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2761                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2762                                  MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2763                                 break;
2764                         case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2765                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2766                                     MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2767                                 break;
2768                         default:
2769                                 pr_info(MPT3SAS_FMT
2770                                    "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2771                                    ioc->name, ioc->pdev->subsystem_device);
2772                                 break;
2773                         }
2774                 default:
2775                         pr_info(MPT3SAS_FMT
2776                            "HP SAS HBA: Subsystem ID: 0x%X\n",
2777                            ioc->name, ioc->pdev->subsystem_device);
2778                         break;
2779                 }
2780         default:
2781                 break;
2782         }
2783 }
2784
2785 /**
2786  * _base_display_ioc_capabilities - Disply IOC's capabilities.
2787  * @ioc: per adapter object
2788  *
2789  * Return nothing.
2790  */
2791 static void
2792 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2793 {
2794         int i = 0;
2795         char desc[16];
2796         u32 iounit_pg1_flags;
2797         u32 bios_version;
2798
2799         bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2800         strncpy(desc, ioc->manu_pg0.ChipName, 16);
2801         pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2802            "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2803             ioc->name, desc,
2804            (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2805            (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2806            (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2807            ioc->facts.FWVersion.Word & 0x000000FF,
2808            ioc->pdev->revision,
2809            (bios_version & 0xFF000000) >> 24,
2810            (bios_version & 0x00FF0000) >> 16,
2811            (bios_version & 0x0000FF00) >> 8,
2812             bios_version & 0x000000FF);
2813
2814         _base_display_OEMs_branding(ioc);
2815
2816         pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2817
2818         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2819                 pr_info("Initiator");
2820                 i++;
2821         }
2822
2823         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2824                 pr_info("%sTarget", i ? "," : "");
2825                 i++;
2826         }
2827
2828         i = 0;
2829         pr_info("), ");
2830         pr_info("Capabilities=(");
2831
2832         if (!ioc->hide_ir_msg) {
2833                 if (ioc->facts.IOCCapabilities &
2834                     MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2835                         pr_info("Raid");
2836                         i++;
2837                 }
2838         }
2839
2840         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2841                 pr_info("%sTLR", i ? "," : "");
2842                 i++;
2843         }
2844
2845         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2846                 pr_info("%sMulticast", i ? "," : "");
2847                 i++;
2848         }
2849
2850         if (ioc->facts.IOCCapabilities &
2851             MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2852                 pr_info("%sBIDI Target", i ? "," : "");
2853                 i++;
2854         }
2855
2856         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2857                 pr_info("%sEEDP", i ? "," : "");
2858                 i++;
2859         }
2860
2861         if (ioc->facts.IOCCapabilities &
2862             MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2863                 pr_info("%sSnapshot Buffer", i ? "," : "");
2864                 i++;
2865         }
2866
2867         if (ioc->facts.IOCCapabilities &
2868             MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2869                 pr_info("%sDiag Trace Buffer", i ? "," : "");
2870                 i++;
2871         }
2872
2873         if (ioc->facts.IOCCapabilities &
2874             MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2875                 pr_info("%sDiag Extended Buffer", i ? "," : "");
2876                 i++;
2877         }
2878
2879         if (ioc->facts.IOCCapabilities &
2880             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2881                 pr_info("%sTask Set Full", i ? "," : "");
2882                 i++;
2883         }
2884
2885         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2886         if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2887                 pr_info("%sNCQ", i ? "," : "");
2888                 i++;
2889         }
2890
2891         pr_info(")\n");
2892 }
2893
2894 /**
2895  * mpt3sas_base_update_missing_delay - change the missing delay timers
2896  * @ioc: per adapter object
2897  * @device_missing_delay: amount of time till device is reported missing
2898  * @io_missing_delay: interval IO is returned when there is a missing device
2899  *
2900  * Return nothing.
2901  *
2902  * Passed on the command line, this function will modify the device missing
2903  * delay, as well as the io missing delay. This should be called at driver
2904  * load time.
2905  */
2906 void
2907 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2908         u16 device_missing_delay, u8 io_missing_delay)
2909 {
2910         u16 dmd, dmd_new, dmd_orignal;
2911         u8 io_missing_delay_original;
2912         u16 sz;
2913         Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2914         Mpi2ConfigReply_t mpi_reply;
2915         u8 num_phys = 0;
2916         u16 ioc_status;
2917
2918         mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2919         if (!num_phys)
2920                 return;
2921
2922         sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2923             sizeof(Mpi2SasIOUnit1PhyData_t));
2924         sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2925         if (!sas_iounit_pg1) {
2926                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2927                     ioc->name, __FILE__, __LINE__, __func__);
2928                 goto out;
2929         }
2930         if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2931             sas_iounit_pg1, sz))) {
2932                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2933                     ioc->name, __FILE__, __LINE__, __func__);
2934                 goto out;
2935         }
2936         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2937             MPI2_IOCSTATUS_MASK;
2938         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2939                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2940                     ioc->name, __FILE__, __LINE__, __func__);
2941                 goto out;
2942         }
2943
2944         /* device missing delay */
2945         dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2946         if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2947                 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2948         else
2949                 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2950         dmd_orignal = dmd;
2951         if (device_missing_delay > 0x7F) {
2952                 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2953                     device_missing_delay;
2954                 dmd = dmd / 16;
2955                 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2956         } else
2957                 dmd = device_missing_delay;
2958         sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2959
2960         /* io missing delay */
2961         io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2962         sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2963
2964         if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2965             sz)) {
2966                 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2967                         dmd_new = (dmd &
2968                             MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2969                 else
2970                         dmd_new =
2971                     dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2972                 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2973                         ioc->name, dmd_orignal, dmd_new);
2974                 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2975                         ioc->name, io_missing_delay_original,
2976                     io_missing_delay);
2977                 ioc->device_missing_delay = dmd_new;
2978                 ioc->io_missing_delay = io_missing_delay;
2979         }
2980
2981 out:
2982         kfree(sas_iounit_pg1);
2983 }
2984 /**
2985  * _base_static_config_pages - static start of day config pages
2986  * @ioc: per adapter object
2987  *
2988  * Return nothing.
2989  */
2990 static void
2991 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2992 {
2993         Mpi2ConfigReply_t mpi_reply;
2994         u32 iounit_pg1_flags;
2995
2996         mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2997         if (ioc->ir_firmware)
2998                 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2999                     &ioc->manu_pg10);
3000
3001         /*
3002          * Ensure correct T10 PI operation if vendor left EEDPTagMode
3003          * flag unset in NVDATA.
3004          */
3005         mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3006         if (ioc->manu_pg11.EEDPTagMode == 0) {
3007                 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3008                     ioc->name);
3009                 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3010                 ioc->manu_pg11.EEDPTagMode |= 0x1;
3011                 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3012                     &ioc->manu_pg11);
3013         }
3014
3015         mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3016         mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3017         mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3018         mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3019         mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3020         mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
3021         _base_display_ioc_capabilities(ioc);
3022
3023         /*
3024          * Enable task_set_full handling in iounit_pg1 when the
3025          * facts capabilities indicate that its supported.
3026          */
3027         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3028         if ((ioc->facts.IOCCapabilities &
3029             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3030                 iounit_pg1_flags &=
3031                     ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3032         else
3033                 iounit_pg1_flags |=
3034                     MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3035         ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3036         mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3037
3038         if (ioc->iounit_pg8.NumSensors)
3039                 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
3040 }
3041
3042 /**
3043  * _base_release_memory_pools - release memory
3044  * @ioc: per adapter object
3045  *
3046  * Free memory allocated from _base_allocate_memory_pools.
3047  *
3048  * Return nothing.
3049  */
3050 static void
3051 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3052 {
3053         int i = 0;
3054         struct reply_post_struct *rps;
3055
3056         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3057             __func__));
3058
3059         if (ioc->request) {
3060                 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3061                     ioc->request,  ioc->request_dma);
3062                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3063                         "request_pool(0x%p): free\n",
3064                         ioc->name, ioc->request));
3065                 ioc->request = NULL;
3066         }
3067
3068         if (ioc->sense) {
3069                 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3070                 if (ioc->sense_dma_pool)
3071                         pci_pool_destroy(ioc->sense_dma_pool);
3072                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3073                         "sense_pool(0x%p): free\n",
3074                         ioc->name, ioc->sense));
3075                 ioc->sense = NULL;
3076         }
3077
3078         if (ioc->reply) {
3079                 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3080                 if (ioc->reply_dma_pool)
3081                         pci_pool_destroy(ioc->reply_dma_pool);
3082                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3083                         "reply_pool(0x%p): free\n",
3084                         ioc->name, ioc->reply));
3085                 ioc->reply = NULL;
3086         }
3087
3088         if (ioc->reply_free) {
3089                 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3090                     ioc->reply_free_dma);
3091                 if (ioc->reply_free_dma_pool)
3092                         pci_pool_destroy(ioc->reply_free_dma_pool);
3093                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3094                         "reply_free_pool(0x%p): free\n",
3095                         ioc->name, ioc->reply_free));
3096                 ioc->reply_free = NULL;
3097         }
3098
3099         if (ioc->reply_post) {
3100                 do {
3101                         rps = &ioc->reply_post[i];
3102                         if (rps->reply_post_free) {
3103                                 pci_pool_free(
3104                                     ioc->reply_post_free_dma_pool,
3105                                     rps->reply_post_free,
3106                                     rps->reply_post_free_dma);
3107                                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3108                                     "reply_post_free_pool(0x%p): free\n",
3109                                     ioc->name, rps->reply_post_free));
3110                                 rps->reply_post_free = NULL;
3111                         }
3112                 } while (ioc->rdpq_array_enable &&
3113                            (++i < ioc->reply_queue_count));
3114
3115                 if (ioc->reply_post_free_dma_pool)
3116                         pci_pool_destroy(ioc->reply_post_free_dma_pool);
3117                 kfree(ioc->reply_post);
3118         }
3119
3120         if (ioc->config_page) {
3121                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3122                     "config_page(0x%p): free\n", ioc->name,
3123                     ioc->config_page));
3124                 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3125                     ioc->config_page, ioc->config_page_dma);
3126         }
3127
3128         if (ioc->scsi_lookup) {
3129                 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3130                 ioc->scsi_lookup = NULL;
3131         }
3132         kfree(ioc->hpr_lookup);
3133         kfree(ioc->internal_lookup);
3134         if (ioc->chain_lookup) {
3135                 for (i = 0; i < ioc->chain_depth; i++) {
3136                         if (ioc->chain_lookup[i].chain_buffer)
3137                                 pci_pool_free(ioc->chain_dma_pool,
3138                                     ioc->chain_lookup[i].chain_buffer,
3139                                     ioc->chain_lookup[i].chain_buffer_dma);
3140                 }
3141                 if (ioc->chain_dma_pool)
3142                         pci_pool_destroy(ioc->chain_dma_pool);
3143                 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3144                 ioc->chain_lookup = NULL;
3145         }
3146 }
3147
3148 /**
3149  * _base_allocate_memory_pools - allocate start of day memory pools
3150  * @ioc: per adapter object
3151  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3152  *
3153  * Returns 0 success, anything else error
3154  */
3155 static int
3156 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc,  int sleep_flag)
3157 {
3158         struct mpt3sas_facts *facts;
3159         u16 max_sge_elements;
3160         u16 chains_needed_per_io;
3161         u32 sz, total_sz, reply_post_free_sz;
3162         u32 retry_sz;
3163         u16 max_request_credit;
3164         unsigned short sg_tablesize;
3165         u16 sge_size;
3166         int i;
3167
3168         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3169             __func__));
3170
3171
3172         retry_sz = 0;
3173         facts = &ioc->facts;
3174
3175         /* command line tunables for max sgl entries */
3176         if (max_sgl_entries != -1)
3177                 sg_tablesize = max_sgl_entries;
3178         else {
3179                 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3180                         sg_tablesize = MPT2SAS_SG_DEPTH;
3181                 else
3182                         sg_tablesize = MPT3SAS_SG_DEPTH;
3183         }
3184
3185         if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3186                 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3187         else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
3188                 sg_tablesize = min_t(unsigned short, sg_tablesize,
3189                                       SCSI_MAX_SG_CHAIN_SEGMENTS);
3190                 pr_warn(MPT3SAS_FMT
3191                  "sg_tablesize(%u) is bigger than kernel"
3192                  " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
3193                  sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
3194         }
3195         ioc->shost->sg_tablesize = sg_tablesize;
3196
3197         ioc->hi_priority_depth = facts->HighPriorityCredit;
3198         ioc->internal_depth = ioc->hi_priority_depth + (5);
3199         /* command line tunables  for max controller queue depth */
3200         if (max_queue_depth != -1 && max_queue_depth != 0) {
3201                 max_request_credit = min_t(u16, max_queue_depth +
3202                     ioc->hi_priority_depth + ioc->internal_depth,
3203                     facts->RequestCredit);
3204                 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3205                         max_request_credit =  MAX_HBA_QUEUE_DEPTH;
3206         } else
3207                 max_request_credit = min_t(u16, facts->RequestCredit,
3208                     MAX_HBA_QUEUE_DEPTH);
3209
3210         ioc->hba_queue_depth = max_request_credit;
3211
3212         /* request frame size */
3213         ioc->request_sz = facts->IOCRequestFrameSize * 4;
3214
3215         /* reply frame size */
3216         ioc->reply_sz = facts->ReplyFrameSize * 4;
3217
3218         /* calculate the max scatter element size */
3219         sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3220
3221  retry_allocation:
3222         total_sz = 0;
3223         /* calculate number of sg elements left over in the 1st frame */
3224         max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3225             sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3226         ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3227
3228         /* now do the same for a chain buffer */
3229         max_sge_elements = ioc->request_sz - sge_size;
3230         ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3231
3232         /*
3233          *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3234          */
3235         chains_needed_per_io = ((ioc->shost->sg_tablesize -
3236            ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3237             + 1;
3238         if (chains_needed_per_io > facts->MaxChainDepth) {
3239                 chains_needed_per_io = facts->MaxChainDepth;
3240                 ioc->shost->sg_tablesize = min_t(u16,
3241                 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3242                 * chains_needed_per_io), ioc->shost->sg_tablesize);
3243         }
3244         ioc->chains_needed_per_io = chains_needed_per_io;
3245
3246         /* reply free queue sizing - taking into account for 64 FW events */
3247         ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3248
3249         /* calculate reply descriptor post queue depth */
3250         ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3251                                 ioc->reply_free_queue_depth +  1 ;
3252         /* align the reply post queue on the next 16 count boundary */
3253         if (ioc->reply_post_queue_depth % 16)
3254                 ioc->reply_post_queue_depth += 16 -
3255                 (ioc->reply_post_queue_depth % 16);
3256
3257
3258         if (ioc->reply_post_queue_depth >
3259             facts->MaxReplyDescriptorPostQueueDepth) {
3260                 ioc->reply_post_queue_depth =
3261                                 facts->MaxReplyDescriptorPostQueueDepth -
3262                     (facts->MaxReplyDescriptorPostQueueDepth % 16);
3263                 ioc->hba_queue_depth =
3264                                 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3265                 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3266         }
3267
3268         dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3269             "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3270             "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3271             ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3272             ioc->chains_needed_per_io));
3273
3274         /* reply post queue, 16 byte align */
3275         reply_post_free_sz = ioc->reply_post_queue_depth *
3276             sizeof(Mpi2DefaultReplyDescriptor_t);
3277
3278         sz = reply_post_free_sz;
3279         if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3280                 sz *= ioc->reply_queue_count;
3281
3282         ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3283             (ioc->reply_queue_count):1,
3284             sizeof(struct reply_post_struct), GFP_KERNEL);
3285
3286         if (!ioc->reply_post) {
3287                 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3288                         ioc->name);
3289                 goto out;
3290         }
3291         ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3292             ioc->pdev, sz, 16, 0);
3293         if (!ioc->reply_post_free_dma_pool) {
3294                 pr_err(MPT3SAS_FMT
3295                  "reply_post_free pool: pci_pool_create failed\n",
3296                  ioc->name);
3297                 goto out;
3298         }
3299         i = 0;
3300         do {
3301                 ioc->reply_post[i].reply_post_free =
3302                     pci_pool_alloc(ioc->reply_post_free_dma_pool,
3303                     GFP_KERNEL,
3304                     &ioc->reply_post[i].reply_post_free_dma);
3305                 if (!ioc->reply_post[i].reply_post_free) {
3306                         pr_err(MPT3SAS_FMT
3307                         "reply_post_free pool: pci_pool_alloc failed\n",
3308                         ioc->name);
3309                         goto out;
3310                 }
3311                 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3312                 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3313                     "reply post free pool (0x%p): depth(%d),"
3314                     "element_size(%d), pool_size(%d kB)\n", ioc->name,
3315                     ioc->reply_post[i].reply_post_free,
3316                     ioc->reply_post_queue_depth, 8, sz/1024));
3317                 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3318                     "reply_post_free_dma = (0x%llx)\n", ioc->name,
3319                     (unsigned long long)
3320                     ioc->reply_post[i].reply_post_free_dma));
3321                 total_sz += sz;
3322         } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3323
3324         if (ioc->dma_mask == 64) {
3325                 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3326                         pr_warn(MPT3SAS_FMT
3327                             "no suitable consistent DMA mask for %s\n",
3328                             ioc->name, pci_name(ioc->pdev));
3329                         goto out;
3330                 }
3331         }
3332
3333         ioc->scsiio_depth = ioc->hba_queue_depth -
3334             ioc->hi_priority_depth - ioc->internal_depth;
3335
3336         /* set the scsi host can_queue depth
3337          * with some internal commands that could be outstanding
3338          */
3339         ioc->shost->can_queue = ioc->scsiio_depth;
3340         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3341                 "scsi host: can_queue depth (%d)\n",
3342                 ioc->name, ioc->shost->can_queue));
3343
3344
3345         /* contiguous pool for request and chains, 16 byte align, one extra "
3346          * "frame for smid=0
3347          */
3348         ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3349         sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3350
3351         /* hi-priority queue */
3352         sz += (ioc->hi_priority_depth * ioc->request_sz);
3353
3354         /* internal queue */
3355         sz += (ioc->internal_depth * ioc->request_sz);
3356
3357         ioc->request_dma_sz = sz;
3358         ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3359         if (!ioc->request) {
3360                 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3361                     "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3362                     "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3363                     ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3364                 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3365                         goto out;
3366                 retry_sz += 64;
3367                 ioc->hba_queue_depth = max_request_credit - retry_sz;
3368                 goto retry_allocation;
3369         }
3370
3371         if (retry_sz)
3372                 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3373                     "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3374                     "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3375                     ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3376
3377         /* hi-priority queue */
3378         ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3379             ioc->request_sz);
3380         ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3381             ioc->request_sz);
3382
3383         /* internal queue */
3384         ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3385             ioc->request_sz);
3386         ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3387             ioc->request_sz);
3388
3389         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3390                 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3391                 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3392             (ioc->hba_queue_depth * ioc->request_sz)/1024));
3393
3394         dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3395             ioc->name, (unsigned long long) ioc->request_dma));
3396         total_sz += sz;
3397
3398         sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3399         ioc->scsi_lookup_pages = get_order(sz);
3400         ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3401             GFP_KERNEL, ioc->scsi_lookup_pages);
3402         if (!ioc->scsi_lookup) {
3403                 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3404                         ioc->name, (int)sz);
3405                 goto out;
3406         }
3407
3408         dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3409                 ioc->name, ioc->request, ioc->scsiio_depth));
3410
3411         ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3412         sz = ioc->chain_depth * sizeof(struct chain_tracker);
3413         ioc->chain_pages = get_order(sz);
3414         ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3415             GFP_KERNEL, ioc->chain_pages);
3416         if (!ioc->chain_lookup) {
3417                 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3418                         ioc->name);
3419                 goto out;
3420         }
3421         ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3422             ioc->request_sz, 16, 0);
3423         if (!ioc->chain_dma_pool) {
3424                 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3425                         ioc->name);
3426                 goto out;
3427         }
3428         for (i = 0; i < ioc->chain_depth; i++) {
3429                 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3430                     ioc->chain_dma_pool , GFP_KERNEL,
3431                     &ioc->chain_lookup[i].chain_buffer_dma);
3432                 if (!ioc->chain_lookup[i].chain_buffer) {
3433                         ioc->chain_depth = i;
3434                         goto chain_done;
3435                 }
3436                 total_sz += ioc->request_sz;
3437         }
3438  chain_done:
3439         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3440                 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3441                 ioc->name, ioc->chain_depth, ioc->request_sz,
3442                 ((ioc->chain_depth *  ioc->request_sz))/1024));
3443
3444         /* initialize hi-priority queue smid's */
3445         ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3446             sizeof(struct request_tracker), GFP_KERNEL);
3447         if (!ioc->hpr_lookup) {
3448                 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3449                     ioc->name);
3450                 goto out;
3451         }
3452         ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3453         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3454                 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3455                 ioc->name, ioc->hi_priority,
3456             ioc->hi_priority_depth, ioc->hi_priority_smid));
3457
3458         /* initialize internal queue smid's */
3459         ioc->internal_lookup = kcalloc(ioc->internal_depth,
3460             sizeof(struct request_tracker), GFP_KERNEL);
3461         if (!ioc->internal_lookup) {
3462                 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3463                     ioc->name);
3464                 goto out;
3465         }
3466         ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3467         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3468                 "internal(0x%p): depth(%d), start smid(%d)\n",
3469                 ioc->name, ioc->internal,
3470             ioc->internal_depth, ioc->internal_smid));
3471
3472         /* sense buffers, 4 byte align */
3473         sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3474         ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3475             0);
3476         if (!ioc->sense_dma_pool) {
3477                 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3478                     ioc->name);
3479                 goto out;
3480         }
3481         ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3482             &ioc->sense_dma);
3483         if (!ioc->sense) {
3484                 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3485                     ioc->name);
3486                 goto out;
3487         }
3488         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3489             "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3490             "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3491             SCSI_SENSE_BUFFERSIZE, sz/1024));
3492         dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3493             ioc->name, (unsigned long long)ioc->sense_dma));
3494         total_sz += sz;
3495
3496         /* reply pool, 4 byte align */
3497         sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3498         ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3499             0);
3500         if (!ioc->reply_dma_pool) {
3501                 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3502                     ioc->name);
3503                 goto out;
3504         }
3505         ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3506             &ioc->reply_dma);
3507         if (!ioc->reply) {
3508                 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3509                     ioc->name);
3510                 goto out;
3511         }
3512         ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3513         ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3514         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3515                 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3516                 ioc->name, ioc->reply,
3517             ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3518         dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3519             ioc->name, (unsigned long long)ioc->reply_dma));
3520         total_sz += sz;
3521
3522         /* reply free queue, 16 byte align */
3523         sz = ioc->reply_free_queue_depth * 4;
3524         ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3525             ioc->pdev, sz, 16, 0);
3526         if (!ioc->reply_free_dma_pool) {
3527                 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3528                         ioc->name);
3529                 goto out;
3530         }
3531         ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3532             &ioc->reply_free_dma);
3533         if (!ioc->reply_free) {
3534                 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3535                         ioc->name);
3536                 goto out;
3537         }
3538         memset(ioc->reply_free, 0, sz);
3539         dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3540             "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3541             ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3542         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3543                 "reply_free_dma (0x%llx)\n",
3544                 ioc->name, (unsigned long long)ioc->reply_free_dma));
3545         total_sz += sz;
3546
3547         ioc->config_page_sz = 512;
3548         ioc->config_page = pci_alloc_consistent(ioc->pdev,
3549             ioc->config_page_sz, &ioc->config_page_dma);
3550         if (!ioc->config_page) {
3551                 pr_err(MPT3SAS_FMT
3552                         "config page: pci_pool_alloc failed\n",
3553                         ioc->name);
3554                 goto out;
3555         }
3556         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3557                 "config page(0x%p): size(%d)\n",
3558                 ioc->name, ioc->config_page, ioc->config_page_sz));
3559         dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3560                 ioc->name, (unsigned long long)ioc->config_page_dma));
3561         total_sz += ioc->config_page_sz;
3562
3563         pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3564             ioc->name, total_sz/1024);
3565         pr_info(MPT3SAS_FMT
3566                 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3567             ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3568         pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3569             ioc->name, ioc->shost->sg_tablesize);
3570         return 0;
3571
3572  out:
3573         return -ENOMEM;
3574 }
3575
3576 /**
3577  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3578  * @ioc: Pointer to MPT_ADAPTER structure
3579  * @cooked: Request raw or cooked IOC state
3580  *
3581  * Returns all IOC Doorbell register bits if cooked==0, else just the
3582  * Doorbell bits in MPI_IOC_STATE_MASK.
3583  */
3584 u32
3585 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3586 {
3587         u32 s, sc;
3588
3589         s = readl(&ioc->chip->Doorbell);
3590         sc = s & MPI2_IOC_STATE_MASK;
3591         return cooked ? sc : s;
3592 }
3593
3594 /**
3595  * _base_wait_on_iocstate - waiting on a particular ioc state
3596  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3597  * @timeout: timeout in second
3598  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3599  *
3600  * Returns 0 for success, non-zero for failure.
3601  */
3602 static int
3603 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3604         int sleep_flag)
3605 {
3606         u32 count, cntdn;
3607         u32 current_state;
3608
3609         count = 0;
3610         cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3611         do {
3612                 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3613                 if (current_state == ioc_state)
3614                         return 0;
3615                 if (count && current_state == MPI2_IOC_STATE_FAULT)
3616                         break;
3617                 if (sleep_flag == CAN_SLEEP)
3618                         usleep_range(1000, 1500);
3619                 else
3620                         udelay(500);
3621                 count++;
3622         } while (--cntdn);
3623
3624         return current_state;
3625 }
3626
3627 /**
3628  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3629  * a write to the doorbell)
3630  * @ioc: per adapter object
3631  * @timeout: timeout in second
3632  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3633  *
3634  * Returns 0 for success, non-zero for failure.
3635  *
3636  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3637  */
3638 static int
3639 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3640
3641 static int
3642 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3643         int sleep_flag)
3644 {
3645         u32 cntdn, count;
3646         u32 int_status;
3647
3648         count = 0;
3649         cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3650         do {
3651                 int_status = readl(&ioc->chip->HostInterruptStatus);
3652                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3653                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3654                                 "%s: successful count(%d), timeout(%d)\n",
3655                                 ioc->name, __func__, count, timeout));
3656                         return 0;
3657                 }
3658                 if (sleep_flag == CAN_SLEEP)
3659                         usleep_range(1000, 1500);
3660                 else
3661                         udelay(500);
3662                 count++;
3663         } while (--cntdn);
3664
3665         pr_err(MPT3SAS_FMT
3666                 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3667                 ioc->name, __func__, count, int_status);
3668         return -EFAULT;
3669 }
3670
3671 /**
3672  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3673  * @ioc: per adapter object
3674  * @timeout: timeout in second
3675  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3676  *
3677  * Returns 0 for success, non-zero for failure.
3678  *
3679  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3680  * doorbell.
3681  */
3682 static int
3683 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3684         int sleep_flag)
3685 {
3686         u32 cntdn, count;
3687         u32 int_status;
3688         u32 doorbell;
3689
3690         count = 0;
3691         cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3692         do {
3693                 int_status = readl(&ioc->chip->HostInterruptStatus);
3694                 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3695                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3696                                 "%s: successful count(%d), timeout(%d)\n",
3697                                 ioc->name, __func__, count, timeout));
3698                         return 0;
3699                 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3700                         doorbell = readl(&ioc->chip->Doorbell);
3701                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
3702                             MPI2_IOC_STATE_FAULT) {
3703                                 mpt3sas_base_fault_info(ioc , doorbell);
3704                                 return -EFAULT;
3705                         }
3706                 } else if (int_status == 0xFFFFFFFF)
3707                         goto out;
3708
3709                 if (sleep_flag == CAN_SLEEP)
3710                         usleep_range(1000, 1500);
3711                 else
3712                         udelay(500);
3713                 count++;
3714         } while (--cntdn);
3715
3716  out:
3717         pr_err(MPT3SAS_FMT
3718          "%s: failed due to timeout count(%d), int_status(%x)!\n",
3719          ioc->name, __func__, count, int_status);
3720         return -EFAULT;
3721 }
3722
3723 /**
3724  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3725  * @ioc: per adapter object
3726  * @timeout: timeout in second
3727  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3728  *
3729  * Returns 0 for success, non-zero for failure.
3730  *
3731  */
3732 static int
3733 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3734         int sleep_flag)
3735 {
3736         u32 cntdn, count;
3737         u32 doorbell_reg;
3738
3739         count = 0;
3740         cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3741         do {
3742                 doorbell_reg = readl(&ioc->chip->Doorbell);
3743                 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3744                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3745                                 "%s: successful count(%d), timeout(%d)\n",
3746                                 ioc->name, __func__, count, timeout));
3747                         return 0;
3748                 }
3749                 if (sleep_flag == CAN_SLEEP)
3750                         usleep_range(1000, 1500);
3751                 else
3752                         udelay(500);
3753                 count++;
3754         } while (--cntdn);
3755
3756         pr_err(MPT3SAS_FMT
3757                 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3758                 ioc->name, __func__, count, doorbell_reg);
3759         return -EFAULT;
3760 }
3761
3762 /**
3763  * _base_send_ioc_reset - send doorbell reset
3764  * @ioc: per adapter object
3765  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3766  * @timeout: timeout in second
3767  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3768  *
3769  * Returns 0 for success, non-zero for failure.
3770  */
3771 static int
3772 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3773         int sleep_flag)
3774 {
3775         u32 ioc_state;
3776         int r = 0;
3777
3778         if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3779                 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3780                     ioc->name, __func__);
3781                 return -EFAULT;
3782         }
3783
3784         if (!(ioc->facts.IOCCapabilities &
3785            MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3786                 return -EFAULT;
3787
3788         pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3789
3790         writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3791             &ioc->chip->Doorbell);
3792         if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3793                 r = -EFAULT;
3794                 goto out;
3795         }
3796         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3797             timeout, sleep_flag);
3798         if (ioc_state) {
3799                 pr_err(MPT3SAS_FMT
3800                         "%s: failed going to ready state (ioc_state=0x%x)\n",
3801                         ioc->name, __func__, ioc_state);
3802                 r = -EFAULT;
3803                 goto out;
3804         }
3805  out:
3806         pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3807             ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3808         return r;
3809 }
3810
3811 /**
3812  * _base_handshake_req_reply_wait - send request thru doorbell interface
3813  * @ioc: per adapter object
3814  * @request_bytes: request length
3815  * @request: pointer having request payload
3816  * @reply_bytes: reply length
3817  * @reply: pointer to reply payload
3818  * @timeout: timeout in second
3819  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3820  *
3821  * Returns 0 for success, non-zero for failure.
3822  */
3823 static int
3824 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3825         u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3826 {
3827         MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3828         int i;
3829         u8 failed;
3830         u16 dummy;
3831         __le32 *mfp;
3832
3833         /* make sure doorbell is not in use */
3834         if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3835                 pr_err(MPT3SAS_FMT
3836                         "doorbell is in use (line=%d)\n",
3837                         ioc->name, __LINE__);
3838                 return -EFAULT;
3839         }
3840
3841         /* clear pending doorbell interrupts from previous state changes */
3842         if (readl(&ioc->chip->HostInterruptStatus) &
3843             MPI2_HIS_IOC2SYS_DB_STATUS)
3844                 writel(0, &ioc->chip->HostInterruptStatus);
3845
3846         /* send message to ioc */
3847         writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3848             ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3849             &ioc->chip->Doorbell);
3850
3851         if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3852                 pr_err(MPT3SAS_FMT
3853                         "doorbell handshake int failed (line=%d)\n",
3854                         ioc->name, __LINE__);
3855                 return -EFAULT;
3856         }
3857         writel(0, &ioc->chip->HostInterruptStatus);
3858
3859         if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3860                 pr_err(MPT3SAS_FMT
3861                         "doorbell handshake ack failed (line=%d)\n",
3862                         ioc->name, __LINE__);
3863                 return -EFAULT;
3864         }
3865
3866         /* send message 32-bits at a time */
3867         for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3868                 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3869                 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3870                         failed = 1;
3871         }
3872
3873         if (failed) {
3874                 pr_err(MPT3SAS_FMT
3875                         "doorbell handshake sending request failed (line=%d)\n",
3876                         ioc->name, __LINE__);
3877                 return -EFAULT;
3878         }
3879
3880         /* now wait for the reply */
3881         if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3882                 pr_err(MPT3SAS_FMT
3883                         "doorbell handshake int failed (line=%d)\n",
3884                         ioc->name, __LINE__);
3885                 return -EFAULT;
3886         }
3887
3888         /* read the first two 16-bits, it gives the total length of the reply */
3889         reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3890             & MPI2_DOORBELL_DATA_MASK);
3891         writel(0, &ioc->chip->HostInterruptStatus);
3892         if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3893                 pr_err(MPT3SAS_FMT
3894                         "doorbell handshake int failed (line=%d)\n",
3895                         ioc->name, __LINE__);
3896                 return -EFAULT;
3897         }
3898         reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3899             & MPI2_DOORBELL_DATA_MASK);
3900         writel(0, &ioc->chip->HostInterruptStatus);
3901
3902         for (i = 2; i < default_reply->MsgLength * 2; i++)  {
3903                 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3904                         pr_err(MPT3SAS_FMT
3905                                 "doorbell handshake int failed (line=%d)\n",
3906                                 ioc->name, __LINE__);
3907                         return -EFAULT;
3908                 }
3909                 if (i >=  reply_bytes/2) /* overflow case */
3910                         dummy = readl(&ioc->chip->Doorbell);
3911                 else
3912                         reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3913                             & MPI2_DOORBELL_DATA_MASK);
3914                 writel(0, &ioc->chip->HostInterruptStatus);
3915         }
3916
3917         _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3918         if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3919                 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3920                         "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3921         }
3922         writel(0, &ioc->chip->HostInterruptStatus);
3923
3924         if (ioc->logging_level & MPT_DEBUG_INIT) {
3925                 mfp = (__le32 *)reply;
3926                 pr_info("\toffset:data\n");
3927                 for (i = 0; i < reply_bytes/4; i++)
3928                         pr_info("\t[0x%02x]:%08x\n", i*4,
3929                             le32_to_cpu(mfp[i]));
3930         }
3931         return 0;
3932 }
3933
3934 /**
3935  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3936  * @ioc: per adapter object
3937  * @mpi_reply: the reply payload from FW
3938  * @mpi_request: the request payload sent to FW
3939  *
3940  * The SAS IO Unit Control Request message allows the host to perform low-level
3941  * operations, such as resets on the PHYs of the IO Unit, also allows the host
3942  * to obtain the IOC assigned device handles for a device if it has other
3943  * identifying information about the device, in addition allows the host to
3944  * remove IOC resources associated with the device.
3945  *
3946  * Returns 0 for success, non-zero for failure.
3947  */
3948 int
3949 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3950         Mpi2SasIoUnitControlReply_t *mpi_reply,
3951         Mpi2SasIoUnitControlRequest_t *mpi_request)
3952 {
3953         u16 smid;
3954         u32 ioc_state;
3955         unsigned long timeleft;
3956         bool issue_reset = false;
3957         int rc;
3958         void *request;
3959         u16 wait_state_count;
3960
3961         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3962             __func__));
3963
3964         mutex_lock(&ioc->base_cmds.mutex);
3965
3966         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3967                 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3968                     ioc->name, __func__);
3969                 rc = -EAGAIN;
3970                 goto out;
3971         }
3972
3973         wait_state_count = 0;
3974         ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3975         while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3976                 if (wait_state_count++ == 10) {
3977                         pr_err(MPT3SAS_FMT
3978                             "%s: failed due to ioc not operational\n",
3979                             ioc->name, __func__);
3980                         rc = -EFAULT;
3981                         goto out;
3982                 }
3983                 ssleep(1);
3984                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3985                 pr_info(MPT3SAS_FMT
3986                         "%s: waiting for operational state(count=%d)\n",
3987                         ioc->name, __func__, wait_state_count);
3988         }
3989
3990         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3991         if (!smid) {
3992                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3993                     ioc->name, __func__);
3994                 rc = -EAGAIN;
3995                 goto out;
3996         }
3997
3998         rc = 0;
3999         ioc->base_cmds.status = MPT3_CMD_PENDING;
4000         request = mpt3sas_base_get_msg_frame(ioc, smid);
4001         ioc->base_cmds.smid = smid;
4002         memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4003         if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4004             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4005                 ioc->ioc_link_reset_in_progress = 1;
4006         init_completion(&ioc->base_cmds.done);
4007         mpt3sas_base_put_smid_default(ioc, smid);
4008         timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4009             msecs_to_jiffies(10000));
4010         if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4011             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4012             ioc->ioc_link_reset_in_progress)
4013                 ioc->ioc_link_reset_in_progress = 0;
4014         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4015                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4016                     ioc->name, __func__);
4017                 _debug_dump_mf(mpi_request,
4018                     sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4019                 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4020                         issue_reset = true;
4021                 goto issue_host_reset;
4022         }
4023         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4024                 memcpy(mpi_reply, ioc->base_cmds.reply,
4025                     sizeof(Mpi2SasIoUnitControlReply_t));
4026         else
4027                 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4028         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4029         goto out;
4030
4031  issue_host_reset:
4032         if (issue_reset)
4033                 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4034                     FORCE_BIG_HAMMER);
4035         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4036         rc = -EFAULT;
4037  out:
4038         mutex_unlock(&ioc->base_cmds.mutex);
4039         return rc;
4040 }
4041
4042 /**
4043  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4044  * @ioc: per adapter object
4045  * @mpi_reply: the reply payload from FW
4046  * @mpi_request: the request payload sent to FW
4047  *
4048  * The SCSI Enclosure Processor request message causes the IOC to
4049  * communicate with SES devices to control LED status signals.
4050  *
4051  * Returns 0 for success, non-zero for failure.
4052  */
4053 int
4054 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4055         Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4056 {
4057         u16 smid;
4058         u32 ioc_state;
4059         unsigned long timeleft;
4060         bool issue_reset = false;
4061         int rc;
4062         void *request;
4063         u16 wait_state_count;
4064
4065         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4066             __func__));
4067
4068         mutex_lock(&ioc->base_cmds.mutex);
4069
4070         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4071                 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4072                     ioc->name, __func__);
4073                 rc = -EAGAIN;
4074                 goto out;
4075         }
4076
4077         wait_state_count = 0;
4078         ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4079         while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4080                 if (wait_state_count++ == 10) {
4081                         pr_err(MPT3SAS_FMT
4082                             "%s: failed due to ioc not operational\n",
4083                             ioc->name, __func__);
4084                         rc = -EFAULT;
4085                         goto out;
4086                 }
4087                 ssleep(1);
4088                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4089                 pr_info(MPT3SAS_FMT
4090                         "%s: waiting for operational state(count=%d)\n",
4091                         ioc->name,
4092                     __func__, wait_state_count);
4093         }
4094
4095         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4096         if (!smid) {
4097                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4098                     ioc->name, __func__);
4099                 rc = -EAGAIN;
4100                 goto out;
4101         }
4102
4103         rc = 0;
4104         ioc->base_cmds.status = MPT3_CMD_PENDING;
4105         request = mpt3sas_base_get_msg_frame(ioc, smid);
4106         ioc->base_cmds.smid = smid;
4107         memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4108         init_completion(&ioc->base_cmds.done);
4109         mpt3sas_base_put_smid_default(ioc, smid);
4110         timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4111             msecs_to_jiffies(10000));
4112         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4113                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4114                     ioc->name, __func__);
4115                 _debug_dump_mf(mpi_request,
4116                     sizeof(Mpi2SepRequest_t)/4);
4117                 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4118                         issue_reset = false;
4119                 goto issue_host_reset;
4120         }
4121         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4122                 memcpy(mpi_reply, ioc->base_cmds.reply,
4123                     sizeof(Mpi2SepReply_t));
4124         else
4125                 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4126         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4127         goto out;
4128
4129  issue_host_reset:
4130         if (issue_reset)
4131                 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4132                     FORCE_BIG_HAMMER);
4133         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4134         rc = -EFAULT;
4135  out:
4136         mutex_unlock(&ioc->base_cmds.mutex);
4137         return rc;
4138 }
4139
4140 /**
4141  * _base_get_port_facts - obtain port facts reply and save in ioc
4142  * @ioc: per adapter object
4143  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4144  *
4145  * Returns 0 for success, non-zero for failure.
4146  */
4147 static int
4148 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
4149 {
4150         Mpi2PortFactsRequest_t mpi_request;
4151         Mpi2PortFactsReply_t mpi_reply;
4152         struct mpt3sas_port_facts *pfacts;
4153         int mpi_reply_sz, mpi_request_sz, r;
4154
4155         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4156             __func__));
4157
4158         mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4159         mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4160         memset(&mpi_request, 0, mpi_request_sz);
4161         mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4162         mpi_request.PortNumber = port;
4163         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4164             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4165
4166         if (r != 0) {
4167                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4168                     ioc->name, __func__, r);
4169                 return r;
4170         }
4171
4172         pfacts = &ioc->pfacts[port];
4173         memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4174         pfacts->PortNumber = mpi_reply.PortNumber;
4175         pfacts->VP_ID = mpi_reply.VP_ID;
4176         pfacts->VF_ID = mpi_reply.VF_ID;
4177         pfacts->MaxPostedCmdBuffers =
4178             le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4179
4180         return 0;
4181 }
4182
4183 /**
4184  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4185  * @ioc: per adapter object
4186  * @timeout:
4187  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4188  *
4189  * Returns 0 for success, non-zero for failure.
4190  */
4191 static int
4192 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
4193         int sleep_flag)
4194 {
4195         u32 ioc_state;
4196         int rc;
4197
4198         dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4199             __func__));
4200
4201         if (ioc->pci_error_recovery) {
4202                 dfailprintk(ioc, printk(MPT3SAS_FMT
4203                     "%s: host in pci error recovery\n", ioc->name, __func__));
4204                 return -EFAULT;
4205         }
4206
4207         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4208         dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4209             ioc->name, __func__, ioc_state));
4210
4211         if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4212             (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4213                 return 0;
4214
4215         if (ioc_state & MPI2_DOORBELL_USED) {
4216                 dhsprintk(ioc, printk(MPT3SAS_FMT
4217                     "unexpected doorbell active!\n", ioc->name));
4218                 goto issue_diag_reset;
4219         }
4220
4221         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4222                 mpt3sas_base_fault_info(ioc, ioc_state &
4223                     MPI2_DOORBELL_DATA_MASK);
4224                 goto issue_diag_reset;
4225         }
4226
4227         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
4228             timeout, sleep_flag);
4229         if (ioc_state) {
4230                 dfailprintk(ioc, printk(MPT3SAS_FMT
4231                     "%s: failed going to ready state (ioc_state=0x%x)\n",
4232                     ioc->name, __func__, ioc_state));
4233                 return -EFAULT;
4234         }
4235
4236  issue_diag_reset:
4237         rc = _base_diag_reset(ioc, sleep_flag);
4238         return rc;
4239 }
4240
4241 /**
4242  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4243  * @ioc: per adapter object
4244  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4245  *
4246  * Returns 0 for success, non-zero for failure.
4247  */
4248 static int
4249 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4250 {
4251         Mpi2IOCFactsRequest_t mpi_request;
4252         Mpi2IOCFactsReply_t mpi_reply;
4253         struct mpt3sas_facts *facts;
4254         int mpi_reply_sz, mpi_request_sz, r;
4255
4256         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4257             __func__));
4258
4259         r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
4260         if (r) {
4261                 dfailprintk(ioc, printk(MPT3SAS_FMT
4262                     "%s: failed getting to correct state\n",
4263                     ioc->name, __func__));
4264                 return r;
4265         }
4266         mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4267         mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4268         memset(&mpi_request, 0, mpi_request_sz);
4269         mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4270         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4271             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4272
4273         if (r != 0) {
4274                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4275                     ioc->name, __func__, r);
4276                 return r;
4277         }
4278
4279         facts = &ioc->facts;
4280         memset(facts, 0, sizeof(struct mpt3sas_facts));
4281         facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4282         facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4283         facts->VP_ID = mpi_reply.VP_ID;
4284         facts->VF_ID = mpi_reply.VF_ID;
4285         facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4286         facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4287         facts->WhoInit = mpi_reply.WhoInit;
4288         facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4289         facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4290         facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4291         facts->MaxReplyDescriptorPostQueueDepth =
4292             le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4293         facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4294         facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4295         if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4296                 ioc->ir_firmware = 1;
4297         if ((facts->IOCCapabilities &
4298               MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4299                 ioc->rdpq_array_capable = 1;
4300         facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4301         facts->IOCRequestFrameSize =
4302             le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4303         facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4304         facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4305         ioc->shost->max_id = -1;
4306         facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4307         facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4308         facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4309         facts->HighPriorityCredit =
4310             le16_to_cpu(mpi_reply.HighPriorityCredit);
4311         facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4312         facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4313
4314         dinitprintk(ioc, pr_info(MPT3SAS_FMT
4315                 "hba queue depth(%d), max chains per io(%d)\n",
4316                 ioc->name, facts->RequestCredit,
4317             facts->MaxChainDepth));
4318         dinitprintk(ioc, pr_info(MPT3SAS_FMT
4319                 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4320             facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4321         return 0;
4322 }
4323
4324 /**
4325  * _base_send_ioc_init - send ioc_init to firmware
4326  * @ioc: per adapter object
4327  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4328  *
4329  * Returns 0 for success, non-zero for failure.
4330  */
4331 static int
4332 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4333 {
4334         Mpi2IOCInitRequest_t mpi_request;
4335         Mpi2IOCInitReply_t mpi_reply;
4336         int i, r = 0;
4337         struct timeval current_time;
4338         u16 ioc_status;
4339         u32 reply_post_free_array_sz = 0;
4340         Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4341         dma_addr_t reply_post_free_array_dma;
4342
4343         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4344             __func__));
4345
4346         memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4347         mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4348         mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4349         mpi_request.VF_ID = 0; /* TODO */
4350         mpi_request.VP_ID = 0;
4351         mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
4352         mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4353
4354         if (_base_is_controller_msix_enabled(ioc))
4355                 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4356         mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4357         mpi_request.ReplyDescriptorPostQueueDepth =
4358             cpu_to_le16(ioc->reply_post_queue_depth);
4359         mpi_request.ReplyFreeQueueDepth =
4360             cpu_to_le16(ioc->reply_free_queue_depth);
4361
4362         mpi_request.SenseBufferAddressHigh =
4363             cpu_to_le32((u64)ioc->sense_dma >> 32);
4364         mpi_request.SystemReplyAddressHigh =
4365             cpu_to_le32((u64)ioc->reply_dma >> 32);
4366         mpi_request.SystemRequestFrameBaseAddress =
4367             cpu_to_le64((u64)ioc->request_dma);
4368         mpi_request.ReplyFreeQueueAddress =
4369             cpu_to_le64((u64)ioc->reply_free_dma);
4370
4371         if (ioc->rdpq_array_enable) {
4372                 reply_post_free_array_sz = ioc->reply_queue_count *
4373                     sizeof(Mpi2IOCInitRDPQArrayEntry);
4374                 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4375                         reply_post_free_array_sz, &reply_post_free_array_dma);
4376                 if (!reply_post_free_array) {
4377                         pr_err(MPT3SAS_FMT
4378                         "reply_post_free_array: pci_alloc_consistent failed\n",
4379                         ioc->name);
4380                         r = -ENOMEM;
4381                         goto out;
4382                 }
4383                 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4384                 for (i = 0; i < ioc->reply_queue_count; i++)
4385                         reply_post_free_array[i].RDPQBaseAddress =
4386                             cpu_to_le64(
4387                                 (u64)ioc->reply_post[i].reply_post_free_dma);
4388                 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4389                 mpi_request.ReplyDescriptorPostQueueAddress =
4390                     cpu_to_le64((u64)reply_post_free_array_dma);
4391         } else {
4392                 mpi_request.ReplyDescriptorPostQueueAddress =
4393                     cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4394         }
4395
4396         /* This time stamp specifies number of milliseconds
4397          * since epoch ~ midnight January 1, 1970.
4398          */
4399         do_gettimeofday(&current_time);
4400         mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
4401             (current_time.tv_usec / 1000));
4402
4403         if (ioc->logging_level & MPT_DEBUG_INIT) {
4404                 __le32 *mfp;
4405                 int i;
4406
4407                 mfp = (__le32 *)&mpi_request;
4408                 pr_info("\toffset:data\n");
4409                 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4410                         pr_info("\t[0x%02x]:%08x\n", i*4,
4411                             le32_to_cpu(mfp[i]));
4412         }
4413
4414         r = _base_handshake_req_reply_wait(ioc,
4415             sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4416             sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4417             sleep_flag);
4418
4419         if (r != 0) {
4420                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4421                     ioc->name, __func__, r);
4422                 goto out;
4423         }
4424
4425         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4426         if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4427             mpi_reply.IOCLogInfo) {
4428                 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4429                 r = -EIO;
4430         }
4431
4432 out:
4433         if (reply_post_free_array)
4434                 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4435                                     reply_post_free_array,
4436                                     reply_post_free_array_dma);
4437         return r;
4438 }
4439
4440 /**
4441  * mpt3sas_port_enable_done - command completion routine for port enable
4442  * @ioc: per adapter object
4443  * @smid: system request message index
4444  * @msix_index: MSIX table index supplied by the OS
4445  * @reply: reply message frame(lower 32bit addr)
4446  *
4447  * Return 1 meaning mf should be freed from _base_interrupt
4448  *        0 means the mf is freed from this function.
4449  */
4450 u8
4451 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4452         u32 reply)
4453 {
4454         MPI2DefaultReply_t *mpi_reply;
4455         u16 ioc_status;
4456
4457         if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4458                 return 1;
4459
4460         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4461         if (!mpi_reply)
4462                 return 1;
4463
4464         if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4465                 return 1;
4466
4467         ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4468         ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4469         ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4470         memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4471         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4472         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4473                 ioc->port_enable_failed = 1;
4474
4475         if (ioc->is_driver_loading) {
4476                 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4477                         mpt3sas_port_enable_complete(ioc);
4478                         return 1;
4479                 } else {
4480                         ioc->start_scan_failed = ioc_status;
4481                         ioc->start_scan = 0;
4482                         return 1;
4483                 }
4484         }
4485         complete(&ioc->port_enable_cmds.done);
4486         return 1;
4487 }
4488
4489 /**
4490  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4491  * @ioc: per adapter object
4492  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4493  *
4494  * Returns 0 for success, non-zero for failure.
4495  */
4496 static int
4497 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4498 {
4499         Mpi2PortEnableRequest_t *mpi_request;
4500         Mpi2PortEnableReply_t *mpi_reply;
4501         unsigned long timeleft;
4502         int r = 0;
4503         u16 smid;
4504         u16 ioc_status;
4505
4506         pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4507
4508         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4509                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4510                     ioc->name, __func__);
4511                 return -EAGAIN;
4512         }
4513
4514         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4515         if (!smid) {
4516                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4517                     ioc->name, __func__);
4518                 return -EAGAIN;
4519         }
4520
4521         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4522         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4523         ioc->port_enable_cmds.smid = smid;
4524         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4525         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4526
4527         init_completion(&ioc->port_enable_cmds.done);
4528         mpt3sas_base_put_smid_default(ioc, smid);
4529         timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4530             300*HZ);
4531         if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4532                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4533                     ioc->name, __func__);
4534                 _debug_dump_mf(mpi_request,
4535                     sizeof(Mpi2PortEnableRequest_t)/4);
4536                 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4537                         r = -EFAULT;
4538                 else
4539                         r = -ETIME;
4540                 goto out;
4541         }
4542
4543         mpi_reply = ioc->port_enable_cmds.reply;
4544         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4545         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4546                 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4547                     ioc->name, __func__, ioc_status);
4548                 r = -EFAULT;
4549                 goto out;
4550         }
4551
4552  out:
4553         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4554         pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4555             "SUCCESS" : "FAILED"));
4556         return r;
4557 }
4558
4559 /**
4560  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4561  * @ioc: per adapter object
4562  *
4563  * Returns 0 for success, non-zero for failure.
4564  */
4565 int
4566 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4567 {
4568         Mpi2PortEnableRequest_t *mpi_request;
4569         u16 smid;
4570
4571         pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4572
4573         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4574                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4575                     ioc->name, __func__);
4576                 return -EAGAIN;
4577         }
4578
4579         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4580         if (!smid) {
4581                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4582                     ioc->name, __func__);
4583                 return -EAGAIN;
4584         }
4585
4586         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4587         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4588         ioc->port_enable_cmds.smid = smid;
4589         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4590         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4591
4592         mpt3sas_base_put_smid_default(ioc, smid);
4593         return 0;
4594 }
4595
4596 /**
4597  * _base_determine_wait_on_discovery - desposition
4598  * @ioc: per adapter object
4599  *
4600  * Decide whether to wait on discovery to complete. Used to either
4601  * locate boot device, or report volumes ahead of physical devices.
4602  *
4603  * Returns 1 for wait, 0 for don't wait
4604  */
4605 static int
4606 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4607 {
4608         /* We wait for discovery to complete if IR firmware is loaded.
4609          * The sas topology events arrive before PD events, so we need time to
4610          * turn on the bit in ioc->pd_handles to indicate PD
4611          * Also, it maybe required to report Volumes ahead of physical
4612          * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4613          */
4614         if (ioc->ir_firmware)
4615                 return 1;
4616
4617         /* if no Bios, then we don't need to wait */
4618         if (!ioc->bios_pg3.BiosVersion)
4619                 return 0;
4620
4621         /* Bios is present, then we drop down here.
4622          *
4623          * If there any entries in the Bios Page 2, then we wait
4624          * for discovery to complete.
4625          */
4626
4627         /* Current Boot Device */
4628         if ((ioc->bios_pg2.CurrentBootDeviceForm &
4629             MPI2_BIOSPAGE2_FORM_MASK) ==
4630             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4631         /* Request Boot Device */
4632            (ioc->bios_pg2.ReqBootDeviceForm &
4633             MPI2_BIOSPAGE2_FORM_MASK) ==
4634             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4635         /* Alternate Request Boot Device */
4636            (ioc->bios_pg2.ReqAltBootDeviceForm &
4637             MPI2_BIOSPAGE2_FORM_MASK) ==
4638             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4639                 return 0;
4640
4641         return 1;
4642 }
4643
4644 /**
4645  * _base_unmask_events - turn on notification for this event
4646  * @ioc: per adapter object
4647  * @event: firmware event
4648  *
4649  * The mask is stored in ioc->event_masks.
4650  */
4651 static void
4652 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4653 {
4654         u32 desired_event;
4655
4656         if (event >= 128)
4657                 return;
4658
4659         desired_event = (1 << (event % 32));
4660
4661         if (event < 32)
4662                 ioc->event_masks[0] &= ~desired_event;
4663         else if (event < 64)
4664                 ioc->event_masks[1] &= ~desired_event;
4665         else if (event < 96)
4666                 ioc->event_masks[2] &= ~desired_event;
4667         else if (event < 128)
4668                 ioc->event_masks[3] &= ~desired_event;
4669 }
4670
4671 /**
4672  * _base_event_notification - send event notification
4673  * @ioc: per adapter object
4674  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4675  *
4676  * Returns 0 for success, non-zero for failure.
4677  */
4678 static int
4679 _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4680 {
4681         Mpi2EventNotificationRequest_t *mpi_request;
4682         unsigned long timeleft;
4683         u16 smid;
4684         int r = 0;
4685         int i;
4686
4687         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4688             __func__));
4689
4690         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4691                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4692                     ioc->name, __func__);
4693                 return -EAGAIN;
4694         }
4695
4696         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4697         if (!smid) {
4698                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4699                     ioc->name, __func__);
4700                 return -EAGAIN;
4701         }
4702         ioc->base_cmds.status = MPT3_CMD_PENDING;
4703         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4704         ioc->base_cmds.smid = smid;
4705         memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4706         mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4707         mpi_request->VF_ID = 0; /* TODO */
4708         mpi_request->VP_ID = 0;
4709         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4710                 mpi_request->EventMasks[i] =
4711                     cpu_to_le32(ioc->event_masks[i]);
4712         init_completion(&ioc->base_cmds.done);
4713         mpt3sas_base_put_smid_default(ioc, smid);
4714         timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4715         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4716                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4717                     ioc->name, __func__);
4718                 _debug_dump_mf(mpi_request,
4719                     sizeof(Mpi2EventNotificationRequest_t)/4);
4720                 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4721                         r = -EFAULT;
4722                 else
4723                         r = -ETIME;
4724         } else
4725                 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4726                     ioc->name, __func__));
4727         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4728         return r;
4729 }
4730
4731 /**
4732  * mpt3sas_base_validate_event_type - validating event types
4733  * @ioc: per adapter object
4734  * @event: firmware event
4735  *
4736  * This will turn on firmware event notification when application
4737  * ask for that event. We don't mask events that are already enabled.
4738  */
4739 void
4740 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4741 {
4742         int i, j;
4743         u32 event_mask, desired_event;
4744         u8 send_update_to_fw;
4745
4746         for (i = 0, send_update_to_fw = 0; i <
4747             MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4748                 event_mask = ~event_type[i];
4749                 desired_event = 1;
4750                 for (j = 0; j < 32; j++) {
4751                         if (!(event_mask & desired_event) &&
4752                             (ioc->event_masks[i] & desired_event)) {
4753                                 ioc->event_masks[i] &= ~desired_event;
4754                                 send_update_to_fw = 1;
4755                         }
4756                         desired_event = (desired_event << 1);
4757                 }
4758         }
4759
4760         if (!send_update_to_fw)
4761                 return;
4762
4763         mutex_lock(&ioc->base_cmds.mutex);
4764         _base_event_notification(ioc, CAN_SLEEP);
4765         mutex_unlock(&ioc->base_cmds.mutex);
4766 }
4767
4768 /**
4769  * _base_diag_reset - the "big hammer" start of day reset
4770  * @ioc: per adapter object
4771  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4772  *
4773  * Returns 0 for success, non-zero for failure.
4774  */
4775 static int
4776 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4777 {
4778         u32 host_diagnostic;
4779         u32 ioc_state;
4780         u32 count;
4781         u32 hcb_size;
4782
4783         pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4784
4785         drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4786             ioc->name));
4787
4788         count = 0;
4789         do {
4790                 /* Write magic sequence to WriteSequence register
4791                  * Loop until in diagnostic mode
4792                  */
4793                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4794                         "write magic sequence\n", ioc->name));
4795                 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4796                 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4797                 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4798                 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4799                 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4800                 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4801                 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4802
4803                 /* wait 100 msec */
4804                 if (sleep_flag == CAN_SLEEP)
4805                         msleep(100);
4806                 else
4807                         mdelay(100);
4808
4809                 if (count++ > 20)
4810                         goto out;
4811
4812                 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4813                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4814                         "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4815                     ioc->name, count, host_diagnostic));
4816
4817         } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4818
4819         hcb_size = readl(&ioc->chip->HCBSize);
4820
4821         drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4822             ioc->name));
4823         writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4824              &ioc->chip->HostDiagnostic);
4825
4826         /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4827         if (sleep_flag == CAN_SLEEP)
4828                 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4829         else
4830                 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4831
4832         /* Approximately 300 second max wait */
4833         for (count = 0; count < (300000000 /
4834                 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4835
4836                 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4837
4838                 if (host_diagnostic == 0xFFFFFFFF)
4839                         goto out;
4840                 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4841                         break;
4842
4843                 /* Wait to pass the second read delay window */
4844                 if (sleep_flag == CAN_SLEEP)
4845                         msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4846                                                                 / 1000);
4847                 else
4848                         mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4849                                                                 / 1000);
4850         }
4851
4852         if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4853
4854                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4855                 "restart the adapter assuming the HCB Address points to good F/W\n",
4856                     ioc->name));
4857                 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4858                 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4859                 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4860
4861                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4862                     "re-enable the HCDW\n", ioc->name));
4863                 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4864                     &ioc->chip->HCBSize);
4865         }
4866
4867         drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4868             ioc->name));
4869         writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4870             &ioc->chip->HostDiagnostic);
4871
4872         drsprintk(ioc, pr_info(MPT3SAS_FMT
4873                 "disable writes to the diagnostic register\n", ioc->name));
4874         writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4875
4876         drsprintk(ioc, pr_info(MPT3SAS_FMT
4877                 "Wait for FW to go to the READY state\n", ioc->name));
4878         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4879             sleep_flag);
4880         if (ioc_state) {
4881                 pr_err(MPT3SAS_FMT
4882                         "%s: failed going to ready state (ioc_state=0x%x)\n",
4883                         ioc->name, __func__, ioc_state);
4884                 goto out;
4885         }
4886
4887         pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4888         return 0;
4889
4890  out:
4891         pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4892         return -EFAULT;
4893 }
4894
4895 /**
4896  * _base_make_ioc_ready - put controller in READY state
4897  * @ioc: per adapter object
4898  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4899  * @type: FORCE_BIG_HAMMER or SOFT_RESET
4900  *
4901  * Returns 0 for success, non-zero for failure.
4902  */
4903 static int
4904 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4905         enum reset_type type)
4906 {
4907         u32 ioc_state;
4908         int rc;
4909         int count;
4910
4911         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4912             __func__));
4913
4914         if (ioc->pci_error_recovery)
4915                 return 0;
4916
4917         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4918         dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4919             ioc->name, __func__, ioc_state));
4920
4921         /* if in RESET state, it should move to READY state shortly */
4922         count = 0;
4923         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4924                 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4925                     MPI2_IOC_STATE_READY) {
4926                         if (count++ == 10) {
4927                                 pr_err(MPT3SAS_FMT
4928                                         "%s: failed going to ready state (ioc_state=0x%x)\n",
4929                                     ioc->name, __func__, ioc_state);
4930                                 return -EFAULT;
4931                         }
4932                         if (sleep_flag == CAN_SLEEP)
4933                                 ssleep(1);
4934                         else
4935                                 mdelay(1000);
4936                         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4937                 }
4938         }
4939
4940         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4941                 return 0;
4942
4943         if (ioc_state & MPI2_DOORBELL_USED) {
4944                 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4945                         "unexpected doorbell active!\n",
4946                         ioc->name));
4947                 goto issue_diag_reset;
4948         }
4949
4950         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4951                 mpt3sas_base_fault_info(ioc, ioc_state &
4952                     MPI2_DOORBELL_DATA_MASK);
4953                 goto issue_diag_reset;
4954         }
4955
4956         if (type == FORCE_BIG_HAMMER)
4957                 goto issue_diag_reset;
4958
4959         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4960                 if (!(_base_send_ioc_reset(ioc,
4961                     MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4962                         return 0;
4963         }
4964
4965  issue_diag_reset:
4966         rc = _base_diag_reset(ioc, CAN_SLEEP);
4967         return rc;
4968 }
4969
4970 /**
4971  * _base_make_ioc_operational - put controller in OPERATIONAL state
4972  * @ioc: per adapter object
4973  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4974  *
4975  * Returns 0 for success, non-zero for failure.
4976  */
4977 static int
4978 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4979 {
4980         int r, i;
4981         unsigned long   flags;
4982         u32 reply_address;
4983         u16 smid;
4984         struct _tr_list *delayed_tr, *delayed_tr_next;
4985         u8 hide_flag;
4986         struct adapter_reply_queue *reply_q;
4987         long reply_post_free;
4988         u32 reply_post_free_sz, index = 0;
4989
4990         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4991             __func__));
4992
4993         /* clean the delayed target reset list */
4994         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4995             &ioc->delayed_tr_list, list) {
4996                 list_del(&delayed_tr->list);
4997                 kfree(delayed_tr);
4998         }
4999
5000
5001         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5002             &ioc->delayed_tr_volume_list, list) {
5003                 list_del(&delayed_tr->list);
5004                 kfree(delayed_tr);
5005         }
5006
5007         /* initialize the scsi lookup free list */
5008         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5009         INIT_LIST_HEAD(&ioc->free_list);
5010         smid = 1;
5011         for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5012                 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5013                 ioc->scsi_lookup[i].cb_idx = 0xFF;
5014                 ioc->scsi_lookup[i].smid = smid;
5015                 ioc->scsi_lookup[i].scmd = NULL;
5016                 ioc->scsi_lookup[i].direct_io = 0;
5017                 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5018                     &ioc->free_list);
5019         }
5020
5021         /* hi-priority queue */
5022         INIT_LIST_HEAD(&ioc->hpr_free_list);
5023         smid = ioc->hi_priority_smid;
5024         for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5025                 ioc->hpr_lookup[i].cb_idx = 0xFF;
5026                 ioc->hpr_lookup[i].smid = smid;
5027                 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5028                     &ioc->hpr_free_list);
5029         }
5030
5031         /* internal queue */
5032         INIT_LIST_HEAD(&ioc->internal_free_list);
5033         smid = ioc->internal_smid;
5034         for (i = 0; i < ioc->internal_depth; i++, smid++) {
5035                 ioc->internal_lookup[i].cb_idx = 0xFF;
5036                 ioc->internal_lookup[i].smid = smid;
5037                 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5038                     &ioc->internal_free_list);
5039         }
5040
5041         /* chain pool */
5042         INIT_LIST_HEAD(&ioc->free_chain_list);
5043         for (i = 0; i < ioc->chain_depth; i++)
5044                 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5045                     &ioc->free_chain_list);
5046
5047         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5048
5049         /* initialize Reply Free Queue */
5050         for (i = 0, reply_address = (u32)ioc->reply_dma ;
5051             i < ioc->reply_free_queue_depth ; i++, reply_address +=
5052             ioc->reply_sz)
5053                 ioc->reply_free[i] = cpu_to_le32(reply_address);
5054
5055         /* initialize reply queues */
5056         if (ioc->is_driver_loading)
5057                 _base_assign_reply_queues(ioc);
5058
5059         /* initialize Reply Post Free Queue */
5060         reply_post_free_sz = ioc->reply_post_queue_depth *
5061             sizeof(Mpi2DefaultReplyDescriptor_t);
5062         reply_post_free = (long)ioc->reply_post[index].reply_post_free;
5063         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5064                 reply_q->reply_post_host_index = 0;
5065                 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
5066                     reply_post_free;
5067                 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5068                         reply_q->reply_post_free[i].Words =
5069                             cpu_to_le64(ULLONG_MAX);
5070                 if (!_base_is_controller_msix_enabled(ioc))
5071                         goto skip_init_reply_post_free_queue;
5072                 /*
5073                  * If RDPQ is enabled, switch to the next allocation.
5074                  * Otherwise advance within the contiguous region.
5075                  */
5076                 if (ioc->rdpq_array_enable)
5077                         reply_post_free = (long)
5078                             ioc->reply_post[++index].reply_post_free;
5079                 else
5080                         reply_post_free += reply_post_free_sz;
5081         }
5082  skip_init_reply_post_free_queue:
5083
5084         r = _base_send_ioc_init(ioc, sleep_flag);
5085         if (r)
5086                 return r;
5087
5088         /* initialize reply free host index */
5089         ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5090         writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5091
5092         /* initialize reply post host index */
5093         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5094                 if (ioc->msix96_vector)
5095                         writel((reply_q->msix_index & 7)<<
5096                            MPI2_RPHI_MSIX_INDEX_SHIFT,
5097                            ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5098                 else
5099                         writel(reply_q->msix_index <<
5100                                 MPI2_RPHI_MSIX_INDEX_SHIFT,
5101                                 &ioc->chip->ReplyPostHostIndex);
5102
5103                 if (!_base_is_controller_msix_enabled(ioc))
5104                         goto skip_init_reply_post_host_index;
5105         }
5106
5107  skip_init_reply_post_host_index:
5108
5109         _base_unmask_interrupts(ioc);
5110         r = _base_event_notification(ioc, sleep_flag);
5111         if (r)
5112                 return r;
5113
5114         if (sleep_flag == CAN_SLEEP)
5115                 _base_static_config_pages(ioc);
5116
5117
5118         if (ioc->is_driver_loading) {
5119
5120                 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5121                     == 0x80) {
5122                         hide_flag = (u8) (
5123                             le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5124                             MFG_PAGE10_HIDE_SSDS_MASK);
5125                         if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5126                                 ioc->mfg_pg10_hide_flag = hide_flag;
5127                 }
5128
5129                 ioc->wait_for_discovery_to_complete =
5130                     _base_determine_wait_on_discovery(ioc);
5131
5132                 return r; /* scan_start and scan_finished support */
5133         }
5134
5135         r = _base_send_port_enable(ioc, sleep_flag);
5136         if (r)
5137                 return r;
5138
5139         return r;
5140 }
5141
5142 /**
5143  * mpt3sas_base_free_resources - free resources controller resources
5144  * @ioc: per adapter object
5145  *
5146  * Return nothing.
5147  */
5148 void
5149 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5150 {
5151         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5152             __func__));
5153
5154         /* synchronizing freeing resource with pci_access_mutex lock */
5155         mutex_lock(&ioc->pci_access_mutex);
5156         if (ioc->chip_phys && ioc->chip) {
5157                 _base_mask_interrupts(ioc);
5158                 ioc->shost_recovery = 1;
5159                 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5160                 ioc->shost_recovery = 0;
5161         }
5162
5163         mpt3sas_base_unmap_resources(ioc);
5164         mutex_unlock(&ioc->pci_access_mutex);
5165         return;
5166 }
5167
5168 /**
5169  * mpt3sas_base_attach - attach controller instance
5170  * @ioc: per adapter object
5171  *
5172  * Returns 0 for success, non-zero for failure.
5173  */
5174 int
5175 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5176 {
5177         int r, i;
5178         int cpu_id, last_cpu_id = 0;
5179
5180         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5181             __func__));
5182
5183         /* setup cpu_msix_table */
5184         ioc->cpu_count = num_online_cpus();
5185         for_each_online_cpu(cpu_id)
5186                 last_cpu_id = cpu_id;
5187         ioc->cpu_msix_table_sz = last_cpu_id + 1;
5188         ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5189         ioc->reply_queue_count = 1;
5190         if (!ioc->cpu_msix_table) {
5191                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5192                         "allocation for cpu_msix_table failed!!!\n",
5193                         ioc->name));
5194                 r = -ENOMEM;
5195                 goto out_free_resources;
5196         }
5197
5198         if (ioc->is_warpdrive) {
5199                 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5200                     sizeof(resource_size_t *), GFP_KERNEL);
5201                 if (!ioc->reply_post_host_index) {
5202                         dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5203                                 "for cpu_msix_table failed!!!\n", ioc->name));
5204                         r = -ENOMEM;
5205                         goto out_free_resources;
5206                 }
5207         }
5208
5209         ioc->rdpq_array_enable_assigned = 0;
5210         ioc->dma_mask = 0;
5211         r = mpt3sas_base_map_resources(ioc);
5212         if (r)
5213                 goto out_free_resources;
5214
5215         pci_set_drvdata(ioc->pdev, ioc->shost);
5216         r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5217         if (r)
5218                 goto out_free_resources;
5219
5220         switch (ioc->hba_mpi_version_belonged) {
5221         case MPI2_VERSION:
5222                 ioc->build_sg_scmd = &_base_build_sg_scmd;
5223                 ioc->build_sg = &_base_build_sg;
5224                 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5225                 break;
5226         case MPI25_VERSION:
5227                 /*
5228                  * In SAS3.0,
5229                  * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5230                  * Target Status - all require the IEEE formated scatter gather
5231                  * elements.
5232                  */
5233                 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5234                 ioc->build_sg = &_base_build_sg_ieee;
5235                 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5236                 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5237                 break;
5238         }
5239
5240         /*
5241          * These function pointers for other requests that don't
5242          * the require IEEE scatter gather elements.
5243          *
5244          * For example Configuration Pages and SAS IOUNIT Control don't.
5245          */
5246         ioc->build_sg_mpi = &_base_build_sg;
5247         ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5248
5249         r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5250         if (r)
5251                 goto out_free_resources;
5252
5253         ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5254             sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5255         if (!ioc->pfacts) {
5256                 r = -ENOMEM;
5257                 goto out_free_resources;
5258         }
5259
5260         for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5261                 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
5262                 if (r)
5263                         goto out_free_resources;
5264         }
5265
5266         r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
5267         if (r)
5268                 goto out_free_resources;
5269
5270         init_waitqueue_head(&ioc->reset_wq);
5271
5272         /* allocate memory pd handle bitmask list */
5273         ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5274         if (ioc->facts.MaxDevHandle % 8)
5275                 ioc->pd_handles_sz++;
5276         ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5277             GFP_KERNEL);
5278         if (!ioc->pd_handles) {
5279                 r = -ENOMEM;
5280                 goto out_free_resources;
5281         }
5282         ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5283             GFP_KERNEL);
5284         if (!ioc->blocking_handles) {
5285                 r = -ENOMEM;
5286                 goto out_free_resources;
5287         }
5288
5289         ioc->fwfault_debug = mpt3sas_fwfault_debug;
5290
5291         /* base internal command bits */
5292         mutex_init(&ioc->base_cmds.mutex);
5293         ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5294         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5295
5296         /* port_enable command bits */
5297         ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5298         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5299
5300         /* transport internal command bits */
5301         ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5302         ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5303         mutex_init(&ioc->transport_cmds.mutex);
5304
5305         /* scsih internal command bits */
5306         ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5307         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5308         mutex_init(&ioc->scsih_cmds.mutex);
5309
5310         /* task management internal command bits */
5311         ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5312         ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5313         mutex_init(&ioc->tm_cmds.mutex);
5314
5315         /* config page internal command bits */
5316         ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5317         ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5318         mutex_init(&ioc->config_cmds.mutex);
5319
5320         /* ctl module internal command bits */
5321         ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5322         ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5323         ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5324         mutex_init(&ioc->ctl_cmds.mutex);
5325
5326         if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5327             !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5328             !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5329             !ioc->ctl_cmds.sense) {
5330                 r = -ENOMEM;
5331                 goto out_free_resources;
5332         }
5333
5334         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5335                 ioc->event_masks[i] = -1;
5336
5337         /* here we enable the events we care about */
5338         _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5339         _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5340         _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5341         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5342         _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5343         _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5344         _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5345         _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5346         _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5347         _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
5348         _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
5349
5350         r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5351         if (r)
5352                 goto out_free_resources;
5353
5354         ioc->non_operational_loop = 0;
5355         return 0;
5356
5357  out_free_resources:
5358
5359         ioc->remove_host = 1;
5360
5361         mpt3sas_base_free_resources(ioc);
5362         _base_release_memory_pools(ioc);
5363         pci_set_drvdata(ioc->pdev, NULL);
5364         kfree(ioc->cpu_msix_table);
5365         if (ioc->is_warpdrive)
5366                 kfree(ioc->reply_post_host_index);
5367         kfree(ioc->pd_handles);
5368         kfree(ioc->blocking_handles);
5369         kfree(ioc->tm_cmds.reply);
5370         kfree(ioc->transport_cmds.reply);
5371         kfree(ioc->scsih_cmds.reply);
5372         kfree(ioc->config_cmds.reply);
5373         kfree(ioc->base_cmds.reply);
5374         kfree(ioc->port_enable_cmds.reply);
5375         kfree(ioc->ctl_cmds.reply);
5376         kfree(ioc->ctl_cmds.sense);
5377         kfree(ioc->pfacts);
5378         ioc->ctl_cmds.reply = NULL;
5379         ioc->base_cmds.reply = NULL;
5380         ioc->tm_cmds.reply = NULL;
5381         ioc->scsih_cmds.reply = NULL;
5382         ioc->transport_cmds.reply = NULL;
5383         ioc->config_cmds.reply = NULL;
5384         ioc->pfacts = NULL;
5385         return r;
5386 }
5387
5388
5389 /**
5390  * mpt3sas_base_detach - remove controller instance
5391  * @ioc: per adapter object
5392  *
5393  * Return nothing.
5394  */
5395 void
5396 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5397 {
5398         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5399             __func__));
5400
5401         mpt3sas_base_stop_watchdog(ioc);
5402         mpt3sas_base_free_resources(ioc);
5403         _base_release_memory_pools(ioc);
5404         pci_set_drvdata(ioc->pdev, NULL);
5405         kfree(ioc->cpu_msix_table);
5406         if (ioc->is_warpdrive)
5407                 kfree(ioc->reply_post_host_index);
5408         kfree(ioc->pd_handles);
5409         kfree(ioc->blocking_handles);
5410         kfree(ioc->pfacts);
5411         kfree(ioc->ctl_cmds.reply);
5412         kfree(ioc->ctl_cmds.sense);
5413         kfree(ioc->base_cmds.reply);
5414         kfree(ioc->port_enable_cmds.reply);
5415         kfree(ioc->tm_cmds.reply);
5416         kfree(ioc->transport_cmds.reply);
5417         kfree(ioc->scsih_cmds.reply);
5418         kfree(ioc->config_cmds.reply);
5419 }
5420
5421 /**
5422  * _base_reset_handler - reset callback handler (for base)
5423  * @ioc: per adapter object
5424  * @reset_phase: phase
5425  *
5426  * The handler for doing any required cleanup or initialization.
5427  *
5428  * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5429  * MPT3_IOC_DONE_RESET
5430  *
5431  * Return nothing.
5432  */
5433 static void
5434 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5435 {
5436         mpt3sas_scsih_reset_handler(ioc, reset_phase);
5437         mpt3sas_ctl_reset_handler(ioc, reset_phase);
5438         switch (reset_phase) {
5439         case MPT3_IOC_PRE_RESET:
5440                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5441                 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5442                 break;
5443         case MPT3_IOC_AFTER_RESET:
5444                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5445                 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5446                 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5447                         ioc->transport_cmds.status |= MPT3_CMD_RESET;
5448                         mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5449                         complete(&ioc->transport_cmds.done);
5450                 }
5451                 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5452                         ioc->base_cmds.status |= MPT3_CMD_RESET;
5453                         mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5454                         complete(&ioc->base_cmds.done);
5455                 }
5456                 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5457                         ioc->port_enable_failed = 1;
5458                         ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5459                         mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5460                         if (ioc->is_driver_loading) {
5461                                 ioc->start_scan_failed =
5462                                     MPI2_IOCSTATUS_INTERNAL_ERROR;
5463                                 ioc->start_scan = 0;
5464                                 ioc->port_enable_cmds.status =
5465                                     MPT3_CMD_NOT_USED;
5466                         } else
5467                                 complete(&ioc->port_enable_cmds.done);
5468                 }
5469                 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5470                         ioc->config_cmds.status |= MPT3_CMD_RESET;
5471                         mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5472                         ioc->config_cmds.smid = USHRT_MAX;
5473                         complete(&ioc->config_cmds.done);
5474                 }
5475                 break;
5476         case MPT3_IOC_DONE_RESET:
5477                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5478                         "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5479                 break;
5480         }
5481 }
5482
5483 /**
5484  * _wait_for_commands_to_complete - reset controller
5485  * @ioc: Pointer to MPT_ADAPTER structure
5486  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5487  *
5488  * This function waiting(3s) for all pending commands to complete
5489  * prior to putting controller in reset.
5490  */
5491 static void
5492 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5493 {
5494         u32 ioc_state;
5495         unsigned long flags;
5496         u16 i;
5497
5498         ioc->pending_io_count = 0;
5499         if (sleep_flag != CAN_SLEEP)
5500                 return;
5501
5502         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5503         if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5504                 return;
5505
5506         /* pending command count */
5507         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5508         for (i = 0; i < ioc->scsiio_depth; i++)
5509                 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5510                         ioc->pending_io_count++;
5511         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5512
5513         if (!ioc->pending_io_count)
5514                 return;
5515
5516         /* wait for pending commands to complete */
5517         wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5518 }
5519
5520 /**
5521  * mpt3sas_base_hard_reset_handler - reset controller
5522  * @ioc: Pointer to MPT_ADAPTER structure
5523  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5524  * @type: FORCE_BIG_HAMMER or SOFT_RESET
5525  *
5526  * Returns 0 for success, non-zero for failure.
5527  */
5528 int
5529 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5530         enum reset_type type)
5531 {
5532         int r;
5533         unsigned long flags;
5534         u32 ioc_state;
5535         u8 is_fault = 0, is_trigger = 0;
5536
5537         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5538             __func__));
5539
5540         if (ioc->pci_error_recovery) {
5541                 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5542                     ioc->name, __func__);
5543                 r = 0;
5544                 goto out_unlocked;
5545         }
5546
5547         if (mpt3sas_fwfault_debug)
5548                 mpt3sas_halt_firmware(ioc);
5549
5550         /* TODO - What we really should be doing is pulling
5551          * out all the code associated with NO_SLEEP; its never used.
5552          * That is legacy code from mpt fusion driver, ported over.
5553          * I will leave this BUG_ON here for now till its been resolved.
5554          */
5555         BUG_ON(sleep_flag == NO_SLEEP);
5556
5557         /* wait for an active reset in progress to complete */
5558         if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5559                 do {
5560                         ssleep(1);
5561                 } while (ioc->shost_recovery == 1);
5562                 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5563                     __func__));
5564                 return ioc->ioc_reset_in_progress_status;
5565         }
5566
5567         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5568         ioc->shost_recovery = 1;
5569         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5570
5571         if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5572             MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5573             (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5574             MPT3_DIAG_BUFFER_IS_RELEASED))) {
5575                 is_trigger = 1;
5576                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5577                 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5578                         is_fault = 1;
5579         }
5580         _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5581         _wait_for_commands_to_complete(ioc, sleep_flag);
5582         _base_mask_interrupts(ioc);
5583         r = _base_make_ioc_ready(ioc, sleep_flag, type);
5584         if (r)
5585                 goto out;
5586         _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5587
5588         /* If this hard reset is called while port enable is active, then
5589          * there is no reason to call make_ioc_operational
5590          */
5591         if (ioc->is_driver_loading && ioc->port_enable_failed) {
5592                 ioc->remove_host = 1;
5593                 r = -EFAULT;
5594                 goto out;
5595         }
5596         r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5597         if (r)
5598                 goto out;
5599
5600         if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5601                 panic("%s: Issue occurred with flashing controller firmware."
5602                       "Please reboot the system and ensure that the correct"
5603                       " firmware version is running\n", ioc->name);
5604
5605         r = _base_make_ioc_operational(ioc, sleep_flag);
5606         if (!r)
5607                 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5608
5609  out:
5610         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5611             ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5612
5613         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5614         ioc->ioc_reset_in_progress_status = r;
5615         ioc->shost_recovery = 0;
5616         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5617         ioc->ioc_reset_count++;
5618         mutex_unlock(&ioc->reset_in_progress_mutex);
5619
5620  out_unlocked:
5621         if ((r == 0) && is_trigger) {
5622                 if (is_fault)
5623                         mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5624                 else
5625                         mpt3sas_trigger_master(ioc,
5626                             MASTER_TRIGGER_ADAPTER_RESET);
5627         }
5628         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5629             __func__));
5630         return r;
5631 }