2 * Copyright (c) 2000-2011 LSI Corporation.
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
9 * mpi2_cnfg.h Version: 02.00.22
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
100 * Added expander reduced functionality data to SAS
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
143 * 05-25-11 02.00.20 Cleaned up a few comments.
144 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
145 * for PCIe link as obsolete.
146 * Added SpinupFlags field containing a Disable Spin-up
147 * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
148 * SAS IO Unit Page 4.
149 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
150 * Added UEFIVersion field to BIOS Page 1 and defined new
152 * --------------------------------------------------------------------------
158 /*****************************************************************************
159 * Configuration Page Header and defines
160 *****************************************************************************/
162 /* Config Page Header */
163 typedef struct _MPI2_CONFIG_PAGE_HEADER
165 U8 PageVersion; /* 0x00 */
166 U8 PageLength; /* 0x01 */
167 U8 PageNumber; /* 0x02 */
168 U8 PageType; /* 0x03 */
169 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
170 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
172 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
174 MPI2_CONFIG_PAGE_HEADER Struct;
178 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
179 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
181 /* Extended Config Page Header */
182 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
184 U8 PageVersion; /* 0x00 */
185 U8 Reserved1; /* 0x01 */
186 U8 PageNumber; /* 0x02 */
187 U8 PageType; /* 0x03 */
188 U16 ExtPageLength; /* 0x04 */
189 U8 ExtPageType; /* 0x06 */
190 U8 Reserved2; /* 0x07 */
191 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
192 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
193 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
195 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
197 MPI2_CONFIG_PAGE_HEADER Struct;
198 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
202 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
203 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
206 /* PageType field values */
207 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
208 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
209 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
210 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
212 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
213 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
214 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
215 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
216 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
217 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
218 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
219 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
221 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
224 /* ExtPageType field values */
225 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
226 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
227 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
228 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
229 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
230 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
231 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
232 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
233 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
234 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
235 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
238 /*****************************************************************************
239 * PageAddress defines
240 *****************************************************************************/
242 /* RAID Volume PageAddress format */
243 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
244 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
245 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
247 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
250 /* RAID Physical Disk PageAddress format */
251 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
252 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
253 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
254 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
256 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
257 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
260 /* SAS Expander PageAddress format */
261 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
262 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
263 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
264 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
266 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
267 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
268 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
271 /* SAS Device PageAddress format */
272 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
273 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
274 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
276 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
279 /* SAS PHY PageAddress format */
280 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
281 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
282 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
284 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
285 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
288 /* SAS Port PageAddress format */
289 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
290 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
291 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
293 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
296 /* SAS Enclosure PageAddress format */
297 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
298 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
299 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
301 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
304 /* RAID Configuration PageAddress format */
305 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
306 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
307 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
308 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
310 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
313 /* Driver Persistent Mapping PageAddress format */
314 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
315 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
317 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
318 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
319 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
322 /* Ethernet PageAddress format */
323 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
324 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
326 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
330 /****************************************************************************
331 * Configuration messages
332 ****************************************************************************/
334 /* Configuration Request Message */
335 typedef struct _MPI2_CONFIG_REQUEST
337 U8 Action; /* 0x00 */
338 U8 SGLFlags; /* 0x01 */
339 U8 ChainOffset; /* 0x02 */
340 U8 Function; /* 0x03 */
341 U16 ExtPageLength; /* 0x04 */
342 U8 ExtPageType; /* 0x06 */
343 U8 MsgFlags; /* 0x07 */
346 U16 Reserved1; /* 0x0A */
347 U8 Reserved2; /* 0x0C */
348 U8 ProxyVF_ID; /* 0x0D */
349 U16 Reserved4; /* 0x0E */
350 U32 Reserved3; /* 0x10 */
351 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
352 U32 PageAddress; /* 0x18 */
353 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
354 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
355 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
357 /* values for the Action field */
358 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
359 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
360 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
361 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
362 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
363 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
364 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
365 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
367 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
370 /* Config Reply Message */
371 typedef struct _MPI2_CONFIG_REPLY
373 U8 Action; /* 0x00 */
374 U8 SGLFlags; /* 0x01 */
375 U8 MsgLength; /* 0x02 */
376 U8 Function; /* 0x03 */
377 U16 ExtPageLength; /* 0x04 */
378 U8 ExtPageType; /* 0x06 */
379 U8 MsgFlags; /* 0x07 */
382 U16 Reserved1; /* 0x0A */
383 U16 Reserved2; /* 0x0C */
384 U16 IOCStatus; /* 0x0E */
385 U32 IOCLogInfo; /* 0x10 */
386 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
387 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
388 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
392 /*****************************************************************************
394 * C o n f i g u r a t i o n P a g e s
396 *****************************************************************************/
398 /****************************************************************************
399 * Manufacturing Config pages
400 ****************************************************************************/
402 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
405 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
406 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
407 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
408 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
409 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
410 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
411 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
413 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
415 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
416 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
417 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
418 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
419 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
420 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
421 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
422 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
423 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
428 /* Manufacturing Page 0 */
430 typedef struct _MPI2_CONFIG_PAGE_MAN_0
432 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
433 U8 ChipName[16]; /* 0x04 */
434 U8 ChipRevision[8]; /* 0x14 */
435 U8 BoardName[16]; /* 0x1C */
436 U8 BoardAssembly[16]; /* 0x2C */
437 U8 BoardTracerNumber[16]; /* 0x3C */
438 } MPI2_CONFIG_PAGE_MAN_0,
439 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
440 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
442 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
445 /* Manufacturing Page 1 */
447 typedef struct _MPI2_CONFIG_PAGE_MAN_1
449 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
450 U8 VPD[256]; /* 0x04 */
451 } MPI2_CONFIG_PAGE_MAN_1,
452 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
453 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
455 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
458 typedef struct _MPI2_CHIP_REVISION_ID
460 U16 DeviceID; /* 0x00 */
461 U8 PCIRevisionID; /* 0x02 */
462 U8 Reserved; /* 0x03 */
463 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
464 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
467 /* Manufacturing Page 2 */
470 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
471 * one and check Header.PageLength at runtime.
473 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
474 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
477 typedef struct _MPI2_CONFIG_PAGE_MAN_2
479 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
480 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
481 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
482 } MPI2_CONFIG_PAGE_MAN_2,
483 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
484 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
486 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
489 /* Manufacturing Page 3 */
492 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
493 * one and check Header.PageLength at runtime.
495 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
496 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
499 typedef struct _MPI2_CONFIG_PAGE_MAN_3
501 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
502 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
503 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
504 } MPI2_CONFIG_PAGE_MAN_3,
505 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
506 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
508 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
511 /* Manufacturing Page 4 */
513 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
515 U8 PowerSaveFlags; /* 0x00 */
516 U8 InternalOperationsSleepTime; /* 0x01 */
517 U8 InternalOperationsRunTime; /* 0x02 */
518 U8 HostIdleTime; /* 0x03 */
519 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
520 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
521 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
523 /* defines for the PowerSaveFlags field */
524 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
525 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
526 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
527 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
529 typedef struct _MPI2_CONFIG_PAGE_MAN_4
531 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
532 U32 Reserved1; /* 0x04 */
533 U32 Flags; /* 0x08 */
534 U8 InquirySize; /* 0x0C */
535 U8 Reserved2; /* 0x0D */
536 U16 Reserved3; /* 0x0E */
537 U8 InquiryData[56]; /* 0x10 */
538 U32 RAID0VolumeSettings; /* 0x48 */
539 U32 RAID1EVolumeSettings; /* 0x4C */
540 U32 RAID1VolumeSettings; /* 0x50 */
541 U32 RAID10VolumeSettings; /* 0x54 */
542 U32 Reserved4; /* 0x58 */
543 U32 Reserved5; /* 0x5C */
544 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
545 U8 MaxOCEDisks; /* 0x64 */
546 U8 ResyncRate; /* 0x65 */
547 U16 DataScrubDuration; /* 0x66 */
548 U8 MaxHotSpares; /* 0x68 */
549 U8 MaxPhysDisksPerVol; /* 0x69 */
550 U8 MaxPhysDisks; /* 0x6A */
551 U8 MaxVolumes; /* 0x6B */
552 } MPI2_CONFIG_PAGE_MAN_4,
553 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
554 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
556 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
558 /* Manufacturing Page 4 Flags field */
559 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
560 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
562 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
563 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
564 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
566 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
567 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
568 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
569 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
570 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
572 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
573 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
574 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
575 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
577 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
578 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
579 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
580 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
581 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
582 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
583 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
584 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
587 /* Manufacturing Page 5 */
590 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
591 * one and check the value returned for NumPhys at runtime.
593 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
594 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
597 typedef struct _MPI2_MANUFACTURING5_ENTRY
600 U64 DeviceName; /* 0x08 */
601 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
602 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
604 typedef struct _MPI2_CONFIG_PAGE_MAN_5
606 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
607 U8 NumPhys; /* 0x04 */
608 U8 Reserved1; /* 0x05 */
609 U16 Reserved2; /* 0x06 */
610 U32 Reserved3; /* 0x08 */
611 U32 Reserved4; /* 0x0C */
612 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
613 } MPI2_CONFIG_PAGE_MAN_5,
614 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
615 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
617 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
620 /* Manufacturing Page 6 */
622 typedef struct _MPI2_CONFIG_PAGE_MAN_6
624 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
625 U32 ProductSpecificInfo;/* 0x04 */
626 } MPI2_CONFIG_PAGE_MAN_6,
627 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
628 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
630 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
633 /* Manufacturing Page 7 */
635 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
637 U32 Pinout; /* 0x00 */
638 U8 Connector[16]; /* 0x04 */
639 U8 Location; /* 0x14 */
640 U8 ReceptacleID; /* 0x15 */
642 U32 Reserved2; /* 0x18 */
643 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
644 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
646 /* defines for the Pinout field */
647 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
648 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
650 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
651 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
652 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
653 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
654 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
655 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
656 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
657 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
658 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
659 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
660 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
661 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
662 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
663 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
664 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
666 /* defines for the Location field */
667 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
668 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
669 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
670 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
671 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
672 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
673 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
676 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
677 * one and check the value returned for NumPhys at runtime.
679 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
680 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
683 typedef struct _MPI2_CONFIG_PAGE_MAN_7
685 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
686 U32 Reserved1; /* 0x04 */
687 U32 Reserved2; /* 0x08 */
688 U32 Flags; /* 0x0C */
689 U8 EnclosureName[16]; /* 0x10 */
690 U8 NumPhys; /* 0x20 */
691 U8 Reserved3; /* 0x21 */
692 U16 Reserved4; /* 0x22 */
693 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
694 } MPI2_CONFIG_PAGE_MAN_7,
695 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
696 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
698 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
700 /* defines for the Flags field */
701 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
705 * Generic structure to use for product-specific manufacturing pages
706 * (currently Manufacturing Page 8 through Manufacturing Page 31).
709 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
711 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
712 U32 ProductSpecificInfo;/* 0x04 */
713 } MPI2_CONFIG_PAGE_MAN_PS,
714 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
715 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
717 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
718 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
719 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
720 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
721 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
722 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
723 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
724 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
725 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
726 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
727 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
728 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
729 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
730 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
731 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
732 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
733 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
734 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
735 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
736 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
737 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
738 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
739 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
740 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
743 /****************************************************************************
744 * IO Unit Config Pages
745 ****************************************************************************/
749 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
751 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
752 U64 UniqueValue; /* 0x04 */
753 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
754 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
755 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
756 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
758 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
763 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
765 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
766 U32 Flags; /* 0x04 */
767 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
768 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
770 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
772 /* IO Unit Page 1 Flags defines */
773 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
774 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
775 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
776 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
777 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
778 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
779 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
780 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
781 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
782 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
788 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
789 * one and check the value returned for GPIOCount at runtime.
791 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
792 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
795 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
797 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
798 U8 GPIOCount; /* 0x04 */
799 U8 Reserved1; /* 0x05 */
800 U16 Reserved2; /* 0x06 */
801 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
802 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
803 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
805 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
807 /* defines for IO Unit Page 3 GPIOVal field */
808 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
809 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
810 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
811 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
817 * Upper layer code (drivers, utilities, etc.) should leave this define set to
818 * one and check the value returned for NumDmaEngines at runtime.
820 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
821 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
824 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
825 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
826 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
827 U64 RaidAcceleratorBufferSize; /* 0x0C */
828 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
829 U8 RAControlSize; /* 0x1C */
830 U8 NumDmaEngines; /* 0x1D */
831 U8 RAMinControlSize; /* 0x1E */
832 U8 RAMaxControlSize; /* 0x1F */
833 U32 Reserved1; /* 0x20 */
834 U32 Reserved2; /* 0x24 */
835 U32 Reserved3; /* 0x28 */
836 U32 DmaEngineCapabilities
837 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
838 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
839 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
841 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
843 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
844 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
845 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
847 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
848 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
849 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
850 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
855 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
856 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
857 U16 Flags; /* 0x04 */
858 U8 RAHostControlSize; /* 0x06 */
859 U8 Reserved0; /* 0x07 */
860 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
861 U32 Reserved1; /* 0x10 */
862 U32 Reserved2; /* 0x14 */
863 U32 Reserved3; /* 0x18 */
864 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
865 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
867 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
869 /* defines for IO Unit Page 6 Flags field */
870 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
875 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
876 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
877 U16 Reserved1; /* 0x04 */
878 U8 PCIeWidth; /* 0x06 */
879 U8 PCIeSpeed; /* 0x07 */
880 U32 ProcessorState; /* 0x08 */
881 U32 PowerManagementCapabilities; /* 0x0C */
882 U16 IOCTemperature; /* 0x10 */
883 U8 IOCTemperatureUnits; /* 0x12 */
884 U8 IOCSpeed; /* 0x13 */
885 U16 BoardTemperature; /* 0x14 */
886 U8 BoardTemperatureUnits; /* 0x16 */
887 U8 Reserved3; /* 0x17 */
888 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
889 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
891 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
893 /* defines for IO Unit Page 7 PCIeWidth field */
894 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
895 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
896 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
897 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
899 /* defines for IO Unit Page 7 PCIeSpeed field */
900 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
901 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
902 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
904 /* defines for IO Unit Page 7 ProcessorState field */
905 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
906 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
908 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
909 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
910 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
912 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
913 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
914 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
915 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
916 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
917 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
919 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
920 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
921 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
922 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
924 /* defines for IO Unit Page 7 IOCSpeed field */
925 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
926 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
927 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
928 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
930 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
931 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
932 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
933 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
937 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
939 typedef struct _MPI2_IOUNIT8_SENSOR {
940 U16 Flags; /* 0x00 */
941 U16 Reserved1; /* 0x02 */
943 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
944 U32 Reserved2; /* 0x0C */
945 U32 Reserved3; /* 0x10 */
946 U32 Reserved4; /* 0x14 */
947 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
948 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
950 /* defines for IO Unit Page 8 Sensor Flags field */
951 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
952 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
953 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
954 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
957 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
958 * one and check the value returned for NumSensors at runtime.
960 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
961 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
964 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
965 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
966 U32 Reserved1; /* 0x04 */
967 U32 Reserved2; /* 0x08 */
968 U8 NumSensors; /* 0x0C */
969 U8 PollingInterval; /* 0x0D */
970 U16 Reserved3; /* 0x0E */
972 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
973 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
974 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
976 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
981 typedef struct _MPI2_IOUNIT9_SENSOR {
982 U16 CurrentTemperature; /* 0x00 */
983 U16 Reserved1; /* 0x02 */
985 U8 Reserved2; /* 0x05 */
986 U16 Reserved3; /* 0x06 */
987 U32 Reserved4; /* 0x08 */
988 U32 Reserved5; /* 0x0C */
989 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
990 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
992 /* defines for IO Unit Page 9 Sensor Flags field */
993 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
996 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
997 * one and check the value returned for NumSensors at runtime.
999 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1000 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1003 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1004 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1005 U32 Reserved1; /* 0x04 */
1006 U32 Reserved2; /* 0x08 */
1007 U8 NumSensors; /* 0x0C */
1008 U8 Reserved4; /* 0x0D */
1009 U16 Reserved3; /* 0x0E */
1011 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1012 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1013 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1015 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1018 /* IO Unit Page 10 */
1020 typedef struct _MPI2_IOUNIT10_FUNCTION {
1021 U8 CreditPercent; /* 0x00 */
1022 U8 Reserved1; /* 0x01 */
1023 U16 Reserved2; /* 0x02 */
1024 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1025 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1028 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1029 * one and check the value returned for NumFunctions at runtime.
1031 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1032 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1035 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1036 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1037 U8 NumFunctions; /* 0x04 */
1038 U8 Reserved1; /* 0x05 */
1039 U16 Reserved2; /* 0x06 */
1040 U32 Reserved3; /* 0x08 */
1041 U32 Reserved4; /* 0x0C */
1042 MPI2_IOUNIT10_FUNCTION
1043 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1044 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1045 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1047 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1051 /****************************************************************************
1053 ****************************************************************************/
1057 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1059 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1060 U32 Reserved1; /* 0x04 */
1061 U32 Reserved2; /* 0x08 */
1062 U16 VendorID; /* 0x0C */
1063 U16 DeviceID; /* 0x0E */
1064 U8 RevisionID; /* 0x10 */
1065 U8 Reserved3; /* 0x11 */
1066 U16 Reserved4; /* 0x12 */
1067 U32 ClassCode; /* 0x14 */
1068 U16 SubsystemVendorID; /* 0x18 */
1069 U16 SubsystemID; /* 0x1A */
1070 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1071 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1073 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1078 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1080 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1081 U32 Flags; /* 0x04 */
1082 U32 CoalescingTimeout; /* 0x08 */
1083 U8 CoalescingDepth; /* 0x0C */
1084 U8 PCISlotNum; /* 0x0D */
1085 U8 PCIBusNum; /* 0x0E */
1086 U8 PCIDomainSegment; /* 0x0F */
1087 U32 Reserved1; /* 0x10 */
1088 U32 Reserved2; /* 0x14 */
1089 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1090 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1092 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1094 /* defines for IOC Page 1 Flags field */
1095 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1097 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1098 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1099 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1103 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1105 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1106 U32 CapabilitiesFlags; /* 0x04 */
1107 U8 MaxDrivesRAID0; /* 0x08 */
1108 U8 MaxDrivesRAID1; /* 0x09 */
1109 U8 MaxDrivesRAID1E; /* 0x0A */
1110 U8 MaxDrivesRAID10; /* 0x0B */
1111 U8 MinDrivesRAID0; /* 0x0C */
1112 U8 MinDrivesRAID1; /* 0x0D */
1113 U8 MinDrivesRAID1E; /* 0x0E */
1114 U8 MinDrivesRAID10; /* 0x0F */
1115 U32 Reserved1; /* 0x10 */
1116 U8 MaxGlobalHotSpares; /* 0x14 */
1117 U8 MaxPhysDisks; /* 0x15 */
1118 U8 MaxVolumes; /* 0x16 */
1119 U8 MaxConfigs; /* 0x17 */
1120 U8 MaxOCEDisks; /* 0x18 */
1121 U8 Reserved2; /* 0x19 */
1122 U16 Reserved3; /* 0x1A */
1123 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1124 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1125 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1126 U32 Reserved4; /* 0x28 */
1127 U32 Reserved5; /* 0x2C */
1128 U16 DefaultMetadataSize; /* 0x30 */
1129 U16 Reserved6; /* 0x32 */
1130 U16 MaxBadBlockTableEntries; /* 0x34 */
1131 U16 Reserved7; /* 0x36 */
1132 U32 IRNvsramVersion; /* 0x38 */
1133 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1134 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1136 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1138 /* defines for IOC Page 6 CapabilitiesFlags */
1139 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1140 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1141 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1142 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1143 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1144 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1149 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1151 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1153 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1154 U32 Reserved1; /* 0x04 */
1155 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1156 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1157 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1158 U32 Reserved3; /* 0x1C */
1159 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1160 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1162 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1167 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1169 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1170 U8 NumDevsPerEnclosure; /* 0x04 */
1171 U8 Reserved1; /* 0x05 */
1172 U16 Reserved2; /* 0x06 */
1173 U16 MaxPersistentEntries; /* 0x08 */
1174 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1175 U16 Flags; /* 0x0C */
1176 U16 Reserved3; /* 0x0E */
1177 U16 IRVolumeMappingFlags; /* 0x10 */
1178 U16 Reserved4; /* 0x12 */
1179 U32 Reserved5; /* 0x14 */
1180 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1181 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1183 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1185 /* defines for IOC Page 8 Flags field */
1186 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1187 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1189 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1190 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1191 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1193 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1194 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1196 /* defines for IOC Page 8 IRVolumeMappingFlags */
1197 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1198 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1199 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1202 /****************************************************************************
1204 ****************************************************************************/
1208 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1210 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1211 U32 BiosOptions; /* 0x04 */
1212 U32 IOCSettings; /* 0x08 */
1213 U32 Reserved1; /* 0x0C */
1214 U32 DeviceSettings; /* 0x10 */
1215 U16 NumberOfDevices; /* 0x14 */
1216 U16 UEFIVersion; /* 0x16 */
1217 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1218 U16 IOTimeoutSequential; /* 0x1A */
1219 U16 IOTimeoutOther; /* 0x1C */
1220 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1221 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1222 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1224 #define MPI2_BIOSPAGE1_PAGEVERSION (0x05)
1226 /* values for BIOS Page 1 BiosOptions field */
1227 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1228 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1229 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1230 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1232 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1234 /* values for BIOS Page 1 IOCSettings field */
1235 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1236 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1237 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1239 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1240 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1241 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1242 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1244 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1245 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1246 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1247 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1248 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1250 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1252 /* values for BIOS Page 1 DeviceSettings field */
1253 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1254 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1255 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1256 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1257 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1259 /* defines for BIOS Page 1 UEFIVersion field */
1260 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1261 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1262 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1263 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1269 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1271 U32 Reserved1; /* 0x00 */
1272 U32 Reserved2; /* 0x04 */
1273 U32 Reserved3; /* 0x08 */
1274 U32 Reserved4; /* 0x0C */
1275 U32 Reserved5; /* 0x10 */
1276 U32 Reserved6; /* 0x14 */
1277 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1278 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1279 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1281 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1283 U64 SASAddress; /* 0x00 */
1284 U8 LUN[8]; /* 0x08 */
1285 U32 Reserved1; /* 0x10 */
1286 U32 Reserved2; /* 0x14 */
1287 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1288 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1290 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1292 U64 EnclosureLogicalID; /* 0x00 */
1293 U32 Reserved1; /* 0x08 */
1294 U32 Reserved2; /* 0x0C */
1295 U16 SlotNumber; /* 0x10 */
1296 U16 Reserved3; /* 0x12 */
1297 U32 Reserved4; /* 0x14 */
1298 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1299 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1300 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1302 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1304 U64 DeviceName; /* 0x00 */
1305 U8 LUN[8]; /* 0x08 */
1306 U32 Reserved1; /* 0x10 */
1307 U32 Reserved2; /* 0x14 */
1308 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1309 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1311 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1313 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1314 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1315 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1316 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1317 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1318 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1320 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1322 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1323 U32 Reserved1; /* 0x04 */
1324 U32 Reserved2; /* 0x08 */
1325 U32 Reserved3; /* 0x0C */
1326 U32 Reserved4; /* 0x10 */
1327 U32 Reserved5; /* 0x14 */
1328 U32 Reserved6; /* 0x18 */
1329 U8 ReqBootDeviceForm; /* 0x1C */
1330 U8 Reserved7; /* 0x1D */
1331 U16 Reserved8; /* 0x1E */
1332 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1333 U8 ReqAltBootDeviceForm; /* 0x38 */
1334 U8 Reserved9; /* 0x39 */
1335 U16 Reserved10; /* 0x3A */
1336 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1337 U8 CurrentBootDeviceForm; /* 0x58 */
1338 U8 Reserved11; /* 0x59 */
1339 U16 Reserved12; /* 0x5A */
1340 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1341 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1342 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1344 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1346 /* values for BIOS Page 2 BootDeviceForm fields */
1347 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1348 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1349 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1350 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1351 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1356 typedef struct _MPI2_ADAPTER_INFO
1358 U8 PciBusNumber; /* 0x00 */
1359 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1360 U16 AdapterFlags; /* 0x02 */
1361 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1362 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1364 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1365 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1367 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1369 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1370 U32 GlobalFlags; /* 0x04 */
1371 U32 BiosVersion; /* 0x08 */
1372 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1373 U32 Reserved1; /* 0x1C */
1374 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1375 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1377 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1379 /* values for BIOS Page 3 GlobalFlags */
1380 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1381 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1382 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1384 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1385 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1386 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1387 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1393 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1394 * one and check the value returned for NumPhys at runtime.
1396 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1397 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1400 typedef struct _MPI2_BIOS4_ENTRY
1402 U64 ReassignmentWWID; /* 0x00 */
1403 U64 ReassignmentDeviceName; /* 0x08 */
1404 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1405 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1407 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1409 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1410 U8 NumPhys; /* 0x04 */
1411 U8 Reserved1; /* 0x05 */
1412 U16 Reserved2; /* 0x06 */
1413 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1414 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1415 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1417 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1420 /****************************************************************************
1421 * RAID Volume Config Pages
1422 ****************************************************************************/
1424 /* RAID Volume Page 0 */
1426 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1428 U8 RAIDSetNum; /* 0x00 */
1429 U8 PhysDiskMap; /* 0x01 */
1430 U8 PhysDiskNum; /* 0x02 */
1431 U8 Reserved; /* 0x03 */
1432 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1433 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1435 /* defines for the PhysDiskMap field */
1436 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1437 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1439 typedef struct _MPI2_RAIDVOL0_SETTINGS
1441 U16 Settings; /* 0x00 */
1442 U8 HotSparePool; /* 0x01 */
1443 U8 Reserved; /* 0x02 */
1444 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1445 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1447 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1448 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1449 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1450 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1451 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1452 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1453 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1454 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1455 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1457 /* RAID Volume Page 0 VolumeSettings defines */
1458 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1459 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1461 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1462 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1463 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1464 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1467 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1468 * one and check the value returned for NumPhysDisks at runtime.
1470 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1471 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1474 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1476 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1477 U16 DevHandle; /* 0x04 */
1478 U8 VolumeState; /* 0x06 */
1479 U8 VolumeType; /* 0x07 */
1480 U32 VolumeStatusFlags; /* 0x08 */
1481 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1482 U64 MaxLBA; /* 0x10 */
1483 U32 StripeSize; /* 0x18 */
1484 U16 BlockSize; /* 0x1C */
1485 U16 Reserved1; /* 0x1E */
1486 U8 SupportedPhysDisks; /* 0x20 */
1487 U8 ResyncRate; /* 0x21 */
1488 U16 DataScrubDuration; /* 0x22 */
1489 U8 NumPhysDisks; /* 0x24 */
1490 U8 Reserved2; /* 0x25 */
1491 U8 Reserved3; /* 0x26 */
1492 U8 InactiveStatus; /* 0x27 */
1493 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1494 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1495 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1497 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1499 /* values for RAID VolumeState */
1500 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1501 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1502 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1503 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1504 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1505 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1507 /* values for RAID VolumeType */
1508 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1509 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1510 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1511 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1512 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1514 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1515 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1516 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1517 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1518 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1519 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1520 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1521 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1522 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1523 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1524 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1525 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1526 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1527 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1528 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1529 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1530 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1531 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1532 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1533 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1535 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1536 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1537 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1538 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1539 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1541 /* values for RAID Volume Page 0 InactiveStatus field */
1542 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1543 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1544 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1545 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1546 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1547 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1548 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1551 /* RAID Volume Page 1 */
1553 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1555 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1556 U16 DevHandle; /* 0x04 */
1557 U16 Reserved0; /* 0x06 */
1558 U8 GUID[24]; /* 0x08 */
1559 U8 Name[16]; /* 0x20 */
1560 U64 WWID; /* 0x30 */
1561 U32 Reserved1; /* 0x38 */
1562 U32 Reserved2; /* 0x3C */
1563 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1564 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1566 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1569 /****************************************************************************
1570 * RAID Physical Disk Config Pages
1571 ****************************************************************************/
1573 /* RAID Physical Disk Page 0 */
1575 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1577 U16 Reserved1; /* 0x00 */
1578 U8 HotSparePool; /* 0x02 */
1579 U8 Reserved2; /* 0x03 */
1580 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1581 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1583 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1585 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1587 U8 VendorID[8]; /* 0x00 */
1588 U8 ProductID[16]; /* 0x08 */
1589 U8 ProductRevLevel[4]; /* 0x18 */
1590 U8 SerialNum[32]; /* 0x1C */
1591 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1592 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1593 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1595 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1597 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1598 U16 DevHandle; /* 0x04 */
1599 U8 Reserved1; /* 0x06 */
1600 U8 PhysDiskNum; /* 0x07 */
1601 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1602 U32 Reserved2; /* 0x0C */
1603 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1604 U32 Reserved3; /* 0x4C */
1605 U8 PhysDiskState; /* 0x50 */
1606 U8 OfflineReason; /* 0x51 */
1607 U8 IncompatibleReason; /* 0x52 */
1608 U8 PhysDiskAttributes; /* 0x53 */
1609 U32 PhysDiskStatusFlags; /* 0x54 */
1610 U64 DeviceMaxLBA; /* 0x58 */
1611 U64 HostMaxLBA; /* 0x60 */
1612 U64 CoercedMaxLBA; /* 0x68 */
1613 U16 BlockSize; /* 0x70 */
1614 U16 Reserved5; /* 0x72 */
1615 U32 Reserved6; /* 0x74 */
1616 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1617 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1618 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1620 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1622 /* PhysDiskState defines */
1623 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1624 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1625 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1626 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1627 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1628 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1629 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1630 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1632 /* OfflineReason defines */
1633 #define MPI2_PHYSDISK0_ONLINE (0x00)
1634 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1635 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1636 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1637 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1638 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1639 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1641 /* IncompatibleReason defines */
1642 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1643 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1644 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1645 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1646 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1647 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1648 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1649 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1651 /* PhysDiskAttributes defines */
1652 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1653 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1654 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1656 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1657 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1658 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1660 /* PhysDiskStatusFlags defines */
1661 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1662 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1663 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1664 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1665 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1666 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1667 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1668 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1671 /* RAID Physical Disk Page 1 */
1674 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1675 * one and check the value returned for NumPhysDiskPaths at runtime.
1677 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1678 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1681 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1683 U16 DevHandle; /* 0x00 */
1684 U16 Reserved1; /* 0x02 */
1685 U64 WWID; /* 0x04 */
1686 U64 OwnerWWID; /* 0x0C */
1687 U8 OwnerIdentifier; /* 0x14 */
1688 U8 Reserved2; /* 0x15 */
1689 U16 Flags; /* 0x16 */
1690 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1691 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1693 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1694 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1695 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1696 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1698 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1700 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1701 U8 NumPhysDiskPaths; /* 0x04 */
1702 U8 PhysDiskNum; /* 0x05 */
1703 U16 Reserved1; /* 0x06 */
1704 U32 Reserved2; /* 0x08 */
1705 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1706 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1707 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1708 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1710 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1713 /****************************************************************************
1714 * values for fields used by several types of SAS Config Pages
1715 ****************************************************************************/
1717 /* values for NegotiatedLinkRates fields */
1718 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1719 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1720 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1721 /* link rates used for Negotiated Physical and Logical Link Rate */
1722 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1723 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1724 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1725 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1726 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1727 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1728 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1729 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1730 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1731 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1734 /* values for AttachedPhyInfo fields */
1735 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1736 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1737 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1739 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1740 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1741 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1742 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1743 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1744 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1745 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1746 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1747 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1748 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1751 /* values for PhyInfo fields */
1752 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1754 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1755 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1756 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1757 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1758 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1760 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1761 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1762 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1763 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1764 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1765 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1767 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1768 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1769 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1770 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1771 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1772 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1773 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1774 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1775 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1776 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1778 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1779 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1780 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1781 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1783 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1784 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1786 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1787 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1788 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1789 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1792 /* values for SAS ProgrammedLinkRate fields */
1793 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1794 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1795 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1796 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1797 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1798 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1799 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1800 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1801 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1802 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1805 /* values for SAS HwLinkRate fields */
1806 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1807 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1808 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1809 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1810 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1811 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1812 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1813 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1817 /****************************************************************************
1818 * SAS IO Unit Config Pages
1819 ****************************************************************************/
1821 /* SAS IO Unit Page 0 */
1823 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1826 U8 PortFlags; /* 0x01 */
1827 U8 PhyFlags; /* 0x02 */
1828 U8 NegotiatedLinkRate; /* 0x03 */
1829 U32 ControllerPhyDeviceInfo;/* 0x04 */
1830 U16 AttachedDevHandle; /* 0x08 */
1831 U16 ControllerDevHandle; /* 0x0A */
1832 U32 DiscoveryStatus; /* 0x0C */
1833 U32 Reserved; /* 0x10 */
1834 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1835 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1838 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1839 * one and check the value returned for NumPhys at runtime.
1841 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1842 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1845 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1847 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1848 U32 Reserved1; /* 0x08 */
1849 U8 NumPhys; /* 0x0C */
1850 U8 Reserved2; /* 0x0D */
1851 U16 Reserved3; /* 0x0E */
1852 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1853 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1854 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1855 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1857 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1859 /* values for SAS IO Unit Page 0 PortFlags */
1860 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1861 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1863 /* values for SAS IO Unit Page 0 PhyFlags */
1864 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1865 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1867 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1869 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1871 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1872 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1873 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1874 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1875 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1876 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1877 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1878 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1879 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1880 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1881 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1882 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1883 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1884 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1885 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1886 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1887 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1888 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1889 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1890 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1891 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1894 /* SAS IO Unit Page 1 */
1896 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1899 U8 PortFlags; /* 0x01 */
1900 U8 PhyFlags; /* 0x02 */
1901 U8 MaxMinLinkRate; /* 0x03 */
1902 U32 ControllerPhyDeviceInfo; /* 0x04 */
1903 U16 MaxTargetPortConnectTime; /* 0x08 */
1904 U16 Reserved1; /* 0x0A */
1905 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1906 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1909 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1910 * one and check the value returned for NumPhys at runtime.
1912 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1913 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1916 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1918 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1919 U16 ControlFlags; /* 0x08 */
1920 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1921 U16 AdditionalControlFlags; /* 0x0C */
1922 U16 SASWideMaxQueueDepth; /* 0x0E */
1923 U8 NumPhys; /* 0x10 */
1924 U8 SATAMaxQDepth; /* 0x11 */
1925 U8 ReportDeviceMissingDelay; /* 0x12 */
1926 U8 IODeviceMissingDelay; /* 0x13 */
1927 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1928 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1929 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1930 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1932 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1934 /* values for SAS IO Unit Page 1 ControlFlags */
1935 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1936 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1937 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1938 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1940 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1941 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1942 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1943 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1944 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1946 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1947 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1948 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1949 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1950 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1951 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1952 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1953 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1955 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1956 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1957 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1958 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1959 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1960 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1961 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1962 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1963 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1965 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1966 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1967 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1969 /* values for SAS IO Unit Page 1 PortFlags */
1970 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1972 /* values for SAS IO Unit Page 1 PhyFlags */
1973 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1974 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1976 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1977 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1978 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1979 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1980 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1981 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1982 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1983 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1984 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1986 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1989 /* SAS IO Unit Page 4 */
1991 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1993 U8 MaxTargetSpinup; /* 0x00 */
1994 U8 SpinupDelay; /* 0x01 */
1995 U8 SpinupFlags; /* 0x02 */
1996 U8 Reserved1; /* 0x03 */
1997 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1998 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2000 /* defines for SAS IO Unit Page 4 SpinupFlags */
2001 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2004 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2005 * one and check the value returned for NumPhys at runtime.
2007 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2008 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2011 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2013 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2014 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2015 U32 Reserved1; /* 0x18 */
2016 U32 Reserved2; /* 0x1C */
2017 U32 Reserved3; /* 0x20 */
2018 U8 BootDeviceWaitTime; /* 0x24 */
2019 U8 Reserved4; /* 0x25 */
2020 U16 Reserved5; /* 0x26 */
2021 U8 NumPhys; /* 0x28 */
2022 U8 PEInitialSpinupDelay; /* 0x29 */
2023 U8 PEReplyDelay; /* 0x2A */
2024 U8 Flags; /* 0x2B */
2025 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2026 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2027 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2028 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2030 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2032 /* defines for Flags field */
2033 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2035 /* defines for PHY field */
2036 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2039 /* SAS IO Unit Page 5 */
2041 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2042 U8 ControlFlags; /* 0x00 */
2043 U8 PortWidthModGroup; /* 0x01 */
2044 U16 InactivityTimerExponent; /* 0x02 */
2045 U8 SATAPartialTimeout; /* 0x04 */
2046 U8 Reserved2; /* 0x05 */
2047 U8 SATASlumberTimeout; /* 0x06 */
2048 U8 Reserved3; /* 0x07 */
2049 U8 SASPartialTimeout; /* 0x08 */
2050 U8 Reserved4; /* 0x09 */
2051 U8 SASSlumberTimeout; /* 0x0A */
2052 U8 Reserved5; /* 0x0B */
2053 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2054 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2055 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2057 /* defines for ControlFlags field */
2058 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2059 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2060 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2061 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2063 /* defines for PortWidthModeGroup field */
2064 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2066 /* defines for InactivityTimerExponent field */
2067 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2068 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2069 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2070 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2071 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2072 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2073 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2074 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2076 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2077 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2078 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2079 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2080 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2081 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2082 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2083 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2086 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2087 * one and check the value returned for NumPhys at runtime.
2089 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2090 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2093 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2094 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2095 U8 NumPhys; /* 0x08 */
2096 U8 Reserved1; /* 0x09 */
2097 U16 Reserved2; /* 0x0A */
2098 U32 Reserved3; /* 0x0C */
2099 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2100 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2101 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2102 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2103 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2105 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2108 /* SAS IO Unit Page 6 */
2110 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2111 U8 CurrentStatus; /* 0x00 */
2112 U8 CurrentModulation; /* 0x01 */
2113 U8 CurrentUtilization; /* 0x02 */
2114 U8 Reserved1; /* 0x03 */
2115 U32 Reserved2; /* 0x04 */
2116 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2117 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2118 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2119 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2121 /* defines for CurrentStatus field */
2122 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2123 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2124 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2125 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2126 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2127 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2128 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2129 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2131 /* defines for CurrentModulation field */
2132 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2133 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2134 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2135 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2138 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2139 * one and check the value returned for NumGroups at runtime.
2141 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2142 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2145 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2146 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2147 U32 Reserved1; /* 0x08 */
2148 U32 Reserved2; /* 0x0C */
2149 U8 NumGroups; /* 0x10 */
2150 U8 Reserved3; /* 0x11 */
2151 U16 Reserved4; /* 0x12 */
2152 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2153 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2154 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2155 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2156 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2158 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2161 /* SAS IO Unit Page 7 */
2163 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2164 U8 Flags; /* 0x00 */
2165 U8 Reserved1; /* 0x01 */
2166 U16 Reserved2; /* 0x02 */
2167 U8 Threshold75Pct; /* 0x04 */
2168 U8 Threshold50Pct; /* 0x05 */
2169 U8 Threshold25Pct; /* 0x06 */
2170 U8 Reserved3; /* 0x07 */
2171 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2172 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2173 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2174 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2176 /* defines for Flags field */
2177 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2181 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2182 * one and check the value returned for NumGroups at runtime.
2184 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2185 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2188 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2189 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2190 U8 SamplingInterval; /* 0x08 */
2191 U8 WindowLength; /* 0x09 */
2192 U16 Reserved1; /* 0x0A */
2193 U32 Reserved2; /* 0x0C */
2194 U32 Reserved3; /* 0x10 */
2195 U8 NumGroups; /* 0x14 */
2196 U8 Reserved4; /* 0x15 */
2197 U16 Reserved5; /* 0x16 */
2198 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2199 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2200 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2201 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2202 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2204 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2207 /* SAS IO Unit Page 8 */
2209 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2210 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2211 U32 Reserved1; /* 0x08 */
2212 U32 PowerManagementCapabilities;/* 0x0C */
2213 U32 Reserved2; /* 0x10 */
2214 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2215 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2216 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2218 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2220 /* defines for PowerManagementCapabilities field */
2221 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2222 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2223 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2224 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2225 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2226 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2227 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2228 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2229 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2230 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2234 /* SAS IO Unit Page 16 */
2236 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2237 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2238 U64 TimeStamp; /* 0x08 */
2239 U32 Reserved1; /* 0x10 */
2240 U32 Reserved2; /* 0x14 */
2241 U32 FastPathPendedRequests; /* 0x18 */
2242 U32 FastPathUnPendedRequests; /* 0x1C */
2243 U32 FastPathHostRequestStarts; /* 0x20 */
2244 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2245 U32 FastPathHostCompletions; /* 0x28 */
2246 U32 FastPathFirmwareCompletions; /* 0x2C */
2247 U32 NonFastPathRequestStarts; /* 0x30 */
2248 U32 NonFastPathHostCompletions; /* 0x30 */
2249 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2250 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2251 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2253 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2256 /****************************************************************************
2257 * SAS Expander Config Pages
2258 ****************************************************************************/
2260 /* SAS Expander Page 0 */
2262 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2264 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2265 U8 PhysicalPort; /* 0x08 */
2266 U8 ReportGenLength; /* 0x09 */
2267 U16 EnclosureHandle; /* 0x0A */
2268 U64 SASAddress; /* 0x0C */
2269 U32 DiscoveryStatus; /* 0x14 */
2270 U16 DevHandle; /* 0x18 */
2271 U16 ParentDevHandle; /* 0x1A */
2272 U16 ExpanderChangeCount; /* 0x1C */
2273 U16 ExpanderRouteIndexes; /* 0x1E */
2274 U8 NumPhys; /* 0x20 */
2275 U8 SASLevel; /* 0x21 */
2276 U16 Flags; /* 0x22 */
2277 U16 STPBusInactivityTimeLimit; /* 0x24 */
2278 U16 STPMaxConnectTimeLimit; /* 0x26 */
2279 U16 STP_SMP_NexusLossTime; /* 0x28 */
2280 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2281 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2282 U16 ZoneLockInactivityLimit; /* 0x34 */
2283 U16 Reserved1; /* 0x36 */
2284 U8 TimeToReducedFunc; /* 0x38 */
2285 U8 InitialTimeToReducedFunc; /* 0x39 */
2286 U8 MaxReducedFuncTime; /* 0x3A */
2287 U8 Reserved2; /* 0x3B */
2288 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2289 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2291 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2293 /* values for SAS Expander Page 0 DiscoveryStatus field */
2294 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2295 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2296 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2297 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2298 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2299 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2300 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2301 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2302 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2303 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2304 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2305 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2306 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2307 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2308 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2309 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2310 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2311 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2312 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2313 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2315 /* values for SAS Expander Page 0 Flags field */
2316 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2317 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2318 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2319 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2320 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2321 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2322 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2323 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2324 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2325 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2326 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2329 /* SAS Expander Page 1 */
2331 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2333 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2334 U8 PhysicalPort; /* 0x08 */
2335 U8 Reserved1; /* 0x09 */
2336 U16 Reserved2; /* 0x0A */
2337 U8 NumPhys; /* 0x0C */
2339 U16 NumTableEntriesProgrammed; /* 0x0E */
2340 U8 ProgrammedLinkRate; /* 0x10 */
2341 U8 HwLinkRate; /* 0x11 */
2342 U16 AttachedDevHandle; /* 0x12 */
2343 U32 PhyInfo; /* 0x14 */
2344 U32 AttachedDeviceInfo; /* 0x18 */
2345 U16 ExpanderDevHandle; /* 0x1C */
2346 U8 ChangeCount; /* 0x1E */
2347 U8 NegotiatedLinkRate; /* 0x1F */
2348 U8 PhyIdentifier; /* 0x20 */
2349 U8 AttachedPhyIdentifier; /* 0x21 */
2350 U8 Reserved3; /* 0x22 */
2351 U8 DiscoveryInfo; /* 0x23 */
2352 U32 AttachedPhyInfo; /* 0x24 */
2353 U8 ZoneGroup; /* 0x28 */
2354 U8 SelfConfigStatus; /* 0x29 */
2355 U16 Reserved4; /* 0x2A */
2356 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2357 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2359 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2361 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2363 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2365 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2367 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2369 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2371 /* values for SAS Expander Page 1 DiscoveryInfo field */
2372 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2373 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2374 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2376 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2378 /****************************************************************************
2379 * SAS Device Config Pages
2380 ****************************************************************************/
2382 /* SAS Device Page 0 */
2384 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2386 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2387 U16 Slot; /* 0x08 */
2388 U16 EnclosureHandle; /* 0x0A */
2389 U64 SASAddress; /* 0x0C */
2390 U16 ParentDevHandle; /* 0x14 */
2391 U8 PhyNum; /* 0x16 */
2392 U8 AccessStatus; /* 0x17 */
2393 U16 DevHandle; /* 0x18 */
2394 U8 AttachedPhyIdentifier; /* 0x1A */
2395 U8 ZoneGroup; /* 0x1B */
2396 U32 DeviceInfo; /* 0x1C */
2397 U16 Flags; /* 0x20 */
2398 U8 PhysicalPort; /* 0x22 */
2399 U8 MaxPortConnections; /* 0x23 */
2400 U64 DeviceName; /* 0x24 */
2401 U8 PortGroups; /* 0x2C */
2402 U8 DmaGroup; /* 0x2D */
2403 U8 ControlGroup; /* 0x2E */
2404 U8 Reserved1; /* 0x2F */
2405 U32 Reserved2; /* 0x30 */
2406 U32 Reserved3; /* 0x34 */
2407 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2408 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2410 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2412 /* values for SAS Device Page 0 AccessStatus field */
2413 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2414 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2415 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2416 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2417 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2418 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2419 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2420 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2421 /* specific values for SATA Init failures */
2422 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2423 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2424 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2425 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2426 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2427 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2428 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2429 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2430 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2431 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2432 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2434 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2436 /* values for SAS Device Page 0 Flags field */
2437 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2438 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2439 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2440 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2441 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2442 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2443 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2444 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2445 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2446 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2447 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2448 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2451 /* SAS Device Page 1 */
2453 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2455 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2456 U32 Reserved1; /* 0x08 */
2457 U64 SASAddress; /* 0x0C */
2458 U32 Reserved2; /* 0x14 */
2459 U16 DevHandle; /* 0x18 */
2460 U16 Reserved3; /* 0x1A */
2461 U8 InitialRegDeviceFIS[20];/* 0x1C */
2462 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2463 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2465 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2468 /****************************************************************************
2469 * SAS PHY Config Pages
2470 ****************************************************************************/
2472 /* SAS PHY Page 0 */
2474 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2476 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2477 U16 OwnerDevHandle; /* 0x08 */
2478 U16 Reserved1; /* 0x0A */
2479 U16 AttachedDevHandle; /* 0x0C */
2480 U8 AttachedPhyIdentifier; /* 0x0E */
2481 U8 Reserved2; /* 0x0F */
2482 U32 AttachedPhyInfo; /* 0x10 */
2483 U8 ProgrammedLinkRate; /* 0x14 */
2484 U8 HwLinkRate; /* 0x15 */
2485 U8 ChangeCount; /* 0x16 */
2486 U8 Flags; /* 0x17 */
2487 U32 PhyInfo; /* 0x18 */
2488 U8 NegotiatedLinkRate; /* 0x1C */
2489 U8 Reserved3; /* 0x1D */
2490 U16 Reserved4; /* 0x1E */
2491 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2492 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2494 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2496 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2498 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2500 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2502 /* values for SAS PHY Page 0 Flags field */
2503 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2505 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2507 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2510 /* SAS PHY Page 1 */
2512 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2514 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2515 U32 Reserved1; /* 0x08 */
2516 U32 InvalidDwordCount; /* 0x0C */
2517 U32 RunningDisparityErrorCount; /* 0x10 */
2518 U32 LossDwordSynchCount; /* 0x14 */
2519 U32 PhyResetProblemCount; /* 0x18 */
2520 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2521 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2523 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2526 /* SAS PHY Page 2 */
2528 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2529 U8 PhyEventCode; /* 0x00 */
2530 U8 Reserved1; /* 0x01 */
2531 U16 Reserved2; /* 0x02 */
2532 U32 PhyEventInfo; /* 0x04 */
2533 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2534 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2536 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2540 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2541 * one and check the value returned for NumPhyEvents at runtime.
2543 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2544 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2547 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2548 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2549 U32 Reserved1; /* 0x08 */
2550 U8 NumPhyEvents; /* 0x0C */
2551 U8 Reserved2; /* 0x0D */
2552 U16 Reserved3; /* 0x0E */
2553 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2555 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2556 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2558 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2561 /* SAS PHY Page 3 */
2563 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2564 U8 PhyEventCode; /* 0x00 */
2565 U8 Reserved1; /* 0x01 */
2566 U16 Reserved2; /* 0x02 */
2567 U8 CounterType; /* 0x04 */
2568 U8 ThresholdWindow; /* 0x05 */
2569 U8 TimeUnits; /* 0x06 */
2570 U8 Reserved3; /* 0x07 */
2571 U32 EventThreshold; /* 0x08 */
2572 U16 ThresholdFlags; /* 0x0C */
2573 U16 Reserved4; /* 0x0E */
2574 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2575 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2577 /* values for PhyEventCode field */
2578 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2579 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2580 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2581 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2582 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2583 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2584 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2585 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2586 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2587 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2588 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2589 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2590 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2591 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2592 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2593 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2594 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2595 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2596 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2597 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2598 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2599 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2600 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2601 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2602 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2603 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2604 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2605 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2606 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2607 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2608 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2609 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2610 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2611 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2612 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2613 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2614 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2616 /* values for the CounterType field */
2617 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2618 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2619 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2621 /* values for the TimeUnits field */
2622 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2623 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2624 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2625 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2627 /* values for the ThresholdFlags field */
2628 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2629 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2632 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2633 * one and check the value returned for NumPhyEvents at runtime.
2635 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2636 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2639 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2640 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2641 U32 Reserved1; /* 0x08 */
2642 U8 NumPhyEvents; /* 0x0C */
2643 U8 Reserved2; /* 0x0D */
2644 U16 Reserved3; /* 0x0E */
2645 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2646 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2647 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2648 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2650 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2653 /* SAS PHY Page 4 */
2655 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2656 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2657 U16 Reserved1; /* 0x08 */
2658 U8 Reserved2; /* 0x0A */
2659 U8 Flags; /* 0x0B */
2660 U8 InitialFrame[28]; /* 0x0C */
2661 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2662 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2664 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2666 /* values for the Flags field */
2667 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2668 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2673 /****************************************************************************
2674 * SAS Port Config Pages
2675 ****************************************************************************/
2677 /* SAS Port Page 0 */
2679 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2681 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2682 U8 PortNumber; /* 0x08 */
2683 U8 PhysicalPort; /* 0x09 */
2684 U8 PortWidth; /* 0x0A */
2685 U8 PhysicalPortWidth; /* 0x0B */
2686 U8 ZoneGroup; /* 0x0C */
2687 U8 Reserved1; /* 0x0D */
2688 U16 Reserved2; /* 0x0E */
2689 U64 SASAddress; /* 0x10 */
2690 U32 DeviceInfo; /* 0x18 */
2691 U32 Reserved3; /* 0x1C */
2692 U32 Reserved4; /* 0x20 */
2693 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2694 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2696 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2698 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2701 /****************************************************************************
2702 * SAS Enclosure Config Pages
2703 ****************************************************************************/
2705 /* SAS Enclosure Page 0 */
2707 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2709 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2710 U32 Reserved1; /* 0x08 */
2711 U64 EnclosureLogicalID; /* 0x0C */
2712 U16 Flags; /* 0x14 */
2713 U16 EnclosureHandle; /* 0x16 */
2714 U16 NumSlots; /* 0x18 */
2715 U16 StartSlot; /* 0x1A */
2716 U16 Reserved2; /* 0x1C */
2717 U16 SEPDevHandle; /* 0x1E */
2718 U32 Reserved3; /* 0x20 */
2719 U32 Reserved4; /* 0x24 */
2720 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2721 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2722 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2724 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2726 /* values for SAS Enclosure Page 0 Flags field */
2727 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2728 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2729 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2730 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2731 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2732 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2733 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2736 /****************************************************************************
2738 ****************************************************************************/
2743 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2744 * one and check the value returned for NumLogEntries at runtime.
2746 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2747 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2750 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2752 typedef struct _MPI2_LOG_0_ENTRY
2754 U64 TimeStamp; /* 0x00 */
2755 U32 Reserved1; /* 0x08 */
2756 U16 LogSequence; /* 0x0C */
2757 U16 LogEntryQualifier; /* 0x0E */
2758 U8 VP_ID; /* 0x10 */
2759 U8 VF_ID; /* 0x11 */
2760 U16 Reserved2; /* 0x12 */
2761 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2762 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2763 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2765 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2766 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2767 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2768 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2769 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2770 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2772 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2774 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2775 U32 Reserved1; /* 0x08 */
2776 U32 Reserved2; /* 0x0C */
2777 U16 NumLogEntries; /* 0x10 */
2778 U16 Reserved3; /* 0x12 */
2779 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2780 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2781 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2783 #define MPI2_LOG_0_PAGEVERSION (0x02)
2786 /****************************************************************************
2788 ****************************************************************************/
2793 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2794 * one and check the value returned for NumElements at runtime.
2796 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2797 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2800 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2802 U16 ElementFlags; /* 0x00 */
2803 U16 VolDevHandle; /* 0x02 */
2804 U8 HotSparePool; /* 0x04 */
2805 U8 PhysDiskNum; /* 0x05 */
2806 U16 PhysDiskDevHandle; /* 0x06 */
2807 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2808 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2809 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2811 /* values for the ElementFlags field */
2812 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2813 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2814 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2815 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2816 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2819 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2821 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2822 U8 NumHotSpares; /* 0x08 */
2823 U8 NumPhysDisks; /* 0x09 */
2824 U8 NumVolumes; /* 0x0A */
2825 U8 ConfigNum; /* 0x0B */
2826 U32 Flags; /* 0x0C */
2827 U8 ConfigGUID[24]; /* 0x10 */
2828 U32 Reserved1; /* 0x28 */
2829 U8 NumElements; /* 0x2C */
2830 U8 Reserved2; /* 0x2D */
2831 U16 Reserved3; /* 0x2E */
2832 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2833 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2834 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2835 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2837 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2839 /* values for RAID Configuration Page 0 Flags field */
2840 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2843 /****************************************************************************
2844 * Driver Persistent Mapping Config Pages
2845 ****************************************************************************/
2847 /* Driver Persistent Mapping Page 0 */
2849 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2851 U64 PhysicalIdentifier; /* 0x00 */
2852 U16 MappingInformation; /* 0x08 */
2853 U16 DeviceIndex; /* 0x0A */
2854 U32 PhysicalBitsMapping; /* 0x0C */
2855 U32 Reserved1; /* 0x10 */
2856 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2857 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2858 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2860 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2862 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2863 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2864 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2865 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2866 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2868 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2870 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2871 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2872 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2873 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2876 /****************************************************************************
2877 * Ethernet Config Pages
2878 ****************************************************************************/
2880 /* Ethernet Page 0 */
2882 /* IP address (union of IPv4 and IPv6) */
2883 typedef union _MPI2_ETHERNET_IP_ADDR {
2886 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2887 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2889 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2891 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2892 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2893 U8 NumInterfaces; /* 0x08 */
2894 U8 Reserved0; /* 0x09 */
2895 U16 Reserved1; /* 0x0A */
2896 U32 Status; /* 0x0C */
2897 U8 MediaState; /* 0x10 */
2898 U8 Reserved2; /* 0x11 */
2899 U16 Reserved3; /* 0x12 */
2900 U8 MacAddress[6]; /* 0x14 */
2901 U8 Reserved4; /* 0x1A */
2902 U8 Reserved5; /* 0x1B */
2903 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2904 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2905 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2906 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2907 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2908 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2910 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2911 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2912 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2914 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2916 /* values for Ethernet Page 0 Status field */
2917 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2918 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2919 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2920 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2921 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2922 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2923 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2924 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2925 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2926 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2927 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2928 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2930 /* values for Ethernet Page 0 MediaState field */
2931 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2932 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2933 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2935 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2936 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2937 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2938 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2939 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2942 /* Ethernet Page 1 */
2944 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2945 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2946 U32 Reserved0; /* 0x08 */
2947 U32 Flags; /* 0x0C */
2948 U8 MediaState; /* 0x10 */
2949 U8 Reserved1; /* 0x11 */
2950 U16 Reserved2; /* 0x12 */
2951 U8 MacAddress[6]; /* 0x14 */
2952 U8 Reserved3; /* 0x1A */
2953 U8 Reserved4; /* 0x1B */
2954 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2955 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2956 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2957 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2958 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2959 U32 Reserved5; /* 0x6C */
2960 U32 Reserved6; /* 0x70 */
2961 U32 Reserved7; /* 0x74 */
2962 U32 Reserved8; /* 0x78 */
2964 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2965 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2966 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2968 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2970 /* values for Ethernet Page 1 Flags field */
2971 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2972 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2973 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2974 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2975 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2976 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2977 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2978 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2979 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2981 /* values for Ethernet Page 1 MediaState field */
2982 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2983 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2984 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2986 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2987 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2988 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2989 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2990 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2993 /****************************************************************************
2994 * Extended Manufacturing Config Pages
2995 ****************************************************************************/
2998 * Generic structure to use for product-specific extended manufacturing pages
2999 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3003 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3004 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3005 U32 ProductSpecificInfo; /* 0x08 */
3006 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3007 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3008 Mpi2ExtManufacturingPagePS_t,
3009 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3011 /* PageVersion should be provided by product-specific code */
projects / firefly-linux-kernel-4.4.55.git / blob