drivers/scsi/isci/phy.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #include "isci.h"
  57 #include "host.h"
  58 #include "phy.h"
  59 #include "scu_event_codes.h"
  60 #include "probe_roms.h"
  61
  62 #undef C
  63 #define C(a) (#a)
  64 static const char *phy_state_name(enum sci_phy_states state)
  65 {
  66         static const char * const strings[] = PHY_STATES;
  67
  68         return strings[state];
  69 }
  70 #undef C
  71
  72 /* Maximum arbitration wait time in micro-seconds */
  73 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
  74
  75 enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
  76 {
  77         return iphy->max_negotiated_speed;
  78 }
  79
  80 static struct isci_host *phy_to_host(struct isci_phy *iphy)
  81 {
  82         struct isci_phy *table = iphy - iphy->phy_index;
  83         struct isci_host *ihost = container_of(table, typeof(*ihost), phys[0]);
  84
  85         return ihost;
  86 }
  87
  88 static struct device *sciphy_to_dev(struct isci_phy *iphy)
  89 {
  90         return &phy_to_host(iphy)->pdev->dev;
  91 }
  92
  93 static enum sci_status
  94 sci_phy_transport_layer_initialization(struct isci_phy *iphy,
  95                                        struct scu_transport_layer_registers __iomem *reg)
  96 {
  97         u32 tl_control;
  98
  99         iphy->transport_layer_registers = reg;
 100
 101         writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
 102                 &iphy->transport_layer_registers->stp_rni);
 103
 104         /*
 105          * Hardware team recommends that we enable the STP prefetch for all
 106          * transports
 107          */
 108         tl_control = readl(&iphy->transport_layer_registers->control);
 109         tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
 110         writel(tl_control, &iphy->transport_layer_registers->control);
 111
 112         return SCI_SUCCESS;
 113 }
 114
 115 static enum sci_status
 116 sci_phy_link_layer_initialization(struct isci_phy *iphy,
 117                                   struct scu_link_layer_registers __iomem *llr)
 118 {
 119         struct isci_host *ihost = iphy->owning_port->owning_controller;
 120         struct sci_phy_user_params *phy_user;
 121         struct sci_phy_oem_params *phy_oem;
 122         int phy_idx = iphy->phy_index;
 123         struct sci_phy_cap phy_cap;
 124         u32 phy_configuration;
 125         u32 parity_check = 0;
 126         u32 parity_count = 0;
 127         u32 llctl, link_rate;
 128         u32 clksm_value = 0;
 129         u32 sp_timeouts = 0;
 130
 131         phy_user = &ihost->user_parameters.phys[phy_idx];
 132         phy_oem = &ihost->oem_parameters.phys[phy_idx];
 133         iphy->link_layer_registers = llr;
 134
 135         /* Set our IDENTIFY frame data */
 136         #define SCI_END_DEVICE 0x01
 137
 138         writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
 139                SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
 140                SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
 141                SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
 142                SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
 143                &llr->transmit_identification);
 144
 145         /* Write the device SAS Address */
 146         writel(0xFEDCBA98, &llr->sas_device_name_high);
 147         writel(phy_idx, &llr->sas_device_name_low);
 148
 149         /* Write the source SAS Address */
 150         writel(phy_oem->sas_address.high, &llr->source_sas_address_high);
 151         writel(phy_oem->sas_address.low, &llr->source_sas_address_low);
 152
 153         /* Clear and Set the PHY Identifier */
 154         writel(0, &llr->identify_frame_phy_id);
 155         writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id);
 156
 157         /* Change the initial state of the phy configuration register */
 158         phy_configuration = readl(&llr->phy_configuration);
 159
 160         /* Hold OOB state machine in reset */
 161         phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 162         writel(phy_configuration, &llr->phy_configuration);
 163
 164         /* Configure the SNW capabilities */
 165         phy_cap.all = 0;
 166         phy_cap.start = 1;
 167         phy_cap.gen3_no_ssc = 1;
 168         phy_cap.gen2_no_ssc = 1;
 169         phy_cap.gen1_no_ssc = 1;
 170         if (ihost->oem_parameters.controller.do_enable_ssc) {
 171                 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
 172                 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_idx];
 173                 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
 174                 bool en_sas = false;
 175                 bool en_sata = false;
 176                 u32 sas_type = 0;
 177                 u32 sata_spread = 0x2;
 178                 u32 sas_spread = 0x2;
 179
 180                 phy_cap.gen3_ssc = 1;
 181                 phy_cap.gen2_ssc = 1;
 182                 phy_cap.gen1_ssc = 1;
 183
 184                 if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1)
 185                         en_sas = en_sata = true;
 186                 else {
 187                         sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level;
 188                         sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level;
 189
 190                         if (sata_spread)
 191                                 en_sata = true;
 192
 193                         if (sas_spread) {
 194                                 en_sas = true;
 195                                 sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type;
 196                         }
 197
 198                 }
 199
 200                 if (en_sas) {
 201                         u32 reg;
 202
 203                         reg = readl(&xcvr->afe_xcvr_control0);
 204                         reg |= (0x00100000 | (sas_type << 19));
 205                         writel(reg, &xcvr->afe_xcvr_control0);
 206
 207                         reg = readl(&xcvr->afe_tx_ssc_control);
 208                         reg |= sas_spread << 8;
 209                         writel(reg, &xcvr->afe_tx_ssc_control);
 210                 }
 211
 212                 if (en_sata) {
 213                         u32 reg;
 214
 215                         reg = readl(&xcvr->afe_tx_ssc_control);
 216                         reg |= sata_spread;
 217                         writel(reg, &xcvr->afe_tx_ssc_control);
 218
 219                         reg = readl(&llr->stp_control);
 220                         reg |= 1 << 12;
 221                         writel(reg, &llr->stp_control);
 222                 }
 223         }
 224
 225         /* The SAS specification indicates that the phy_capabilities that
 226          * are transmitted shall have an even parity.  Calculate the parity.
 227          */
 228         parity_check = phy_cap.all;
 229         while (parity_check != 0) {
 230                 if (parity_check & 0x1)
 231                         parity_count++;
 232                 parity_check >>= 1;
 233         }
 234
 235         /* If parity indicates there are an odd number of bits set, then
 236          * set the parity bit to 1 in the phy capabilities.
 237          */
 238         if ((parity_count % 2) != 0)
 239                 phy_cap.parity = 1;
 240
 241         writel(phy_cap.all, &llr->phy_capabilities);
 242
 243         /* Set the enable spinup period but disable the ability to send
 244          * notify enable spinup
 245          */
 246         writel(SCU_ENSPINUP_GEN_VAL(COUNT,
 247                         phy_user->notify_enable_spin_up_insertion_frequency),
 248                 &llr->notify_enable_spinup_control);
 249
 250         /* Write the ALIGN Insertion Ferequency for connected phy and
 251          * inpendent of connected state
 252          */
 253         clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
 254                         phy_user->in_connection_align_insertion_frequency);
 255
 256         clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
 257                         phy_user->align_insertion_frequency);
 258
 259         writel(clksm_value, &llr->clock_skew_management);
 260
 261         if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) {
 262                 writel(0x04210400, &llr->afe_lookup_table_control);
 263                 writel(0x020A7C05, &llr->sas_primitive_timeout);
 264         } else
 265                 writel(0x02108421, &llr->afe_lookup_table_control);
 266
 267         llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
 268                 (u8)ihost->user_parameters.no_outbound_task_timeout);
 269
 270         switch (phy_user->max_speed_generation) {
 271         case SCIC_SDS_PARM_GEN3_SPEED:
 272                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
 273                 break;
 274         case SCIC_SDS_PARM_GEN2_SPEED:
 275                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
 276                 break;
 277         default:
 278                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
 279                 break;
 280         }
 281         llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
 282         writel(llctl, &llr->link_layer_control);
 283
 284         sp_timeouts = readl(&llr->sas_phy_timeouts);
 285
 286         /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */
 287         sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF);
 288
 289         /* Set RATE_CHANGE timeout value to 0x3B (59us).  This ensures SCU can
 290          * lock with 3Gb drive when SCU max rate is set to 1.5Gb.
 291          */
 292         sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B);
 293
 294         writel(sp_timeouts, &llr->sas_phy_timeouts);
 295
 296         if (is_a2(ihost->pdev)) {
 297                 /* Program the max ARB time for the PHY to 700us so we
 298                  * inter-operate with the PMC expander which shuts down
 299                  * PHYs if the expander PHY generates too many breaks.
 300                  * This time value will guarantee that the initiator PHY
 301                  * will generate the break.
 302                  */
 303                 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
 304                        &llr->maximum_arbitration_wait_timer_timeout);
 305         }
 306
 307         /* Disable link layer hang detection, rely on the OS timeout for
 308          * I/O timeouts.
 309          */
 310         writel(0, &llr->link_layer_hang_detection_timeout);
 311
 312         /* We can exit the initial state to the stopped state */
 313         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 314
 315         return SCI_SUCCESS;
 316 }
 317
 318 static void phy_sata_timeout(unsigned long data)
 319 {
 320         struct sci_timer *tmr = (struct sci_timer *)data;
 321         struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
 322         struct isci_host *ihost = iphy->owning_port->owning_controller;
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&ihost->scic_lock, flags);
 326
 327         if (tmr->cancel)
 328                 goto done;
 329
 330         dev_dbg(sciphy_to_dev(iphy),
 331                  "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
 332                  "timeout.\n",
 333                  __func__,
 334                  iphy);
 335
 336         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 337 done:
 338         spin_unlock_irqrestore(&ihost->scic_lock, flags);
 339 }
 340
 341 /**
 342  * This method returns the port currently containing this phy. If the phy is
 343  *    currently contained by the dummy port, then the phy is considered to not
 344  *    be part of a port.
 345  * @sci_phy: This parameter specifies the phy for which to retrieve the
 346  *    containing port.
 347  *
 348  * This method returns a handle to a port that contains the supplied phy.
 349  * NULL This value is returned if the phy is not part of a real
 350  * port (i.e. it's contained in the dummy port). !NULL All other
 351  * values indicate a handle/pointer to the port containing the phy.
 352  */
 353 struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy)
 354 {
 355         struct isci_port *iport = iphy->owning_port;
 356
 357         if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT)
 358                 return NULL;
 359
 360         return iphy->owning_port;
 361 }
 362
 363 /**
 364  * This method will assign a port to the phy object.
 365  * @out]: iphy This parameter specifies the phy for which to assign a port
 366  *    object.
 367  *
 368  *
 369  */
 370 void sci_phy_set_port(
 371         struct isci_phy *iphy,
 372         struct isci_port *iport)
 373 {
 374         iphy->owning_port = iport;
 375
 376         if (iphy->bcn_received_while_port_unassigned) {
 377                 iphy->bcn_received_while_port_unassigned = false;
 378                 sci_port_broadcast_change_received(iphy->owning_port, iphy);
 379         }
 380 }
 381
 382 enum sci_status sci_phy_initialize(struct isci_phy *iphy,
 383                                    struct scu_transport_layer_registers __iomem *tl,
 384                                    struct scu_link_layer_registers __iomem *ll)
 385 {
 386         /* Perfrom the initialization of the TL hardware */
 387         sci_phy_transport_layer_initialization(iphy, tl);
 388
 389         /* Perofrm the initialization of the PE hardware */
 390         sci_phy_link_layer_initialization(iphy, ll);
 391
 392         /* There is nothing that needs to be done in this state just
 393          * transition to the stopped state
 394          */
 395         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 396
 397         return SCI_SUCCESS;
 398 }
 399
 400 /**
 401  * This method assigns the direct attached device ID for this phy.
 402  *
 403  * @iphy The phy for which the direct attached device id is to
 404  *       be assigned.
 405  * @device_id The direct attached device ID to assign to the phy.
 406  *       This will either be the RNi for the device or an invalid RNi if there
 407  *       is no current device assigned to the phy.
 408  */
 409 void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id)
 410 {
 411         u32 tl_control;
 412
 413         writel(device_id, &iphy->transport_layer_registers->stp_rni);
 414
 415         /*
 416          * The read should guarantee that the first write gets posted
 417          * before the next write
 418          */
 419         tl_control = readl(&iphy->transport_layer_registers->control);
 420         tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
 421         writel(tl_control, &iphy->transport_layer_registers->control);
 422 }
 423
 424 static void sci_phy_suspend(struct isci_phy *iphy)
 425 {
 426         u32 scu_sas_pcfg_value;
 427
 428         scu_sas_pcfg_value =
 429                 readl(&iphy->link_layer_registers->phy_configuration);
 430         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 431         writel(scu_sas_pcfg_value,
 432                 &iphy->link_layer_registers->phy_configuration);
 433
 434         sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
 435 }
 436
 437 void sci_phy_resume(struct isci_phy *iphy)
 438 {
 439         u32 scu_sas_pcfg_value;
 440
 441         scu_sas_pcfg_value =
 442                 readl(&iphy->link_layer_registers->phy_configuration);
 443         scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 444         writel(scu_sas_pcfg_value,
 445                 &iphy->link_layer_registers->phy_configuration);
 446 }
 447
 448 void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
 449 {
 450         sas->high = readl(&iphy->link_layer_registers->source_sas_address_high);
 451         sas->low = readl(&iphy->link_layer_registers->source_sas_address_low);
 452 }
 453
 454 void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
 455 {
 456         struct sas_identify_frame *iaf;
 457
 458         iaf = &iphy->frame_rcvd.iaf;
 459         memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE);
 460 }
 461
 462 void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto)
 463 {
 464         proto->all = readl(&iphy->link_layer_registers->transmit_identification);
 465 }
 466
 467 enum sci_status sci_phy_start(struct isci_phy *iphy)
 468 {
 469         enum sci_phy_states state = iphy->sm.current_state_id;
 470
 471         if (state != SCI_PHY_STOPPED) {
 472                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 473                         __func__, phy_state_name(state));
 474                 return SCI_FAILURE_INVALID_STATE;
 475         }
 476
 477         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 478         return SCI_SUCCESS;
 479 }
 480
 481 enum sci_status sci_phy_stop(struct isci_phy *iphy)
 482 {
 483         enum sci_phy_states state = iphy->sm.current_state_id;
 484
 485         switch (state) {
 486         case SCI_PHY_SUB_INITIAL:
 487         case SCI_PHY_SUB_AWAIT_OSSP_EN:
 488         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 489         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 490         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 491         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 492         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 493         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 494         case SCI_PHY_SUB_FINAL:
 495         case SCI_PHY_READY:
 496                 break;
 497         default:
 498                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 499                         __func__, phy_state_name(state));
 500                 return SCI_FAILURE_INVALID_STATE;
 501         }
 502
 503         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 504         return SCI_SUCCESS;
 505 }
 506
 507 enum sci_status sci_phy_reset(struct isci_phy *iphy)
 508 {
 509         enum sci_phy_states state = iphy->sm.current_state_id;
 510
 511         if (state != SCI_PHY_READY) {
 512                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 513                         __func__, phy_state_name(state));
 514                 return SCI_FAILURE_INVALID_STATE;
 515         }
 516
 517         sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
 518         return SCI_SUCCESS;
 519 }
 520
 521 enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy)
 522 {
 523         enum sci_phy_states state = iphy->sm.current_state_id;
 524
 525         switch (state) {
 526         case SCI_PHY_SUB_AWAIT_SAS_POWER: {
 527                 u32 enable_spinup;
 528
 529                 enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
 530                 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
 531                 writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
 532
 533                 /* Change state to the final state this substate machine has run to completion */
 534                 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
 535
 536                 return SCI_SUCCESS;
 537         }
 538         case SCI_PHY_SUB_AWAIT_SATA_POWER: {
 539                 u32 scu_sas_pcfg_value;
 540
 541                 /* Release the spinup hold state and reset the OOB state machine */
 542                 scu_sas_pcfg_value =
 543                         readl(&iphy->link_layer_registers->phy_configuration);
 544                 scu_sas_pcfg_value &=
 545                         ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
 546                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 547                 writel(scu_sas_pcfg_value,
 548                         &iphy->link_layer_registers->phy_configuration);
 549
 550                 /* Now restart the OOB operation */
 551                 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 552                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
 553                 writel(scu_sas_pcfg_value,
 554                         &iphy->link_layer_registers->phy_configuration);
 555
 556                 /* Change state to the final state this substate machine has run to completion */
 557                 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
 558
 559                 return SCI_SUCCESS;
 560         }
 561         default:
 562                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 563                         __func__, phy_state_name(state));
 564                 return SCI_FAILURE_INVALID_STATE;
 565         }
 566 }
 567
 568 static void sci_phy_start_sas_link_training(struct isci_phy *iphy)
 569 {
 570         /* continue the link training for the phy as if it were a SAS PHY
 571          * instead of a SATA PHY. This is done because the completion queue had a SAS
 572          * PHY DETECTED event when the state machine was expecting a SATA PHY event.
 573          */
 574         u32 phy_control;
 575
 576         phy_control = readl(&iphy->link_layer_registers->phy_configuration);
 577         phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
 578         writel(phy_control,
 579                &iphy->link_layer_registers->phy_configuration);
 580
 581         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
 582
 583         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
 584 }
 585
 586 static void sci_phy_start_sata_link_training(struct isci_phy *iphy)
 587 {
 588         /* This method continues the link training for the phy as if it were a SATA PHY
 589          * instead of a SAS PHY.  This is done because the completion queue had a SATA
 590          * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
 591          */
 592         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
 593
 594         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
 595 }
 596
 597 /**
 598  * sci_phy_complete_link_training - perform processing common to
 599  *    all protocols upon completion of link training.
 600  * @sci_phy: This parameter specifies the phy object for which link training
 601  *    has completed.
 602  * @max_link_rate: This parameter specifies the maximum link rate to be
 603  *    associated with this phy.
 604  * @next_state: This parameter specifies the next state for the phy's starting
 605  *    sub-state machine.
 606  *
 607  */
 608 static void sci_phy_complete_link_training(struct isci_phy *iphy,
 609                                            enum sas_linkrate max_link_rate,
 610                                            u32 next_state)
 611 {
 612         iphy->max_negotiated_speed = max_link_rate;
 613
 614         sci_change_state(&iphy->sm, next_state);
 615 }
 616
 617 static const char *phy_event_name(u32 event_code)
 618 {
 619         switch (scu_get_event_code(event_code)) {
 620         case SCU_EVENT_PORT_SELECTOR_DETECTED:
 621                 return "port selector";
 622         case SCU_EVENT_SENT_PORT_SELECTION:
 623                 return "port selection";
 624         case SCU_EVENT_HARD_RESET_TRANSMITTED:
 625                 return "tx hard reset";
 626         case SCU_EVENT_HARD_RESET_RECEIVED:
 627                 return "rx hard reset";
 628         case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 629                 return "identify timeout";
 630         case SCU_EVENT_LINK_FAILURE:
 631                 return "link fail";
 632         case SCU_EVENT_SATA_SPINUP_HOLD:
 633                 return "sata spinup hold";
 634         case SCU_EVENT_SAS_15_SSC:
 635         case SCU_EVENT_SAS_15:
 636                 return "sas 1.5";
 637         case SCU_EVENT_SAS_30_SSC:
 638         case SCU_EVENT_SAS_30:
 639                 return "sas 3.0";
 640         case SCU_EVENT_SAS_60_SSC:
 641         case SCU_EVENT_SAS_60:
 642                 return "sas 6.0";
 643         case SCU_EVENT_SATA_15_SSC:
 644         case SCU_EVENT_SATA_15:
 645                 return "sata 1.5";
 646         case SCU_EVENT_SATA_30_SSC:
 647         case SCU_EVENT_SATA_30:
 648                 return "sata 3.0";
 649         case SCU_EVENT_SATA_60_SSC:
 650         case SCU_EVENT_SATA_60:
 651                 return "sata 6.0";
 652         case SCU_EVENT_SAS_PHY_DETECTED:
 653                 return "sas detect";
 654         case SCU_EVENT_SATA_PHY_DETECTED:
 655                 return "sata detect";
 656         default:
 657                 return "unknown";
 658         }
 659 }
 660
 661 #define phy_event_dbg(iphy, state, code) \
 662         dev_dbg(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
 663                 phy_to_host(iphy)->id, iphy->phy_index, \
 664                 phy_state_name(state), phy_event_name(code), code)
 665
 666 #define phy_event_warn(iphy, state, code) \
 667         dev_warn(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
 668                 phy_to_host(iphy)->id, iphy->phy_index, \
 669                 phy_state_name(state), phy_event_name(code), code)
 670
 671 enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code)
 672 {
 673         enum sci_phy_states state = iphy->sm.current_state_id;
 674
 675         switch (state) {
 676         case SCI_PHY_SUB_AWAIT_OSSP_EN:
 677                 switch (scu_get_event_code(event_code)) {
 678                 case SCU_EVENT_SAS_PHY_DETECTED:
 679                         sci_phy_start_sas_link_training(iphy);
 680                         iphy->is_in_link_training = true;
 681                         break;
 682                 case SCU_EVENT_SATA_SPINUP_HOLD:
 683                         sci_phy_start_sata_link_training(iphy);
 684                         iphy->is_in_link_training = true;
 685                         break;
 686                 default:
 687                         phy_event_dbg(iphy, state, event_code);
 688                         return SCI_FAILURE;
 689                 }
 690                 return SCI_SUCCESS;
 691         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 692                 switch (scu_get_event_code(event_code)) {
 693                 case SCU_EVENT_SAS_PHY_DETECTED:
 694                         /*
 695                          * Why is this being reported again by the controller?
 696                          * We would re-enter this state so just stay here */
 697                         break;
 698                 case SCU_EVENT_SAS_15:
 699                 case SCU_EVENT_SAS_15_SSC:
 700                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
 701                                                        SCI_PHY_SUB_AWAIT_IAF_UF);
 702                         break;
 703                 case SCU_EVENT_SAS_30:
 704                 case SCU_EVENT_SAS_30_SSC:
 705                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
 706                                                        SCI_PHY_SUB_AWAIT_IAF_UF);
 707                         break;
 708                 case SCU_EVENT_SAS_60:
 709                 case SCU_EVENT_SAS_60_SSC:
 710                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
 711                                                        SCI_PHY_SUB_AWAIT_IAF_UF);
 712                         break;
 713                 case SCU_EVENT_SATA_SPINUP_HOLD:
 714                         /*
 715                          * We were doing SAS PHY link training and received a SATA PHY event
 716                          * continue OOB/SN as if this were a SATA PHY */
 717                         sci_phy_start_sata_link_training(iphy);
 718                         break;
 719                 case SCU_EVENT_LINK_FAILURE:
 720                         /* Link failure change state back to the starting state */
 721                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 722                         break;
 723                 default:
 724                         phy_event_warn(iphy, state, event_code);
 725                         return SCI_FAILURE;
 726                         break;
 727                 }
 728                 return SCI_SUCCESS;
 729         case SCI_PHY_SUB_AWAIT_IAF_UF:
 730                 switch (scu_get_event_code(event_code)) {
 731                 case SCU_EVENT_SAS_PHY_DETECTED:
 732                         /* Backup the state machine */
 733                         sci_phy_start_sas_link_training(iphy);
 734                         break;
 735                 case SCU_EVENT_SATA_SPINUP_HOLD:
 736                         /* We were doing SAS PHY link training and received a
 737                          * SATA PHY event continue OOB/SN as if this were a
 738                          * SATA PHY
 739                          */
 740                         sci_phy_start_sata_link_training(iphy);
 741                         break;
 742                 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 743                 case SCU_EVENT_LINK_FAILURE:
 744                 case SCU_EVENT_HARD_RESET_RECEIVED:
 745                         /* Start the oob/sn state machine over again */
 746                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 747                         break;
 748                 default:
 749                         phy_event_warn(iphy, state, event_code);
 750                         return SCI_FAILURE;
 751                 }
 752                 return SCI_SUCCESS;
 753         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 754                 switch (scu_get_event_code(event_code)) {
 755                 case SCU_EVENT_LINK_FAILURE:
 756                         /* Link failure change state back to the starting state */
 757                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 758                         break;
 759                 default:
 760                         phy_event_warn(iphy, state, event_code);
 761                         return SCI_FAILURE;
 762                 }
 763                 return SCI_SUCCESS;
 764         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 765                 switch (scu_get_event_code(event_code)) {
 766                 case SCU_EVENT_LINK_FAILURE:
 767                         /* Link failure change state back to the starting state */
 768                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 769                         break;
 770                 case SCU_EVENT_SATA_SPINUP_HOLD:
 771                         /* These events are received every 10ms and are
 772                          * expected while in this state
 773                          */
 774                         break;
 775
 776                 case SCU_EVENT_SAS_PHY_DETECTED:
 777                         /* There has been a change in the phy type before OOB/SN for the
 778                          * SATA finished start down the SAS link traning path.
 779                          */
 780                         sci_phy_start_sas_link_training(iphy);
 781                         break;
 782
 783                 default:
 784                         phy_event_warn(iphy, state, event_code);
 785                         return SCI_FAILURE;
 786                 }
 787                 return SCI_SUCCESS;
 788         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 789                 switch (scu_get_event_code(event_code)) {
 790                 case SCU_EVENT_LINK_FAILURE:
 791                         /* Link failure change state back to the starting state */
 792                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 793                         break;
 794                 case SCU_EVENT_SATA_SPINUP_HOLD:
 795                         /* These events might be received since we dont know how many may be in
 796                          * the completion queue while waiting for power
 797                          */
 798                         break;
 799                 case SCU_EVENT_SATA_PHY_DETECTED:
 800                         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
 801
 802                         /* We have received the SATA PHY notification change state */
 803                         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 804                         break;
 805                 case SCU_EVENT_SAS_PHY_DETECTED:
 806                         /* There has been a change in the phy type before OOB/SN for the
 807                          * SATA finished start down the SAS link traning path.
 808                          */
 809                         sci_phy_start_sas_link_training(iphy);
 810                         break;
 811                 default:
 812                         phy_event_warn(iphy, state, event_code);
 813                         return SCI_FAILURE;
 814                 }
 815                 return SCI_SUCCESS;
 816         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 817                 switch (scu_get_event_code(event_code)) {
 818                 case SCU_EVENT_SATA_PHY_DETECTED:
 819                         /*
 820                          * The hardware reports multiple SATA PHY detected events
 821                          * ignore the extras */
 822                         break;
 823                 case SCU_EVENT_SATA_15:
 824                 case SCU_EVENT_SATA_15_SSC:
 825                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
 826                                                        SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 827                         break;
 828                 case SCU_EVENT_SATA_30:
 829                 case SCU_EVENT_SATA_30_SSC:
 830                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
 831                                                        SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 832                         break;
 833                 case SCU_EVENT_SATA_60:
 834                 case SCU_EVENT_SATA_60_SSC:
 835                         sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
 836                                                        SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 837                         break;
 838                 case SCU_EVENT_LINK_FAILURE:
 839                         /* Link failure change state back to the starting state */
 840                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 841                         break;
 842                 case SCU_EVENT_SAS_PHY_DETECTED:
 843                         /*
 844                          * There has been a change in the phy type before OOB/SN for the
 845                          * SATA finished start down the SAS link traning path. */
 846                         sci_phy_start_sas_link_training(iphy);
 847                         break;
 848                 default:
 849                         phy_event_warn(iphy, state, event_code);
 850                         return SCI_FAILURE;
 851                 }
 852
 853                 return SCI_SUCCESS;
 854         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 855                 switch (scu_get_event_code(event_code)) {
 856                 case SCU_EVENT_SATA_PHY_DETECTED:
 857                         /* Backup the state machine */
 858                         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 859                         break;
 860
 861                 case SCU_EVENT_LINK_FAILURE:
 862                         /* Link failure change state back to the starting state */
 863                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 864                         break;
 865
 866                 default:
 867                         phy_event_warn(iphy, state, event_code);
 868                         return SCI_FAILURE;
 869                 }
 870                 return SCI_SUCCESS;
 871         case SCI_PHY_READY:
 872                 switch (scu_get_event_code(event_code)) {
 873                 case SCU_EVENT_LINK_FAILURE:
 874                         /* Link failure change state back to the starting state */
 875                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 876                         break;
 877                 case SCU_EVENT_BROADCAST_CHANGE:
 878                         /* Broadcast change received. Notify the port. */
 879                         if (phy_get_non_dummy_port(iphy) != NULL)
 880                                 sci_port_broadcast_change_received(iphy->owning_port, iphy);
 881                         else
 882                                 iphy->bcn_received_while_port_unassigned = true;
 883                         break;
 884                 default:
 885                         phy_event_warn(iphy, state, event_code);
 886                         return SCI_FAILURE_INVALID_STATE;
 887                 }
 888                 return SCI_SUCCESS;
 889         case SCI_PHY_RESETTING:
 890                 switch (scu_get_event_code(event_code)) {
 891                 case SCU_EVENT_HARD_RESET_TRANSMITTED:
 892                         /* Link failure change state back to the starting state */
 893                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 894                         break;
 895                 default:
 896                         phy_event_warn(iphy, state, event_code);
 897                         return SCI_FAILURE_INVALID_STATE;
 898                         break;
 899                 }
 900                 return SCI_SUCCESS;
 901         default:
 902                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 903                         __func__, phy_state_name(state));
 904                 return SCI_FAILURE_INVALID_STATE;
 905         }
 906 }
 907
 908 enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index)
 909 {
 910         enum sci_phy_states state = iphy->sm.current_state_id;
 911         struct isci_host *ihost = iphy->owning_port->owning_controller;
 912         enum sci_status result;
 913         unsigned long flags;
 914
 915         switch (state) {
 916         case SCI_PHY_SUB_AWAIT_IAF_UF: {
 917                 u32 *frame_words;
 918                 struct sas_identify_frame iaf;
 919
 920                 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
 921                                                                   frame_index,
 922                                                                   (void **)&frame_words);
 923
 924                 if (result != SCI_SUCCESS)
 925                         return result;
 926
 927                 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
 928                 if (iaf.frame_type == 0) {
 929                         u32 state;
 930
 931                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
 932                         memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
 933                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
 934                         if (iaf.smp_tport) {
 935                                 /* We got the IAF for an expander PHY go to the final
 936                                  * state since there are no power requirements for
 937                                  * expander phys.
 938                                  */
 939                                 state = SCI_PHY_SUB_FINAL;
 940                         } else {
 941                                 /* We got the IAF we can now go to the await spinup
 942                                  * semaphore state
 943                                  */
 944                                 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
 945                         }
 946                         sci_change_state(&iphy->sm, state);
 947                         result = SCI_SUCCESS;
 948                 } else
 949                         dev_warn(sciphy_to_dev(iphy),
 950                                 "%s: PHY starting substate machine received "
 951                                 "unexpected frame id %x\n",
 952                                 __func__, frame_index);
 953
 954                 sci_controller_release_frame(ihost, frame_index);
 955                 return result;
 956         }
 957         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
 958                 struct dev_to_host_fis *frame_header;
 959                 u32 *fis_frame_data;
 960
 961                 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
 962                                                                   frame_index,
 963                                                                   (void **)&frame_header);
 964
 965                 if (result != SCI_SUCCESS)
 966                         return result;
 967
 968                 if ((frame_header->fis_type == FIS_REGD2H) &&
 969                     !(frame_header->status & ATA_BUSY)) {
 970                         sci_unsolicited_frame_control_get_buffer(&ihost->uf_control,
 971                                                                  frame_index,
 972                                                                  (void **)&fis_frame_data);
 973
 974                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
 975                         sci_controller_copy_sata_response(&iphy->frame_rcvd.fis,
 976                                                           frame_header,
 977                                                           fis_frame_data);
 978                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
 979
 980                         /* got IAF we can now go to the await spinup semaphore state */
 981                         sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
 982
 983                         result = SCI_SUCCESS;
 984                 } else
 985                         dev_warn(sciphy_to_dev(iphy),
 986                                  "%s: PHY starting substate machine received "
 987                                  "unexpected frame id %x\n",
 988                                  __func__, frame_index);
 989
 990                 /* Regardless of the result we are done with this frame with it */
 991                 sci_controller_release_frame(ihost, frame_index);
 992
 993                 return result;
 994         }
 995         default:
 996                 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 997                         __func__, phy_state_name(state));
 998                 return SCI_FAILURE_INVALID_STATE;
 999         }
1000
1001 }
1002
1003 static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
1004 {
1005         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1006
1007         /* This is just an temporary state go off to the starting state */
1008         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
1009 }
1010
1011 static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
1012 {
1013         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1014         struct isci_host *ihost = iphy->owning_port->owning_controller;
1015
1016         sci_controller_power_control_queue_insert(ihost, iphy);
1017 }
1018
1019 static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1020 {
1021         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1022         struct isci_host *ihost = iphy->owning_port->owning_controller;
1023
1024         sci_controller_power_control_queue_remove(ihost, iphy);
1025 }
1026
1027 static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1028 {
1029         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1030         struct isci_host *ihost = iphy->owning_port->owning_controller;
1031
1032         sci_controller_power_control_queue_insert(ihost, iphy);
1033 }
1034
1035 static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1036 {
1037         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1038         struct isci_host *ihost = iphy->owning_port->owning_controller;
1039
1040         sci_controller_power_control_queue_remove(ihost, iphy);
1041 }
1042
1043 static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1044 {
1045         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1046
1047         sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1048 }
1049
1050 static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1051 {
1052         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1053
1054         sci_del_timer(&iphy->sata_timer);
1055 }
1056
1057 static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1058 {
1059         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1060
1061         sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1062 }
1063
1064 static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1065 {
1066         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1067
1068         sci_del_timer(&iphy->sata_timer);
1069 }
1070
1071 static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1072 {
1073         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1074
1075         if (sci_port_link_detected(iphy->owning_port, iphy)) {
1076
1077                 /*
1078                  * Clear the PE suspend condition so we can actually
1079                  * receive SIG FIS
1080                  * The hardware will not respond to the XRDY until the PE
1081                  * suspend condition is cleared.
1082                  */
1083                 sci_phy_resume(iphy);
1084
1085                 sci_mod_timer(&iphy->sata_timer,
1086                               SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1087         } else
1088                 iphy->is_in_link_training = false;
1089 }
1090
1091 static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1092 {
1093         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1094
1095         sci_del_timer(&iphy->sata_timer);
1096 }
1097
1098 static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1099 {
1100         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1101
1102         /* State machine has run to completion so exit out and change
1103          * the base state machine to the ready state
1104          */
1105         sci_change_state(&iphy->sm, SCI_PHY_READY);
1106 }
1107
1108 /**
1109  *
1110  * @sci_phy: This is the struct isci_phy object to stop.
1111  *
1112  * This method will stop the struct isci_phy object. This does not reset the
1113  * protocol engine it just suspends it and places it in a state where it will
1114  * not cause the end device to power up. none
1115  */
1116 static void scu_link_layer_stop_protocol_engine(
1117         struct isci_phy *iphy)
1118 {
1119         u32 scu_sas_pcfg_value;
1120         u32 enable_spinup_value;
1121
1122         /* Suspend the protocol engine and place it in a sata spinup hold state */
1123         scu_sas_pcfg_value =
1124                 readl(&iphy->link_layer_registers->phy_configuration);
1125         scu_sas_pcfg_value |=
1126                 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1127                  SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1128                  SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1129         writel(scu_sas_pcfg_value,
1130                &iphy->link_layer_registers->phy_configuration);
1131
1132         /* Disable the notify enable spinup primitives */
1133         enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1134         enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1135         writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1136 }
1137
1138 static void scu_link_layer_start_oob(struct isci_phy *iphy)
1139 {
1140         struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers;
1141         u32 val;
1142
1143         /** Reset OOB sequence - start */
1144         val = readl(&ll->phy_configuration);
1145         val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1146                  SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1147         writel(val, &ll->phy_configuration);
1148         readl(&ll->phy_configuration); /* flush */
1149         /** Reset OOB sequence - end */
1150
1151         /** Start OOB sequence - start */
1152         val = readl(&ll->phy_configuration);
1153         val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1154         writel(val, &ll->phy_configuration);
1155         readl(&ll->phy_configuration); /* flush */
1156         /** Start OOB sequence - end */
1157 }
1158
1159 /**
1160  *
1161  *
1162  * This method will transmit a hard reset request on the specified phy. The SCU
1163  * hardware requires that we reset the OOB state machine and set the hard reset
1164  * bit in the phy configuration register. We then must start OOB over with the
1165  * hard reset bit set.
1166  */
1167 static void scu_link_layer_tx_hard_reset(
1168         struct isci_phy *iphy)
1169 {
1170         u32 phy_configuration_value;
1171
1172         /*
1173          * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1174          * to the starting state. */
1175         phy_configuration_value =
1176                 readl(&iphy->link_layer_registers->phy_configuration);
1177         phy_configuration_value |=
1178                 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1179                  SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1180         writel(phy_configuration_value,
1181                &iphy->link_layer_registers->phy_configuration);
1182
1183         /* Now take the OOB state machine out of reset */
1184         phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1185         phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1186         writel(phy_configuration_value,
1187                &iphy->link_layer_registers->phy_configuration);
1188 }
1189
1190 static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1191 {
1192         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1193         struct isci_port *iport = iphy->owning_port;
1194         struct isci_host *ihost = iport->owning_controller;
1195
1196         /*
1197          * @todo We need to get to the controller to place this PE in a
1198          * reset state
1199          */
1200         sci_del_timer(&iphy->sata_timer);
1201
1202         scu_link_layer_stop_protocol_engine(iphy);
1203
1204         if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1205                 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1206 }
1207
1208 static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm)
1209 {
1210         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1211         struct isci_port *iport = iphy->owning_port;
1212         struct isci_host *ihost = iport->owning_controller;
1213
1214         scu_link_layer_stop_protocol_engine(iphy);
1215         scu_link_layer_start_oob(iphy);
1216
1217         /* We don't know what kind of phy we are going to be just yet */
1218         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1219         iphy->bcn_received_while_port_unassigned = false;
1220
1221         if (iphy->sm.previous_state_id == SCI_PHY_READY)
1222                 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1223
1224         sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1225 }
1226
1227 static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm)
1228 {
1229         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1230         struct isci_port *iport = iphy->owning_port;
1231         struct isci_host *ihost = iport->owning_controller;
1232
1233         sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy);
1234 }
1235
1236 static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm)
1237 {
1238         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1239
1240         sci_phy_suspend(iphy);
1241 }
1242
1243 static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1244 {
1245         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1246
1247         /* The phy is being reset, therefore deactivate it from the port.  In
1248          * the resetting state we don't notify the user regarding link up and
1249          * link down notifications
1250          */
1251         sci_port_deactivate_phy(iphy->owning_port, iphy, false);
1252
1253         if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1254                 scu_link_layer_tx_hard_reset(iphy);
1255         } else {
1256                 /* The SCU does not need to have a discrete reset state so
1257                  * just go back to the starting state.
1258                  */
1259                 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1260         }
1261 }
1262
1263 static const struct sci_base_state sci_phy_state_table[] = {
1264         [SCI_PHY_INITIAL] = { },
1265         [SCI_PHY_STOPPED] = {
1266                 .enter_state = sci_phy_stopped_state_enter,
1267         },
1268         [SCI_PHY_STARTING] = {
1269                 .enter_state = sci_phy_starting_state_enter,
1270         },
1271         [SCI_PHY_SUB_INITIAL] = {
1272                 .enter_state = sci_phy_starting_initial_substate_enter,
1273         },
1274         [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1275         [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1276         [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1277         [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1278                 .enter_state = sci_phy_starting_await_sas_power_substate_enter,
1279                 .exit_state  = sci_phy_starting_await_sas_power_substate_exit,
1280         },
1281         [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1282                 .enter_state = sci_phy_starting_await_sata_power_substate_enter,
1283                 .exit_state  = sci_phy_starting_await_sata_power_substate_exit
1284         },
1285         [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1286                 .enter_state = sci_phy_starting_await_sata_phy_substate_enter,
1287                 .exit_state  = sci_phy_starting_await_sata_phy_substate_exit
1288         },
1289         [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1290                 .enter_state = sci_phy_starting_await_sata_speed_substate_enter,
1291                 .exit_state  = sci_phy_starting_await_sata_speed_substate_exit
1292         },
1293         [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1294                 .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter,
1295                 .exit_state  = sci_phy_starting_await_sig_fis_uf_substate_exit
1296         },
1297         [SCI_PHY_SUB_FINAL] = {
1298                 .enter_state = sci_phy_starting_final_substate_enter,
1299         },
1300         [SCI_PHY_READY] = {
1301                 .enter_state = sci_phy_ready_state_enter,
1302                 .exit_state = sci_phy_ready_state_exit,
1303         },
1304         [SCI_PHY_RESETTING] = {
1305                 .enter_state = sci_phy_resetting_state_enter,
1306         },
1307         [SCI_PHY_FINAL] = { },
1308 };
1309
1310 void sci_phy_construct(struct isci_phy *iphy,
1311                             struct isci_port *iport, u8 phy_index)
1312 {
1313         sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL);
1314
1315         /* Copy the rest of the input data to our locals */
1316         iphy->owning_port = iport;
1317         iphy->phy_index = phy_index;
1318         iphy->bcn_received_while_port_unassigned = false;
1319         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1320         iphy->link_layer_registers = NULL;
1321         iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1322
1323         /* Create the SIGNATURE FIS Timeout timer for this phy */
1324         sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1325 }
1326
1327 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1328 {
1329         struct sci_oem_params *oem = &ihost->oem_parameters;
1330         u64 sci_sas_addr;
1331         __be64 sas_addr;
1332
1333         sci_sas_addr = oem->phys[index].sas_address.high;
1334         sci_sas_addr <<= 32;
1335         sci_sas_addr |= oem->phys[index].sas_address.low;
1336         sas_addr = cpu_to_be64(sci_sas_addr);
1337         memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1338
1339         iphy->sas_phy.enabled = 0;
1340         iphy->sas_phy.id = index;
1341         iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1342         iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1343         iphy->sas_phy.ha = &ihost->sas_ha;
1344         iphy->sas_phy.lldd_phy = iphy;
1345         iphy->sas_phy.enabled = 1;
1346         iphy->sas_phy.class = SAS;
1347         iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1348         iphy->sas_phy.tproto = 0;
1349         iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1350         iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1351         iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1352         iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1353         memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1354 }
1355
1356
1357 /**
1358  * isci_phy_control() - This function is one of the SAS Domain Template
1359  *    functions. This is a phy management function.
1360  * @phy: This parameter specifies the sphy being controlled.
1361  * @func: This parameter specifies the phy control function being invoked.
1362  * @buf: This parameter is specific to the phy function being invoked.
1363  *
1364  * status, zero indicates success.
1365  */
1366 int isci_phy_control(struct asd_sas_phy *sas_phy,
1367                      enum phy_func func,
1368                      void *buf)
1369 {
1370         int ret = 0;
1371         struct isci_phy *iphy = sas_phy->lldd_phy;
1372         struct asd_sas_port *port = sas_phy->port;
1373         struct isci_host *ihost = sas_phy->ha->lldd_ha;
1374         unsigned long flags;
1375
1376         dev_dbg(&ihost->pdev->dev,
1377                 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1378                 __func__, sas_phy, func, buf, iphy, port);
1379
1380         switch (func) {
1381         case PHY_FUNC_DISABLE:
1382                 spin_lock_irqsave(&ihost->scic_lock, flags);
1383                 sci_phy_stop(iphy);
1384                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1385                 break;
1386
1387         case PHY_FUNC_LINK_RESET:
1388                 spin_lock_irqsave(&ihost->scic_lock, flags);
1389                 sci_phy_stop(iphy);
1390                 sci_phy_start(iphy);
1391                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1392                 break;
1393
1394         case PHY_FUNC_HARD_RESET:
1395                 if (!port)
1396                         return -ENODEV;
1397
1398                 ret = isci_port_perform_hard_reset(ihost, port->lldd_port, iphy);
1399
1400                 break;
1401         case PHY_FUNC_GET_EVENTS: {
1402                 struct scu_link_layer_registers __iomem *r;
1403                 struct sas_phy *phy = sas_phy->phy;
1404
1405                 r = iphy->link_layer_registers;
1406                 phy->running_disparity_error_count = readl(&r->running_disparity_error_count);
1407                 phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count);
1408                 phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count);
1409                 phy->invalid_dword_count = readl(&r->invalid_dword_counter);
1410                 break;
1411         }
1412
1413         default:
1414                 dev_dbg(&ihost->pdev->dev,
1415                            "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1416                            __func__, sas_phy, func);
1417                 ret = -ENOSYS;
1418                 break;
1419         }
1420         return ret;
1421 }