drivers/scsi/isci/host.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55 #include <linux/circ_buf.h>
  56 #include <linux/device.h>
  57 #include <scsi/sas.h>
  58 #include "host.h"
  59 #include "isci.h"
  60 #include "port.h"
  61 #include "probe_roms.h"
  62 #include "remote_device.h"
  63 #include "request.h"
  64 #include "scu_completion_codes.h"
  65 #include "scu_event_codes.h"
  66 #include "registers.h"
  67 #include "scu_remote_node_context.h"
  68 #include "scu_task_context.h"
  69
  70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  71
  72 #define smu_max_ports(dcc_value) \
  73         (\
  74                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  75                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  76         )
  77
  78 #define smu_max_task_contexts(dcc_value)        \
  79         (\
  80                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  81                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  82         )
  83
  84 #define smu_max_rncs(dcc_value) \
  85         (\
  86                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
  87                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
  88         )
  89
  90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
  91
  92 /**
  93  *
  94  *
  95  * The number of milliseconds to wait while a given phy is consuming power
  96  * before allowing another set of phys to consume power. Ultimately, this will
  97  * be specified by OEM parameter.
  98  */
  99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 100
 101 /**
 102  * NORMALIZE_PUT_POINTER() -
 103  *
 104  * This macro will normalize the completion queue put pointer so its value can
 105  * be used as an array inde
 106  */
 107 #define NORMALIZE_PUT_POINTER(x) \
 108         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 109
 110
 111 /**
 112  * NORMALIZE_EVENT_POINTER() -
 113  *
 114  * This macro will normalize the completion queue event entry so its value can
 115  * be used as an index.
 116  */
 117 #define NORMALIZE_EVENT_POINTER(x) \
 118         (\
 119                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 120                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 121         )
 122
 123 /**
 124  * NORMALIZE_GET_POINTER() -
 125  *
 126  * This macro will normalize the completion queue get pointer so its value can
 127  * be used as an index into an array
 128  */
 129 #define NORMALIZE_GET_POINTER(x) \
 130         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 131
 132 /**
 133  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 134  *
 135  * This macro will normalize the completion queue cycle pointer so it matches
 136  * the completion queue cycle bit
 137  */
 138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 139         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 140
 141 /**
 142  * COMPLETION_QUEUE_CYCLE_BIT() -
 143  *
 144  * This macro will return the cycle bit of the completion queue entry
 145  */
 146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 147
 148 /* Init the state machine and call the state entry function (if any) */
 149 void sci_init_sm(struct sci_base_state_machine *sm,
 150                  const struct sci_base_state *state_table, u32 initial_state)
 151 {
 152         sci_state_transition_t handler;
 153
 154         sm->initial_state_id    = initial_state;
 155         sm->previous_state_id   = initial_state;
 156         sm->current_state_id    = initial_state;
 157         sm->state_table         = state_table;
 158
 159         handler = sm->state_table[initial_state].enter_state;
 160         if (handler)
 161                 handler(sm);
 162 }
 163
 164 /* Call the state exit fn, update the current state, call the state entry fn */
 165 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
 166 {
 167         sci_state_transition_t handler;
 168
 169         handler = sm->state_table[sm->current_state_id].exit_state;
 170         if (handler)
 171                 handler(sm);
 172
 173         sm->previous_state_id = sm->current_state_id;
 174         sm->current_state_id = next_state;
 175
 176         handler = sm->state_table[sm->current_state_id].enter_state;
 177         if (handler)
 178                 handler(sm);
 179 }
 180
 181 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
 182 {
 183         u32 get_value = ihost->completion_queue_get;
 184         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
 185
 186         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
 187             COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
 188                 return true;
 189
 190         return false;
 191 }
 192
 193 static bool sci_controller_isr(struct isci_host *ihost)
 194 {
 195         if (sci_controller_completion_queue_has_entries(ihost)) {
 196                 return true;
 197         } else {
 198                 /*
 199                  * we have a spurious interrupt it could be that we have already
 200                  * emptied the completion queue from a previous interrupt */
 201                 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 202
 203                 /*
 204                  * There is a race in the hardware that could cause us not to be notified
 205                  * of an interrupt completion if we do not take this step.  We will mask
 206                  * then unmask the interrupts so if there is another interrupt pending
 207                  * the clearing of the interrupt source we get the next interrupt message. */
 208                 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
 209                 writel(0, &ihost->smu_registers->interrupt_mask);
 210         }
 211
 212         return false;
 213 }
 214
 215 irqreturn_t isci_msix_isr(int vec, void *data)
 216 {
 217         struct isci_host *ihost = data;
 218
 219         if (sci_controller_isr(ihost))
 220                 tasklet_schedule(&ihost->completion_tasklet);
 221
 222         return IRQ_HANDLED;
 223 }
 224
 225 static bool sci_controller_error_isr(struct isci_host *ihost)
 226 {
 227         u32 interrupt_status;
 228
 229         interrupt_status =
 230                 readl(&ihost->smu_registers->interrupt_status);
 231         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
 232
 233         if (interrupt_status != 0) {
 234                 /*
 235                  * There is an error interrupt pending so let it through and handle
 236                  * in the callback */
 237                 return true;
 238         }
 239
 240         /*
 241          * There is a race in the hardware that could cause us not to be notified
 242          * of an interrupt completion if we do not take this step.  We will mask
 243          * then unmask the error interrupts so if there was another interrupt
 244          * pending we will be notified.
 245          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
 246         writel(0xff, &ihost->smu_registers->interrupt_mask);
 247         writel(0, &ihost->smu_registers->interrupt_mask);
 248
 249         return false;
 250 }
 251
 252 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
 253 {
 254         u32 index = SCU_GET_COMPLETION_INDEX(ent);
 255         struct isci_request *ireq = ihost->reqs[index];
 256
 257         /* Make sure that we really want to process this IO request */
 258         if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
 259             ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
 260             ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
 261                 /* Yep this is a valid io request pass it along to the
 262                  * io request handler
 263                  */
 264                 sci_io_request_tc_completion(ireq, ent);
 265 }
 266
 267 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
 268 {
 269         u32 index;
 270         struct isci_request *ireq;
 271         struct isci_remote_device *idev;
 272
 273         index = SCU_GET_COMPLETION_INDEX(ent);
 274
 275         switch (scu_get_command_request_type(ent)) {
 276         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
 277         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
 278                 ireq = ihost->reqs[index];
 279                 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
 280                          __func__, ent, ireq);
 281                 /* @todo For a post TC operation we need to fail the IO
 282                  * request
 283                  */
 284                 break;
 285         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
 286         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
 287         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
 288                 idev = ihost->device_table[index];
 289                 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
 290                          __func__, ent, idev);
 291                 /* @todo For a port RNC operation we need to fail the
 292                  * device
 293                  */
 294                 break;
 295         default:
 296                 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
 297                          __func__, ent);
 298                 break;
 299         }
 300 }
 301
 302 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
 303 {
 304         u32 index;
 305         u32 frame_index;
 306
 307         struct scu_unsolicited_frame_header *frame_header;
 308         struct isci_phy *iphy;
 309         struct isci_remote_device *idev;
 310
 311         enum sci_status result = SCI_FAILURE;
 312
 313         frame_index = SCU_GET_FRAME_INDEX(ent);
 314
 315         frame_header = ihost->uf_control.buffers.array[frame_index].header;
 316         ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
 317
 318         if (SCU_GET_FRAME_ERROR(ent)) {
 319                 /*
 320                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
 321                  * /       this cause a problem? We expect the phy initialization will
 322                  * /       fail if there is an error in the frame. */
 323                 sci_controller_release_frame(ihost, frame_index);
 324                 return;
 325         }
 326
 327         if (frame_header->is_address_frame) {
 328                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 329                 iphy = &ihost->phys[index];
 330                 result = sci_phy_frame_handler(iphy, frame_index);
 331         } else {
 332
 333                 index = SCU_GET_COMPLETION_INDEX(ent);
 334
 335                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
 336                         /*
 337                          * This is a signature fis or a frame from a direct attached SATA
 338                          * device that has not yet been created.  In either case forwared
 339                          * the frame to the PE and let it take care of the frame data. */
 340                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 341                         iphy = &ihost->phys[index];
 342                         result = sci_phy_frame_handler(iphy, frame_index);
 343                 } else {
 344                         if (index < ihost->remote_node_entries)
 345                                 idev = ihost->device_table[index];
 346                         else
 347                                 idev = NULL;
 348
 349                         if (idev != NULL)
 350                                 result = sci_remote_device_frame_handler(idev, frame_index);
 351                         else
 352                                 sci_controller_release_frame(ihost, frame_index);
 353                 }
 354         }
 355
 356         if (result != SCI_SUCCESS) {
 357                 /*
 358                  * / @todo Is there any reason to report some additional error message
 359                  * /       when we get this failure notifiction? */
 360         }
 361 }
 362
 363 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
 364 {
 365         struct isci_remote_device *idev;
 366         struct isci_request *ireq;
 367         struct isci_phy *iphy;
 368         u32 index;
 369
 370         index = SCU_GET_COMPLETION_INDEX(ent);
 371
 372         switch (scu_get_event_type(ent)) {
 373         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
 374                 /* / @todo The driver did something wrong and we need to fix the condtion. */
 375                 dev_err(&ihost->pdev->dev,
 376                         "%s: SCIC Controller 0x%p received SMU command error "
 377                         "0x%x\n",
 378                         __func__,
 379                         ihost,
 380                         ent);
 381                 break;
 382
 383         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
 384         case SCU_EVENT_TYPE_SMU_ERROR:
 385         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
 386                 /*
 387                  * / @todo This is a hardware failure and its likely that we want to
 388                  * /       reset the controller. */
 389                 dev_err(&ihost->pdev->dev,
 390                         "%s: SCIC Controller 0x%p received fatal controller "
 391                         "event  0x%x\n",
 392                         __func__,
 393                         ihost,
 394                         ent);
 395                 break;
 396
 397         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
 398                 ireq = ihost->reqs[index];
 399                 sci_io_request_event_handler(ireq, ent);
 400                 break;
 401
 402         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
 403                 switch (scu_get_event_specifier(ent)) {
 404                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
 405                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
 406                         ireq = ihost->reqs[index];
 407                         if (ireq != NULL)
 408                                 sci_io_request_event_handler(ireq, ent);
 409                         else
 410                                 dev_warn(&ihost->pdev->dev,
 411                                          "%s: SCIC Controller 0x%p received "
 412                                          "event 0x%x for io request object "
 413                                          "that doesnt exist.\n",
 414                                          __func__,
 415                                          ihost,
 416                                          ent);
 417
 418                         break;
 419
 420                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
 421                         idev = ihost->device_table[index];
 422                         if (idev != NULL)
 423                                 sci_remote_device_event_handler(idev, ent);
 424                         else
 425                                 dev_warn(&ihost->pdev->dev,
 426                                          "%s: SCIC Controller 0x%p received "
 427                                          "event 0x%x for remote device object "
 428                                          "that doesnt exist.\n",
 429                                          __func__,
 430                                          ihost,
 431                                          ent);
 432
 433                         break;
 434                 }
 435                 break;
 436
 437         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
 438         /*
 439          * direct the broadcast change event to the phy first and then let
 440          * the phy redirect the broadcast change to the port object */
 441         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
 442         /*
 443          * direct error counter event to the phy object since that is where
 444          * we get the event notification.  This is a type 4 event. */
 445         case SCU_EVENT_TYPE_OSSP_EVENT:
 446                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 447                 iphy = &ihost->phys[index];
 448                 sci_phy_event_handler(iphy, ent);
 449                 break;
 450
 451         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
 452         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
 453         case SCU_EVENT_TYPE_RNC_OPS_MISC:
 454                 if (index < ihost->remote_node_entries) {
 455                         idev = ihost->device_table[index];
 456
 457                         if (idev != NULL)
 458                                 sci_remote_device_event_handler(idev, ent);
 459                 } else
 460                         dev_err(&ihost->pdev->dev,
 461                                 "%s: SCIC Controller 0x%p received event 0x%x "
 462                                 "for remote device object 0x%0x that doesnt "
 463                                 "exist.\n",
 464                                 __func__,
 465                                 ihost,
 466                                 ent,
 467                                 index);
 468
 469                 break;
 470
 471         default:
 472                 dev_warn(&ihost->pdev->dev,
 473                          "%s: SCIC Controller received unknown event code %x\n",
 474                          __func__,
 475                          ent);
 476                 break;
 477         }
 478 }
 479
 480 static void sci_controller_process_completions(struct isci_host *ihost)
 481 {
 482         u32 completion_count = 0;
 483         u32 ent;
 484         u32 get_index;
 485         u32 get_cycle;
 486         u32 event_get;
 487         u32 event_cycle;
 488
 489         dev_dbg(&ihost->pdev->dev,
 490                 "%s: completion queue begining get:0x%08x\n",
 491                 __func__,
 492                 ihost->completion_queue_get);
 493
 494         /* Get the component parts of the completion queue */
 495         get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
 496         get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
 497
 498         event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
 499         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
 500
 501         while (
 502                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
 503                 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
 504                 ) {
 505                 completion_count++;
 506
 507                 ent = ihost->completion_queue[get_index];
 508
 509                 /* increment the get pointer and check for rollover to toggle the cycle bit */
 510                 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
 511                              (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
 512                 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
 513
 514                 dev_dbg(&ihost->pdev->dev,
 515                         "%s: completion queue entry:0x%08x\n",
 516                         __func__,
 517                         ent);
 518
 519                 switch (SCU_GET_COMPLETION_TYPE(ent)) {
 520                 case SCU_COMPLETION_TYPE_TASK:
 521                         sci_controller_task_completion(ihost, ent);
 522                         break;
 523
 524                 case SCU_COMPLETION_TYPE_SDMA:
 525                         sci_controller_sdma_completion(ihost, ent);
 526                         break;
 527
 528                 case SCU_COMPLETION_TYPE_UFI:
 529                         sci_controller_unsolicited_frame(ihost, ent);
 530                         break;
 531
 532                 case SCU_COMPLETION_TYPE_EVENT:
 533                         sci_controller_event_completion(ihost, ent);
 534                         break;
 535
 536                 case SCU_COMPLETION_TYPE_NOTIFY: {
 537                         event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
 538                                        (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
 539                         event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
 540
 541                         sci_controller_event_completion(ihost, ent);
 542                         break;
 543                 }
 544                 default:
 545                         dev_warn(&ihost->pdev->dev,
 546                                  "%s: SCIC Controller received unknown "
 547                                  "completion type %x\n",
 548                                  __func__,
 549                                  ent);
 550                         break;
 551                 }
 552         }
 553
 554         /* Update the get register if we completed one or more entries */
 555         if (completion_count > 0) {
 556                 ihost->completion_queue_get =
 557                         SMU_CQGR_GEN_BIT(ENABLE) |
 558                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
 559                         event_cycle |
 560                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
 561                         get_cycle |
 562                         SMU_CQGR_GEN_VAL(POINTER, get_index);
 563
 564                 writel(ihost->completion_queue_get,
 565                        &ihost->smu_registers->completion_queue_get);
 566
 567         }
 568
 569         dev_dbg(&ihost->pdev->dev,
 570                 "%s: completion queue ending get:0x%08x\n",
 571                 __func__,
 572                 ihost->completion_queue_get);
 573
 574 }
 575
 576 static void sci_controller_error_handler(struct isci_host *ihost)
 577 {
 578         u32 interrupt_status;
 579
 580         interrupt_status =
 581                 readl(&ihost->smu_registers->interrupt_status);
 582
 583         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
 584             sci_controller_completion_queue_has_entries(ihost)) {
 585
 586                 sci_controller_process_completions(ihost);
 587                 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
 588         } else {
 589                 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
 590                         interrupt_status);
 591
 592                 sci_change_state(&ihost->sm, SCIC_FAILED);
 593
 594                 return;
 595         }
 596
 597         /* If we dont process any completions I am not sure that we want to do this.
 598          * We are in the middle of a hardware fault and should probably be reset.
 599          */
 600         writel(0, &ihost->smu_registers->interrupt_mask);
 601 }
 602
 603 irqreturn_t isci_intx_isr(int vec, void *data)
 604 {
 605         irqreturn_t ret = IRQ_NONE;
 606         struct isci_host *ihost = data;
 607
 608         if (sci_controller_isr(ihost)) {
 609                 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 610                 tasklet_schedule(&ihost->completion_tasklet);
 611                 ret = IRQ_HANDLED;
 612         } else if (sci_controller_error_isr(ihost)) {
 613                 spin_lock(&ihost->scic_lock);
 614                 sci_controller_error_handler(ihost);
 615                 spin_unlock(&ihost->scic_lock);
 616                 ret = IRQ_HANDLED;
 617         }
 618
 619         return ret;
 620 }
 621
 622 irqreturn_t isci_error_isr(int vec, void *data)
 623 {
 624         struct isci_host *ihost = data;
 625
 626         if (sci_controller_error_isr(ihost))
 627                 sci_controller_error_handler(ihost);
 628
 629         return IRQ_HANDLED;
 630 }
 631
 632 /**
 633  * isci_host_start_complete() - This function is called by the core library,
 634  *    through the ISCI Module, to indicate controller start status.
 635  * @isci_host: This parameter specifies the ISCI host object
 636  * @completion_status: This parameter specifies the completion status from the
 637  *    core library.
 638  *
 639  */
 640 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
 641 {
 642         if (completion_status != SCI_SUCCESS)
 643                 dev_info(&ihost->pdev->dev,
 644                         "controller start timed out, continuing...\n");
 645         isci_host_change_state(ihost, isci_ready);
 646         clear_bit(IHOST_START_PENDING, &ihost->flags);
 647         wake_up(&ihost->eventq);
 648 }
 649
 650 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
 651 {
 652         struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
 653         struct isci_host *ihost = ha->lldd_ha;
 654
 655         if (test_bit(IHOST_START_PENDING, &ihost->flags))
 656                 return 0;
 657
 658         sas_drain_work(ha);
 659
 660         dev_dbg(&ihost->pdev->dev,
 661                 "%s: ihost->status = %d, time = %ld\n",
 662                  __func__, isci_host_get_state(ihost), time);
 663
 664         return 1;
 665
 666 }
 667
 668 /**
 669  * sci_controller_get_suggested_start_timeout() - This method returns the
 670  *    suggested sci_controller_start() timeout amount.  The user is free to
 671  *    use any timeout value, but this method provides the suggested minimum
 672  *    start timeout value.  The returned value is based upon empirical
 673  *    information determined as a result of interoperability testing.
 674  * @controller: the handle to the controller object for which to return the
 675  *    suggested start timeout.
 676  *
 677  * This method returns the number of milliseconds for the suggested start
 678  * operation timeout.
 679  */
 680 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
 681 {
 682         /* Validate the user supplied parameters. */
 683         if (!ihost)
 684                 return 0;
 685
 686         /*
 687          * The suggested minimum timeout value for a controller start operation:
 688          *
 689          *     Signature FIS Timeout
 690          *   + Phy Start Timeout
 691          *   + Number of Phy Spin Up Intervals
 692          *   ---------------------------------
 693          *   Number of milliseconds for the controller start operation.
 694          *
 695          * NOTE: The number of phy spin up intervals will be equivalent
 696          *       to the number of phys divided by the number phys allowed
 697          *       per interval - 1 (once OEM parameters are supported).
 698          *       Currently we assume only 1 phy per interval. */
 699
 700         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
 701                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 702                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
 703 }
 704
 705 static void sci_controller_enable_interrupts(struct isci_host *ihost)
 706 {
 707         BUG_ON(ihost->smu_registers == NULL);
 708         writel(0, &ihost->smu_registers->interrupt_mask);
 709 }
 710
 711 void sci_controller_disable_interrupts(struct isci_host *ihost)
 712 {
 713         BUG_ON(ihost->smu_registers == NULL);
 714         writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
 715 }
 716
 717 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
 718 {
 719         u32 port_task_scheduler_value;
 720
 721         port_task_scheduler_value =
 722                 readl(&ihost->scu_registers->peg0.ptsg.control);
 723         port_task_scheduler_value |=
 724                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
 725                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 726         writel(port_task_scheduler_value,
 727                &ihost->scu_registers->peg0.ptsg.control);
 728 }
 729
 730 static void sci_controller_assign_task_entries(struct isci_host *ihost)
 731 {
 732         u32 task_assignment;
 733
 734         /*
 735          * Assign all the TCs to function 0
 736          * TODO: Do we actually need to read this register to write it back?
 737          */
 738
 739         task_assignment =
 740                 readl(&ihost->smu_registers->task_context_assignment[0]);
 741
 742         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
 743                 (SMU_TCA_GEN_VAL(ENDING,  ihost->task_context_entries - 1)) |
 744                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
 745
 746         writel(task_assignment,
 747                 &ihost->smu_registers->task_context_assignment[0]);
 748
 749 }
 750
 751 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
 752 {
 753         u32 index;
 754         u32 completion_queue_control_value;
 755         u32 completion_queue_get_value;
 756         u32 completion_queue_put_value;
 757
 758         ihost->completion_queue_get = 0;
 759
 760         completion_queue_control_value =
 761                 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
 762                  SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
 763
 764         writel(completion_queue_control_value,
 765                &ihost->smu_registers->completion_queue_control);
 766
 767
 768         /* Set the completion queue get pointer and enable the queue */
 769         completion_queue_get_value = (
 770                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 771                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 772                 | (SMU_CQGR_GEN_BIT(ENABLE))
 773                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 774                 );
 775
 776         writel(completion_queue_get_value,
 777                &ihost->smu_registers->completion_queue_get);
 778
 779         /* Set the completion queue put pointer */
 780         completion_queue_put_value = (
 781                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 782                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 783                 );
 784
 785         writel(completion_queue_put_value,
 786                &ihost->smu_registers->completion_queue_put);
 787
 788         /* Initialize the cycle bit of the completion queue entries */
 789         for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
 790                 /*
 791                  * If get.cycle_bit != completion_queue.cycle_bit
 792                  * its not a valid completion queue entry
 793                  * so at system start all entries are invalid */
 794                 ihost->completion_queue[index] = 0x80000000;
 795         }
 796 }
 797
 798 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
 799 {
 800         u32 frame_queue_control_value;
 801         u32 frame_queue_get_value;
 802         u32 frame_queue_put_value;
 803
 804         /* Write the queue size */
 805         frame_queue_control_value =
 806                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
 807
 808         writel(frame_queue_control_value,
 809                &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
 810
 811         /* Setup the get pointer for the unsolicited frame queue */
 812         frame_queue_get_value = (
 813                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 814                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 815                 );
 816
 817         writel(frame_queue_get_value,
 818                &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
 819         /* Setup the put pointer for the unsolicited frame queue */
 820         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 821         writel(frame_queue_put_value,
 822                &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
 823 }
 824
 825 static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
 826 {
 827         if (ihost->sm.current_state_id == SCIC_STARTING) {
 828                 /*
 829                  * We move into the ready state, because some of the phys/ports
 830                  * may be up and operational.
 831                  */
 832                 sci_change_state(&ihost->sm, SCIC_READY);
 833
 834                 isci_host_start_complete(ihost, status);
 835         }
 836 }
 837
 838 static bool is_phy_starting(struct isci_phy *iphy)
 839 {
 840         enum sci_phy_states state;
 841
 842         state = iphy->sm.current_state_id;
 843         switch (state) {
 844         case SCI_PHY_STARTING:
 845         case SCI_PHY_SUB_INITIAL:
 846         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 847         case SCI_PHY_SUB_AWAIT_IAF_UF:
 848         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 849         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 850         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 851         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 852         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 853         case SCI_PHY_SUB_FINAL:
 854                 return true;
 855         default:
 856                 return false;
 857         }
 858 }
 859
 860 /**
 861  * sci_controller_start_next_phy - start phy
 862  * @scic: controller
 863  *
 864  * If all the phys have been started, then attempt to transition the
 865  * controller to the READY state and inform the user
 866  * (sci_cb_controller_start_complete()).
 867  */
 868 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
 869 {
 870         struct sci_oem_params *oem = &ihost->oem_parameters;
 871         struct isci_phy *iphy;
 872         enum sci_status status;
 873
 874         status = SCI_SUCCESS;
 875
 876         if (ihost->phy_startup_timer_pending)
 877                 return status;
 878
 879         if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
 880                 bool is_controller_start_complete = true;
 881                 u32 state;
 882                 u8 index;
 883
 884                 for (index = 0; index < SCI_MAX_PHYS; index++) {
 885                         iphy = &ihost->phys[index];
 886                         state = iphy->sm.current_state_id;
 887
 888                         if (!phy_get_non_dummy_port(iphy))
 889                                 continue;
 890
 891                         /* The controller start operation is complete iff:
 892                          * - all links have been given an opportunity to start
 893                          * - have no indication of a connected device
 894                          * - have an indication of a connected device and it has
 895                          *   finished the link training process.
 896                          */
 897                         if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
 898                             (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
 899                             (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
 900                             (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) {
 901                                 is_controller_start_complete = false;
 902                                 break;
 903                         }
 904                 }
 905
 906                 /*
 907                  * The controller has successfully finished the start process.
 908                  * Inform the SCI Core user and transition to the READY state. */
 909                 if (is_controller_start_complete == true) {
 910                         sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
 911                         sci_del_timer(&ihost->phy_timer);
 912                         ihost->phy_startup_timer_pending = false;
 913                 }
 914         } else {
 915                 iphy = &ihost->phys[ihost->next_phy_to_start];
 916
 917                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 918                         if (phy_get_non_dummy_port(iphy) == NULL) {
 919                                 ihost->next_phy_to_start++;
 920
 921                                 /* Caution recursion ahead be forwarned
 922                                  *
 923                                  * The PHY was never added to a PORT in MPC mode
 924                                  * so start the next phy in sequence This phy
 925                                  * will never go link up and will not draw power
 926                                  * the OEM parameters either configured the phy
 927                                  * incorrectly for the PORT or it was never
 928                                  * assigned to a PORT
 929                                  */
 930                                 return sci_controller_start_next_phy(ihost);
 931                         }
 932                 }
 933
 934                 status = sci_phy_start(iphy);
 935
 936                 if (status == SCI_SUCCESS) {
 937                         sci_mod_timer(&ihost->phy_timer,
 938                                       SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
 939                         ihost->phy_startup_timer_pending = true;
 940                 } else {
 941                         dev_warn(&ihost->pdev->dev,
 942                                  "%s: Controller stop operation failed "
 943                                  "to stop phy %d because of status "
 944                                  "%d.\n",
 945                                  __func__,
 946                                  ihost->phys[ihost->next_phy_to_start].phy_index,
 947                                  status);
 948                 }
 949
 950                 ihost->next_phy_to_start++;
 951         }
 952
 953         return status;
 954 }
 955
 956 static void phy_startup_timeout(unsigned long data)
 957 {
 958         struct sci_timer *tmr = (struct sci_timer *)data;
 959         struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
 960         unsigned long flags;
 961         enum sci_status status;
 962
 963         spin_lock_irqsave(&ihost->scic_lock, flags);
 964
 965         if (tmr->cancel)
 966                 goto done;
 967
 968         ihost->phy_startup_timer_pending = false;
 969
 970         do {
 971                 status = sci_controller_start_next_phy(ihost);
 972         } while (status != SCI_SUCCESS);
 973
 974 done:
 975         spin_unlock_irqrestore(&ihost->scic_lock, flags);
 976 }
 977
 978 static u16 isci_tci_active(struct isci_host *ihost)
 979 {
 980         return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
 981 }
 982
 983 static enum sci_status sci_controller_start(struct isci_host *ihost,
 984                                              u32 timeout)
 985 {
 986         enum sci_status result;
 987         u16 index;
 988
 989         if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
 990                 dev_warn(&ihost->pdev->dev,
 991                          "SCIC Controller start operation requested in "
 992                          "invalid state\n");
 993                 return SCI_FAILURE_INVALID_STATE;
 994         }
 995
 996         /* Build the TCi free pool */
 997         BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
 998         ihost->tci_head = 0;
 999         ihost->tci_tail = 0;
1000         for (index = 0; index < ihost->task_context_entries; index++)
1001                 isci_tci_free(ihost, index);
1002
1003         /* Build the RNi free pool */
1004         sci_remote_node_table_initialize(&ihost->available_remote_nodes,
1005                                          ihost->remote_node_entries);
1006
1007         /*
1008          * Before anything else lets make sure we will not be
1009          * interrupted by the hardware.
1010          */
1011         sci_controller_disable_interrupts(ihost);
1012
1013         /* Enable the port task scheduler */
1014         sci_controller_enable_port_task_scheduler(ihost);
1015
1016         /* Assign all the task entries to ihost physical function */
1017         sci_controller_assign_task_entries(ihost);
1018
1019         /* Now initialize the completion queue */
1020         sci_controller_initialize_completion_queue(ihost);
1021
1022         /* Initialize the unsolicited frame queue for use */
1023         sci_controller_initialize_unsolicited_frame_queue(ihost);
1024
1025         /* Start all of the ports on this controller */
1026         for (index = 0; index < ihost->logical_port_entries; index++) {
1027                 struct isci_port *iport = &ihost->ports[index];
1028
1029                 result = sci_port_start(iport);
1030                 if (result)
1031                         return result;
1032         }
1033
1034         sci_controller_start_next_phy(ihost);
1035
1036         sci_mod_timer(&ihost->timer, timeout);
1037
1038         sci_change_state(&ihost->sm, SCIC_STARTING);
1039
1040         return SCI_SUCCESS;
1041 }
1042
1043 void isci_host_scan_start(struct Scsi_Host *shost)
1044 {
1045         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1046         unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1047
1048         set_bit(IHOST_START_PENDING, &ihost->flags);
1049
1050         spin_lock_irq(&ihost->scic_lock);
1051         sci_controller_start(ihost, tmo);
1052         sci_controller_enable_interrupts(ihost);
1053         spin_unlock_irq(&ihost->scic_lock);
1054 }
1055
1056 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1057 {
1058         isci_host_change_state(ihost, isci_stopped);
1059         sci_controller_disable_interrupts(ihost);
1060         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1061         wake_up(&ihost->eventq);
1062 }
1063
1064 static void sci_controller_completion_handler(struct isci_host *ihost)
1065 {
1066         /* Empty out the completion queue */
1067         if (sci_controller_completion_queue_has_entries(ihost))
1068                 sci_controller_process_completions(ihost);
1069
1070         /* Clear the interrupt and enable all interrupts again */
1071         writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1072         /* Could we write the value of SMU_ISR_COMPLETION? */
1073         writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1074         writel(0, &ihost->smu_registers->interrupt_mask);
1075 }
1076
1077 /**
1078  * isci_host_completion_routine() - This function is the delayed service
1079  *    routine that calls the sci core library's completion handler. It's
1080  *    scheduled as a tasklet from the interrupt service routine when interrupts
1081  *    in use, or set as the timeout function in polled mode.
1082  * @data: This parameter specifies the ISCI host object
1083  *
1084  */
1085 static void isci_host_completion_routine(unsigned long data)
1086 {
1087         struct isci_host *ihost = (struct isci_host *)data;
1088         struct list_head    completed_request_list;
1089         struct list_head    errored_request_list;
1090         struct list_head    *current_position;
1091         struct list_head    *next_position;
1092         struct isci_request *request;
1093         struct isci_request *next_request;
1094         struct sas_task     *task;
1095         u16 active;
1096
1097         INIT_LIST_HEAD(&completed_request_list);
1098         INIT_LIST_HEAD(&errored_request_list);
1099
1100         spin_lock_irq(&ihost->scic_lock);
1101
1102         sci_controller_completion_handler(ihost);
1103
1104         /* Take the lists of completed I/Os from the host. */
1105
1106         list_splice_init(&ihost->requests_to_complete,
1107                          &completed_request_list);
1108
1109         /* Take the list of errored I/Os from the host. */
1110         list_splice_init(&ihost->requests_to_errorback,
1111                          &errored_request_list);
1112
1113         spin_unlock_irq(&ihost->scic_lock);
1114
1115         /* Process any completions in the lists. */
1116         list_for_each_safe(current_position, next_position,
1117                            &completed_request_list) {
1118
1119                 request = list_entry(current_position, struct isci_request,
1120                                      completed_node);
1121                 task = isci_request_access_task(request);
1122
1123                 /* Normal notification (task_done) */
1124                 dev_dbg(&ihost->pdev->dev,
1125                         "%s: Normal - request/task = %p/%p\n",
1126                         __func__,
1127                         request,
1128                         task);
1129
1130                 /* Return the task to libsas */
1131                 if (task != NULL) {
1132
1133                         task->lldd_task = NULL;
1134                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1135
1136                                 /* If the task is already in the abort path,
1137                                 * the task_done callback cannot be called.
1138                                 */
1139                                 task->task_done(task);
1140                         }
1141                 }
1142
1143                 spin_lock_irq(&ihost->scic_lock);
1144                 isci_free_tag(ihost, request->io_tag);
1145                 spin_unlock_irq(&ihost->scic_lock);
1146         }
1147         list_for_each_entry_safe(request, next_request, &errored_request_list,
1148                                  completed_node) {
1149
1150                 task = isci_request_access_task(request);
1151
1152                 /* Use sas_task_abort */
1153                 dev_warn(&ihost->pdev->dev,
1154                          "%s: Error - request/task = %p/%p\n",
1155                          __func__,
1156                          request,
1157                          task);
1158
1159                 if (task != NULL) {
1160
1161                         /* Put the task into the abort path if it's not there
1162                          * already.
1163                          */
1164                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1165                                 sas_task_abort(task);
1166
1167                 } else {
1168                         /* This is a case where the request has completed with a
1169                          * status such that it needed further target servicing,
1170                          * but the sas_task reference has already been removed
1171                          * from the request.  Since it was errored, it was not
1172                          * being aborted, so there is nothing to do except free
1173                          * it.
1174                          */
1175
1176                         spin_lock_irq(&ihost->scic_lock);
1177                         /* Remove the request from the remote device's list
1178                         * of pending requests.
1179                         */
1180                         list_del_init(&request->dev_node);
1181                         isci_free_tag(ihost, request->io_tag);
1182                         spin_unlock_irq(&ihost->scic_lock);
1183                 }
1184         }
1185
1186         /* the coalesence timeout doubles at each encoding step, so
1187          * update it based on the ilog2 value of the outstanding requests
1188          */
1189         active = isci_tci_active(ihost);
1190         writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1191                SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1192                &ihost->smu_registers->interrupt_coalesce_control);
1193 }
1194
1195 /**
1196  * sci_controller_stop() - This method will stop an individual controller
1197  *    object.This method will invoke the associated user callback upon
1198  *    completion.  The completion callback is called when the following
1199  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1200  *    controller has been quiesced. This method will ensure that all IO
1201  *    requests are quiesced, phys are stopped, and all additional operation by
1202  *    the hardware is halted.
1203  * @controller: the handle to the controller object to stop.
1204  * @timeout: This parameter specifies the number of milliseconds in which the
1205  *    stop operation should complete.
1206  *
1207  * The controller must be in the STARTED or STOPPED state. Indicate if the
1208  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1209  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1210  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1211  * controller is not either in the STARTED or STOPPED states.
1212  */
1213 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1214 {
1215         if (ihost->sm.current_state_id != SCIC_READY) {
1216                 dev_warn(&ihost->pdev->dev,
1217                          "SCIC Controller stop operation requested in "
1218                          "invalid state\n");
1219                 return SCI_FAILURE_INVALID_STATE;
1220         }
1221
1222         sci_mod_timer(&ihost->timer, timeout);
1223         sci_change_state(&ihost->sm, SCIC_STOPPING);
1224         return SCI_SUCCESS;
1225 }
1226
1227 /**
1228  * sci_controller_reset() - This method will reset the supplied core
1229  *    controller regardless of the state of said controller.  This operation is
1230  *    considered destructive.  In other words, all current operations are wiped
1231  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1232  *    requests are not aborted or completed at the actual remote device.
1233  * @controller: the handle to the controller object to reset.
1234  *
1235  * Indicate if the controller reset method succeeded or failed in some way.
1236  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1237  * the controller reset operation is unable to complete.
1238  */
1239 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1240 {
1241         switch (ihost->sm.current_state_id) {
1242         case SCIC_RESET:
1243         case SCIC_READY:
1244         case SCIC_STOPPED:
1245         case SCIC_FAILED:
1246                 /*
1247                  * The reset operation is not a graceful cleanup, just
1248                  * perform the state transition.
1249                  */
1250                 sci_change_state(&ihost->sm, SCIC_RESETTING);
1251                 return SCI_SUCCESS;
1252         default:
1253                 dev_warn(&ihost->pdev->dev,
1254                          "SCIC Controller reset operation requested in "
1255                          "invalid state\n");
1256                 return SCI_FAILURE_INVALID_STATE;
1257         }
1258 }
1259
1260 void isci_host_deinit(struct isci_host *ihost)
1261 {
1262         int i;
1263
1264         /* disable output data selects */
1265         for (i = 0; i < isci_gpio_count(ihost); i++)
1266                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1267
1268         isci_host_change_state(ihost, isci_stopping);
1269         for (i = 0; i < SCI_MAX_PORTS; i++) {
1270                 struct isci_port *iport = &ihost->ports[i];
1271                 struct isci_remote_device *idev, *d;
1272
1273                 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1274                         if (test_bit(IDEV_ALLOCATED, &idev->flags))
1275                                 isci_remote_device_stop(ihost, idev);
1276                 }
1277         }
1278
1279         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1280
1281         spin_lock_irq(&ihost->scic_lock);
1282         sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1283         spin_unlock_irq(&ihost->scic_lock);
1284
1285         wait_for_stop(ihost);
1286
1287         /* disable sgpio: where the above wait should give time for the
1288          * enclosure to sample the gpios going inactive
1289          */
1290         writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1291
1292         sci_controller_reset(ihost);
1293
1294         /* Cancel any/all outstanding port timers */
1295         for (i = 0; i < ihost->logical_port_entries; i++) {
1296                 struct isci_port *iport = &ihost->ports[i];
1297                 del_timer_sync(&iport->timer.timer);
1298         }
1299
1300         /* Cancel any/all outstanding phy timers */
1301         for (i = 0; i < SCI_MAX_PHYS; i++) {
1302                 struct isci_phy *iphy = &ihost->phys[i];
1303                 del_timer_sync(&iphy->sata_timer.timer);
1304         }
1305
1306         del_timer_sync(&ihost->port_agent.timer.timer);
1307
1308         del_timer_sync(&ihost->power_control.timer.timer);
1309
1310         del_timer_sync(&ihost->timer.timer);
1311
1312         del_timer_sync(&ihost->phy_timer.timer);
1313 }
1314
1315 static void __iomem *scu_base(struct isci_host *isci_host)
1316 {
1317         struct pci_dev *pdev = isci_host->pdev;
1318         int id = isci_host->id;
1319
1320         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1321 }
1322
1323 static void __iomem *smu_base(struct isci_host *isci_host)
1324 {
1325         struct pci_dev *pdev = isci_host->pdev;
1326         int id = isci_host->id;
1327
1328         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1329 }
1330
1331 static void isci_user_parameters_get(struct sci_user_parameters *u)
1332 {
1333         int i;
1334
1335         for (i = 0; i < SCI_MAX_PHYS; i++) {
1336                 struct sci_phy_user_params *u_phy = &u->phys[i];
1337
1338                 u_phy->max_speed_generation = phy_gen;
1339
1340                 /* we are not exporting these for now */
1341                 u_phy->align_insertion_frequency = 0x7f;
1342                 u_phy->in_connection_align_insertion_frequency = 0xff;
1343                 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1344         }
1345
1346         u->stp_inactivity_timeout = stp_inactive_to;
1347         u->ssp_inactivity_timeout = ssp_inactive_to;
1348         u->stp_max_occupancy_timeout = stp_max_occ_to;
1349         u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1350         u->no_outbound_task_timeout = no_outbound_task_to;
1351         u->max_concurr_spinup = max_concurr_spinup;
1352 }
1353
1354 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1355 {
1356         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1357
1358         sci_change_state(&ihost->sm, SCIC_RESET);
1359 }
1360
1361 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1362 {
1363         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1364
1365         sci_del_timer(&ihost->timer);
1366 }
1367
1368 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1369 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1370 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1371 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1372 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1373 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1374
1375 /**
1376  * sci_controller_set_interrupt_coalescence() - This method allows the user to
1377  *    configure the interrupt coalescence.
1378  * @controller: This parameter represents the handle to the controller object
1379  *    for which its interrupt coalesce register is overridden.
1380  * @coalesce_number: Used to control the number of entries in the Completion
1381  *    Queue before an interrupt is generated. If the number of entries exceed
1382  *    this number, an interrupt will be generated. The valid range of the input
1383  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1384  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1385  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1386  *    interrupt coalescing timeout.
1387  *
1388  * Indicate if the user successfully set the interrupt coalesce parameters.
1389  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1390  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1391  */
1392 static enum sci_status
1393 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1394                                          u32 coalesce_number,
1395                                          u32 coalesce_timeout)
1396 {
1397         u8 timeout_encode = 0;
1398         u32 min = 0;
1399         u32 max = 0;
1400
1401         /* Check if the input parameters fall in the range. */
1402         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1403                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1404
1405         /*
1406          *  Defined encoding for interrupt coalescing timeout:
1407          *              Value   Min      Max     Units
1408          *              -----   ---      ---     -----
1409          *              0       -        -       Disabled
1410          *              1       13.3     20.0    ns
1411          *              2       26.7     40.0
1412          *              3       53.3     80.0
1413          *              4       106.7    160.0
1414          *              5       213.3    320.0
1415          *              6       426.7    640.0
1416          *              7       853.3    1280.0
1417          *              8       1.7      2.6     us
1418          *              9       3.4      5.1
1419          *              10      6.8      10.2
1420          *              11      13.7     20.5
1421          *              12      27.3     41.0
1422          *              13      54.6     81.9
1423          *              14      109.2    163.8
1424          *              15      218.5    327.7
1425          *              16      436.9    655.4
1426          *              17      873.8    1310.7
1427          *              18      1.7      2.6     ms
1428          *              19      3.5      5.2
1429          *              20      7.0      10.5
1430          *              21      14.0     21.0
1431          *              22      28.0     41.9
1432          *              23      55.9     83.9
1433          *              24      111.8    167.8
1434          *              25      223.7    335.5
1435          *              26      447.4    671.1
1436          *              27      894.8    1342.2
1437          *              28      1.8      2.7     s
1438          *              Others Undefined */
1439
1440         /*
1441          * Use the table above to decide the encode of interrupt coalescing timeout
1442          * value for register writing. */
1443         if (coalesce_timeout == 0)
1444                 timeout_encode = 0;
1445         else{
1446                 /* make the timeout value in unit of (10 ns). */
1447                 coalesce_timeout = coalesce_timeout * 100;
1448                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1449                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1450
1451                 /* get the encode of timeout for register writing. */
1452                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1453                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1454                       timeout_encode++) {
1455                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1456                                 break;
1457                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1458                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1459                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1460                                         break;
1461                                 else{
1462                                         timeout_encode++;
1463                                         break;
1464                                 }
1465                         } else {
1466                                 max = max * 2;
1467                                 min = min * 2;
1468                         }
1469                 }
1470
1471                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1472                         /* the value is out of range. */
1473                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1474         }
1475
1476         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1477                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1478                &ihost->smu_registers->interrupt_coalesce_control);
1479
1480
1481         ihost->interrupt_coalesce_number = (u16)coalesce_number;
1482         ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1483
1484         return SCI_SUCCESS;
1485 }
1486
1487
1488 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1489 {
1490         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1491         u32 val;
1492
1493         /* enable clock gating for power control of the scu unit */
1494         val = readl(&ihost->smu_registers->clock_gating_control);
1495         val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
1496                  SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
1497                  SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
1498         val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
1499         writel(val, &ihost->smu_registers->clock_gating_control);
1500
1501         /* set the default interrupt coalescence number and timeout value. */
1502         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1503 }
1504
1505 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1506 {
1507         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1508
1509         /* disable interrupt coalescence. */
1510         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1511 }
1512
1513 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1514 {
1515         u32 index;
1516         enum sci_status status;
1517         enum sci_status phy_status;
1518
1519         status = SCI_SUCCESS;
1520
1521         for (index = 0; index < SCI_MAX_PHYS; index++) {
1522                 phy_status = sci_phy_stop(&ihost->phys[index]);
1523
1524                 if (phy_status != SCI_SUCCESS &&
1525                     phy_status != SCI_FAILURE_INVALID_STATE) {
1526                         status = SCI_FAILURE;
1527
1528                         dev_warn(&ihost->pdev->dev,
1529                                  "%s: Controller stop operation failed to stop "
1530                                  "phy %d because of status %d.\n",
1531                                  __func__,
1532                                  ihost->phys[index].phy_index, phy_status);
1533                 }
1534         }
1535
1536         return status;
1537 }
1538
1539 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1540 {
1541         u32 index;
1542         enum sci_status port_status;
1543         enum sci_status status = SCI_SUCCESS;
1544
1545         for (index = 0; index < ihost->logical_port_entries; index++) {
1546                 struct isci_port *iport = &ihost->ports[index];
1547
1548                 port_status = sci_port_stop(iport);
1549
1550                 if ((port_status != SCI_SUCCESS) &&
1551                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1552                         status = SCI_FAILURE;
1553
1554                         dev_warn(&ihost->pdev->dev,
1555                                  "%s: Controller stop operation failed to "
1556                                  "stop port %d because of status %d.\n",
1557                                  __func__,
1558                                  iport->logical_port_index,
1559                                  port_status);
1560                 }
1561         }
1562
1563         return status;
1564 }
1565
1566 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1567 {
1568         u32 index;
1569         enum sci_status status;
1570         enum sci_status device_status;
1571
1572         status = SCI_SUCCESS;
1573
1574         for (index = 0; index < ihost->remote_node_entries; index++) {
1575                 if (ihost->device_table[index] != NULL) {
1576                         /* / @todo What timeout value do we want to provide to this request? */
1577                         device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1578
1579                         if ((device_status != SCI_SUCCESS) &&
1580                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1581                                 dev_warn(&ihost->pdev->dev,
1582                                          "%s: Controller stop operation failed "
1583                                          "to stop device 0x%p because of "
1584                                          "status %d.\n",
1585                                          __func__,
1586                                          ihost->device_table[index], device_status);
1587                         }
1588                 }
1589         }
1590
1591         return status;
1592 }
1593
1594 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1595 {
1596         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1597
1598         /* Stop all of the components for this controller */
1599         sci_controller_stop_phys(ihost);
1600         sci_controller_stop_ports(ihost);
1601         sci_controller_stop_devices(ihost);
1602 }
1603
1604 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1605 {
1606         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1607
1608         sci_del_timer(&ihost->timer);
1609 }
1610
1611 static void sci_controller_reset_hardware(struct isci_host *ihost)
1612 {
1613         /* Disable interrupts so we dont take any spurious interrupts */
1614         sci_controller_disable_interrupts(ihost);
1615
1616         /* Reset the SCU */
1617         writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1618
1619         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1620         udelay(1000);
1621
1622         /* The write to the CQGR clears the CQP */
1623         writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1624
1625         /* The write to the UFQGP clears the UFQPR */
1626         writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1627 }
1628
1629 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1630 {
1631         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1632
1633         sci_controller_reset_hardware(ihost);
1634         sci_change_state(&ihost->sm, SCIC_RESET);
1635 }
1636
1637 static const struct sci_base_state sci_controller_state_table[] = {
1638         [SCIC_INITIAL] = {
1639                 .enter_state = sci_controller_initial_state_enter,
1640         },
1641         [SCIC_RESET] = {},
1642         [SCIC_INITIALIZING] = {},
1643         [SCIC_INITIALIZED] = {},
1644         [SCIC_STARTING] = {
1645                 .exit_state  = sci_controller_starting_state_exit,
1646         },
1647         [SCIC_READY] = {
1648                 .enter_state = sci_controller_ready_state_enter,
1649                 .exit_state  = sci_controller_ready_state_exit,
1650         },
1651         [SCIC_RESETTING] = {
1652                 .enter_state = sci_controller_resetting_state_enter,
1653         },
1654         [SCIC_STOPPING] = {
1655                 .enter_state = sci_controller_stopping_state_enter,
1656                 .exit_state = sci_controller_stopping_state_exit,
1657         },
1658         [SCIC_STOPPED] = {},
1659         [SCIC_FAILED] = {}
1660 };
1661
1662 static void sci_controller_set_default_config_parameters(struct isci_host *ihost)
1663 {
1664         /* these defaults are overridden by the platform / firmware */
1665         u16 index;
1666
1667         /* Default to APC mode. */
1668         ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1669
1670         /* Default to APC mode. */
1671         ihost->oem_parameters.controller.max_concurr_spin_up = 1;
1672
1673         /* Default to no SSC operation. */
1674         ihost->oem_parameters.controller.do_enable_ssc = false;
1675
1676         /* Default to short cables on all phys. */
1677         ihost->oem_parameters.controller.cable_selection_mask = 0;
1678
1679         /* Initialize all of the port parameter information to narrow ports. */
1680         for (index = 0; index < SCI_MAX_PORTS; index++) {
1681                 ihost->oem_parameters.ports[index].phy_mask = 0;
1682         }
1683
1684         /* Initialize all of the phy parameter information. */
1685         for (index = 0; index < SCI_MAX_PHYS; index++) {
1686                 /* Default to 3G (i.e. Gen 2). */
1687                 ihost->user_parameters.phys[index].max_speed_generation =
1688                         SCIC_SDS_PARM_GEN2_SPEED;
1689
1690                 /* the frequencies cannot be 0 */
1691                 ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f;
1692                 ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff;
1693                 ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1694
1695                 /*
1696                  * Previous Vitesse based expanders had a arbitration issue that
1697                  * is worked around by having the upper 32-bits of SAS address
1698                  * with a value greater then the Vitesse company identifier.
1699                  * Hence, usage of 0x5FCFFFFF. */
1700                 ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id;
1701                 ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF;
1702         }
1703
1704         ihost->user_parameters.stp_inactivity_timeout = 5;
1705         ihost->user_parameters.ssp_inactivity_timeout = 5;
1706         ihost->user_parameters.stp_max_occupancy_timeout = 5;
1707         ihost->user_parameters.ssp_max_occupancy_timeout = 20;
1708         ihost->user_parameters.no_outbound_task_timeout = 2;
1709 }
1710
1711 static void controller_timeout(unsigned long data)
1712 {
1713         struct sci_timer *tmr = (struct sci_timer *)data;
1714         struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1715         struct sci_base_state_machine *sm = &ihost->sm;
1716         unsigned long flags;
1717
1718         spin_lock_irqsave(&ihost->scic_lock, flags);
1719
1720         if (tmr->cancel)
1721                 goto done;
1722
1723         if (sm->current_state_id == SCIC_STARTING)
1724                 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1725         else if (sm->current_state_id == SCIC_STOPPING) {
1726                 sci_change_state(sm, SCIC_FAILED);
1727                 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1728         } else  /* / @todo Now what do we want to do in this case? */
1729                 dev_err(&ihost->pdev->dev,
1730                         "%s: Controller timer fired when controller was not "
1731                         "in a state being timed.\n",
1732                         __func__);
1733
1734 done:
1735         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1736 }
1737
1738 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1739                                                 void __iomem *scu_base,
1740                                                 void __iomem *smu_base)
1741 {
1742         u8 i;
1743
1744         sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1745
1746         ihost->scu_registers = scu_base;
1747         ihost->smu_registers = smu_base;
1748
1749         sci_port_configuration_agent_construct(&ihost->port_agent);
1750
1751         /* Construct the ports for this controller */
1752         for (i = 0; i < SCI_MAX_PORTS; i++)
1753                 sci_port_construct(&ihost->ports[i], i, ihost);
1754         sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1755
1756         /* Construct the phys for this controller */
1757         for (i = 0; i < SCI_MAX_PHYS; i++) {
1758                 /* Add all the PHYs to the dummy port */
1759                 sci_phy_construct(&ihost->phys[i],
1760                                   &ihost->ports[SCI_MAX_PORTS], i);
1761         }
1762
1763         ihost->invalid_phy_mask = 0;
1764
1765         sci_init_timer(&ihost->timer, controller_timeout);
1766
1767         /* Initialize the User and OEM parameters to default values. */
1768         sci_controller_set_default_config_parameters(ihost);
1769
1770         return sci_controller_reset(ihost);
1771 }
1772
1773 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1774 {
1775         int i;
1776
1777         for (i = 0; i < SCI_MAX_PORTS; i++)
1778                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1779                         return -EINVAL;
1780
1781         for (i = 0; i < SCI_MAX_PHYS; i++)
1782                 if (oem->phys[i].sas_address.high == 0 &&
1783                     oem->phys[i].sas_address.low == 0)
1784                         return -EINVAL;
1785
1786         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1787                 for (i = 0; i < SCI_MAX_PHYS; i++)
1788                         if (oem->ports[i].phy_mask != 0)
1789                                 return -EINVAL;
1790         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1791                 u8 phy_mask = 0;
1792
1793                 for (i = 0; i < SCI_MAX_PHYS; i++)
1794                         phy_mask |= oem->ports[i].phy_mask;
1795
1796                 if (phy_mask == 0)
1797                         return -EINVAL;
1798         } else
1799                 return -EINVAL;
1800
1801         if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1802             oem->controller.max_concurr_spin_up < 1)
1803                 return -EINVAL;
1804
1805         if (oem->controller.do_enable_ssc) {
1806                 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1807                         return -EINVAL;
1808
1809                 if (version >= ISCI_ROM_VER_1_1) {
1810                         u8 test = oem->controller.ssc_sata_tx_spread_level;
1811
1812                         switch (test) {
1813                         case 0:
1814                         case 2:
1815                         case 3:
1816                         case 6:
1817                         case 7:
1818                                 break;
1819                         default:
1820                                 return -EINVAL;
1821                         }
1822
1823                         test = oem->controller.ssc_sas_tx_spread_level;
1824                         if (oem->controller.ssc_sas_tx_type == 0) {
1825                                 switch (test) {
1826                                 case 0:
1827                                 case 2:
1828                                 case 3:
1829                                         break;
1830                                 default:
1831                                         return -EINVAL;
1832                                 }
1833                         } else if (oem->controller.ssc_sas_tx_type == 1) {
1834                                 switch (test) {
1835                                 case 0:
1836                                 case 3:
1837                                 case 6:
1838                                         break;
1839                                 default:
1840                                         return -EINVAL;
1841                                 }
1842                         }
1843                 }
1844         }
1845
1846         return 0;
1847 }
1848
1849 static enum sci_status sci_oem_parameters_set(struct isci_host *ihost)
1850 {
1851         u32 state = ihost->sm.current_state_id;
1852         struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
1853
1854         if (state == SCIC_RESET ||
1855             state == SCIC_INITIALIZING ||
1856             state == SCIC_INITIALIZED) {
1857                 u8 oem_version = pci_info->orom ? pci_info->orom->hdr.version :
1858                         ISCI_ROM_VER_1_0;
1859
1860                 if (sci_oem_parameters_validate(&ihost->oem_parameters,
1861                                                 oem_version))
1862                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1863
1864                 return SCI_SUCCESS;
1865         }
1866
1867         return SCI_FAILURE_INVALID_STATE;
1868 }
1869
1870 static u8 max_spin_up(struct isci_host *ihost)
1871 {
1872         if (ihost->user_parameters.max_concurr_spinup)
1873                 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1874                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1875         else
1876                 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1877                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1878 }
1879
1880 static void power_control_timeout(unsigned long data)
1881 {
1882         struct sci_timer *tmr = (struct sci_timer *)data;
1883         struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1884         struct isci_phy *iphy;
1885         unsigned long flags;
1886         u8 i;
1887
1888         spin_lock_irqsave(&ihost->scic_lock, flags);
1889
1890         if (tmr->cancel)
1891                 goto done;
1892
1893         ihost->power_control.phys_granted_power = 0;
1894
1895         if (ihost->power_control.phys_waiting == 0) {
1896                 ihost->power_control.timer_started = false;
1897                 goto done;
1898         }
1899
1900         for (i = 0; i < SCI_MAX_PHYS; i++) {
1901
1902                 if (ihost->power_control.phys_waiting == 0)
1903                         break;
1904
1905                 iphy = ihost->power_control.requesters[i];
1906                 if (iphy == NULL)
1907                         continue;
1908
1909                 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1910                         break;
1911
1912                 ihost->power_control.requesters[i] = NULL;
1913                 ihost->power_control.phys_waiting--;
1914                 ihost->power_control.phys_granted_power++;
1915                 sci_phy_consume_power_handler(iphy);
1916
1917                 if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1918                         u8 j;
1919
1920                         for (j = 0; j < SCI_MAX_PHYS; j++) {
1921                                 struct isci_phy *requester = ihost->power_control.requesters[j];
1922
1923                                 /*
1924                                  * Search the power_control queue to see if there are other phys
1925                                  * attached to the same remote device. If found, take all of
1926                                  * them out of await_sas_power state.
1927                                  */
1928                                 if (requester != NULL && requester != iphy) {
1929                                         u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1930                                                           iphy->frame_rcvd.iaf.sas_addr,
1931                                                           sizeof(requester->frame_rcvd.iaf.sas_addr));
1932
1933                                         if (other == 0) {
1934                                                 ihost->power_control.requesters[j] = NULL;
1935                                                 ihost->power_control.phys_waiting--;
1936                                                 sci_phy_consume_power_handler(requester);
1937                                         }
1938                                 }
1939                         }
1940                 }
1941         }
1942
1943         /*
1944          * It doesn't matter if the power list is empty, we need to start the
1945          * timer in case another phy becomes ready.
1946          */
1947         sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1948         ihost->power_control.timer_started = true;
1949
1950 done:
1951         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1952 }
1953
1954 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1955                                                struct isci_phy *iphy)
1956 {
1957         BUG_ON(iphy == NULL);
1958
1959         if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1960                 ihost->power_control.phys_granted_power++;
1961                 sci_phy_consume_power_handler(iphy);
1962
1963                 /*
1964                  * stop and start the power_control timer. When the timer fires, the
1965                  * no_of_phys_granted_power will be set to 0
1966                  */
1967                 if (ihost->power_control.timer_started)
1968                         sci_del_timer(&ihost->power_control.timer);
1969
1970                 sci_mod_timer(&ihost->power_control.timer,
1971                                  SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1972                 ihost->power_control.timer_started = true;
1973
1974         } else {
1975                 /*
1976                  * There are phys, attached to the same sas address as this phy, are
1977                  * already in READY state, this phy don't need wait.
1978                  */
1979                 u8 i;
1980                 struct isci_phy *current_phy;
1981
1982                 for (i = 0; i < SCI_MAX_PHYS; i++) {
1983                         u8 other;
1984                         current_phy = &ihost->phys[i];
1985
1986                         other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1987                                        iphy->frame_rcvd.iaf.sas_addr,
1988                                        sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1989
1990                         if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1991                             current_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS &&
1992                             other == 0) {
1993                                 sci_phy_consume_power_handler(iphy);
1994                                 break;
1995                         }
1996                 }
1997
1998                 if (i == SCI_MAX_PHYS) {
1999                         /* Add the phy in the waiting list */
2000                         ihost->power_control.requesters[iphy->phy_index] = iphy;
2001                         ihost->power_control.phys_waiting++;
2002                 }
2003         }
2004 }
2005
2006 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
2007                                                struct isci_phy *iphy)
2008 {
2009         BUG_ON(iphy == NULL);
2010
2011         if (ihost->power_control.requesters[iphy->phy_index])
2012                 ihost->power_control.phys_waiting--;
2013
2014         ihost->power_control.requesters[iphy->phy_index] = NULL;
2015 }
2016
2017 static int is_long_cable(int phy, unsigned char selection_byte)
2018 {
2019         return !!(selection_byte & (1 << phy));
2020 }
2021
2022 static int is_medium_cable(int phy, unsigned char selection_byte)
2023 {
2024         return !!(selection_byte & (1 << (phy + 4)));
2025 }
2026
2027 static enum cable_selections decode_selection_byte(
2028         int phy,
2029         unsigned char selection_byte)
2030 {
2031         return ((selection_byte & (1 << phy)) ? 1 : 0)
2032                 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
2033 }
2034
2035 static unsigned char *to_cable_select(struct isci_host *ihost)
2036 {
2037         if (is_cable_select_overridden())
2038                 return ((unsigned char *)&cable_selection_override)
2039                         + ihost->id;
2040         else
2041                 return &ihost->oem_parameters.controller.cable_selection_mask;
2042 }
2043
2044 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
2045 {
2046         return decode_selection_byte(phy, *to_cable_select(ihost));
2047 }
2048
2049 char *lookup_cable_names(enum cable_selections selection)
2050 {
2051         static char *cable_names[] = {
2052                 [short_cable]     = "short",
2053                 [long_cable]      = "long",
2054                 [medium_cable]    = "medium",
2055                 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
2056         };
2057         return (selection <= undefined_cable) ? cable_names[selection]
2058                                               : cable_names[undefined_cable];
2059 }
2060
2061 #define AFE_REGISTER_WRITE_DELAY 10
2062
2063 static void sci_controller_afe_initialization(struct isci_host *ihost)
2064 {
2065         struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
2066         const struct sci_oem_params *oem = &ihost->oem_parameters;
2067         struct pci_dev *pdev = ihost->pdev;
2068         u32 afe_status;
2069         u32 phy_id;
2070         unsigned char cable_selection_mask = *to_cable_select(ihost);
2071
2072         /* Clear DFX Status registers */
2073         writel(0x0081000f, &afe->afe_dfx_master_control0);
2074         udelay(AFE_REGISTER_WRITE_DELAY);
2075
2076         if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
2077                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2078                  * Timer, PM Stagger Timer
2079                  */
2080                 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
2081                 udelay(AFE_REGISTER_WRITE_DELAY);
2082         }
2083
2084         /* Configure bias currents to normal */
2085         if (is_a2(pdev))
2086                 writel(0x00005A00, &afe->afe_bias_control);
2087         else if (is_b0(pdev) || is_c0(pdev))
2088                 writel(0x00005F00, &afe->afe_bias_control);
2089         else if (is_c1(pdev))
2090                 writel(0x00005500, &afe->afe_bias_control);
2091
2092         udelay(AFE_REGISTER_WRITE_DELAY);
2093
2094         /* Enable PLL */
2095         if (is_a2(pdev))
2096                 writel(0x80040908, &afe->afe_pll_control0);
2097         else if (is_b0(pdev) || is_c0(pdev))
2098                 writel(0x80040A08, &afe->afe_pll_control0);
2099         else if (is_c1(pdev)) {
2100                 writel(0x80000B08, &afe->afe_pll_control0);
2101                 udelay(AFE_REGISTER_WRITE_DELAY);
2102                 writel(0x00000B08, &afe->afe_pll_control0);
2103                 udelay(AFE_REGISTER_WRITE_DELAY);
2104                 writel(0x80000B08, &afe->afe_pll_control0);
2105         }
2106
2107         udelay(AFE_REGISTER_WRITE_DELAY);
2108
2109         /* Wait for the PLL to lock */
2110         do {
2111                 afe_status = readl(&afe->afe_common_block_status);
2112                 udelay(AFE_REGISTER_WRITE_DELAY);
2113         } while ((afe_status & 0x00001000) == 0);
2114
2115         if (is_a2(pdev)) {
2116                 /* Shorten SAS SNW lock time (RxLock timer value from 76
2117                  * us to 50 us)
2118                  */
2119                 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
2120                 udelay(AFE_REGISTER_WRITE_DELAY);
2121         }
2122
2123         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2124                 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
2125                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2126                 int cable_length_long =
2127                         is_long_cable(phy_id, cable_selection_mask);
2128                 int cable_length_medium =
2129                         is_medium_cable(phy_id, cable_selection_mask);
2130
2131                 if (is_a2(pdev)) {
2132                         /* All defaults, except the Receive Word
2133                          * Alignament/Comma Detect Enable....(0xe800)
2134                          */
2135                         writel(0x00004512, &xcvr->afe_xcvr_control0);
2136                         udelay(AFE_REGISTER_WRITE_DELAY);
2137
2138                         writel(0x0050100F, &xcvr->afe_xcvr_control1);
2139                         udelay(AFE_REGISTER_WRITE_DELAY);
2140                 } else if (is_b0(pdev)) {
2141                         /* Configure transmitter SSC parameters */
2142                         writel(0x00030000, &xcvr->afe_tx_ssc_control);
2143                         udelay(AFE_REGISTER_WRITE_DELAY);
2144                 } else if (is_c0(pdev)) {
2145                         /* Configure transmitter SSC parameters */
2146                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
2147                         udelay(AFE_REGISTER_WRITE_DELAY);
2148
2149                         /* All defaults, except the Receive Word
2150                          * Alignament/Comma Detect Enable....(0xe800)
2151                          */
2152                         writel(0x00014500, &xcvr->afe_xcvr_control0);
2153                         udelay(AFE_REGISTER_WRITE_DELAY);
2154                 } else if (is_c1(pdev)) {
2155                         /* Configure transmitter SSC parameters */
2156                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
2157                         udelay(AFE_REGISTER_WRITE_DELAY);
2158
2159                         /* All defaults, except the Receive Word
2160                          * Alignament/Comma Detect Enable....(0xe800)
2161                          */
2162                         writel(0x0001C500, &xcvr->afe_xcvr_control0);
2163                         udelay(AFE_REGISTER_WRITE_DELAY);
2164                 }
2165
2166                 /* Power up TX and RX out from power down (PWRDNTX and
2167                  * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2168                  */
2169                 if (is_a2(pdev))
2170                         writel(0x000003F0, &xcvr->afe_channel_control);
2171                 else if (is_b0(pdev)) {
2172                         writel(0x000003D7, &xcvr->afe_channel_control);
2173                         udelay(AFE_REGISTER_WRITE_DELAY);
2174
2175                         writel(0x000003D4, &xcvr->afe_channel_control);
2176                 } else if (is_c0(pdev)) {
2177                         writel(0x000001E7, &xcvr->afe_channel_control);
2178                         udelay(AFE_REGISTER_WRITE_DELAY);
2179
2180                         writel(0x000001E4, &xcvr->afe_channel_control);
2181                 } else if (is_c1(pdev)) {
2182                         writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2183                                &xcvr->afe_channel_control);
2184                         udelay(AFE_REGISTER_WRITE_DELAY);
2185
2186                         writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2187                                &xcvr->afe_channel_control);
2188                 }
2189                 udelay(AFE_REGISTER_WRITE_DELAY);
2190
2191                 if (is_a2(pdev)) {
2192                         /* Enable TX equalization (0xe824) */
2193                         writel(0x00040000, &xcvr->afe_tx_control);
2194                         udelay(AFE_REGISTER_WRITE_DELAY);
2195                 }
2196
2197                 if (is_a2(pdev) || is_b0(pdev))
2198                         /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2199                          * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2200                          * Enabled) ....(0xe800)
2201                          */
2202                         writel(0x00004100, &xcvr->afe_xcvr_control0);
2203                 else if (is_c0(pdev))
2204                         writel(0x00014100, &xcvr->afe_xcvr_control0);
2205                 else if (is_c1(pdev))
2206                         writel(0x0001C100, &xcvr->afe_xcvr_control0);
2207                 udelay(AFE_REGISTER_WRITE_DELAY);
2208
2209                 /* Leave DFE/FFE on */
2210                 if (is_a2(pdev))
2211                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2212                 else if (is_b0(pdev)) {
2213                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2214                         udelay(AFE_REGISTER_WRITE_DELAY);
2215                         /* Enable TX equalization (0xe824) */
2216                         writel(0x00040000, &xcvr->afe_tx_control);
2217                 } else if (is_c0(pdev)) {
2218                         writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2219                         udelay(AFE_REGISTER_WRITE_DELAY);
2220
2221                         writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2222                         udelay(AFE_REGISTER_WRITE_DELAY);
2223
2224                         /* Enable TX equalization (0xe824) */
2225                         writel(0x00040000, &xcvr->afe_tx_control);
2226                 } else if (is_c1(pdev)) {
2227                         writel(cable_length_long ? 0x01500C0C :
2228                                cable_length_medium ? 0x01400C0D : 0x02400C0D,
2229                                &xcvr->afe_xcvr_control1);
2230                         udelay(AFE_REGISTER_WRITE_DELAY);
2231
2232                         writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2233                         udelay(AFE_REGISTER_WRITE_DELAY);
2234
2235                         writel(cable_length_long ? 0x33091C1F :
2236                                cable_length_medium ? 0x3315181F : 0x2B17161F,
2237                                &xcvr->afe_rx_ssc_control0);
2238                         udelay(AFE_REGISTER_WRITE_DELAY);
2239
2240                         /* Enable TX equalization (0xe824) */
2241                         writel(0x00040000, &xcvr->afe_tx_control);
2242                 }
2243
2244                 udelay(AFE_REGISTER_WRITE_DELAY);
2245
2246                 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2247                 udelay(AFE_REGISTER_WRITE_DELAY);
2248
2249                 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2250                 udelay(AFE_REGISTER_WRITE_DELAY);
2251
2252                 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2253                 udelay(AFE_REGISTER_WRITE_DELAY);
2254
2255                 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2256                 udelay(AFE_REGISTER_WRITE_DELAY);
2257         }
2258
2259         /* Transfer control to the PEs */
2260         writel(0x00010f00, &afe->afe_dfx_master_control0);
2261         udelay(AFE_REGISTER_WRITE_DELAY);
2262 }
2263
2264 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2265 {
2266         sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2267
2268         memset(ihost->power_control.requesters, 0,
2269                sizeof(ihost->power_control.requesters));
2270
2271         ihost->power_control.phys_waiting = 0;
2272         ihost->power_control.phys_granted_power = 0;
2273 }
2274
2275 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2276 {
2277         struct sci_base_state_machine *sm = &ihost->sm;
2278         enum sci_status result = SCI_FAILURE;
2279         unsigned long i, state, val;
2280
2281         if (ihost->sm.current_state_id != SCIC_RESET) {
2282                 dev_warn(&ihost->pdev->dev,
2283                          "SCIC Controller initialize operation requested "
2284                          "in invalid state\n");
2285                 return SCI_FAILURE_INVALID_STATE;
2286         }
2287
2288         sci_change_state(sm, SCIC_INITIALIZING);
2289
2290         sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2291
2292         ihost->next_phy_to_start = 0;
2293         ihost->phy_startup_timer_pending = false;
2294
2295         sci_controller_initialize_power_control(ihost);
2296
2297         /*
2298          * There is nothing to do here for B0 since we do not have to
2299          * program the AFE registers.
2300          * / @todo The AFE settings are supposed to be correct for the B0 but
2301          * /       presently they seem to be wrong. */
2302         sci_controller_afe_initialization(ihost);
2303
2304
2305         /* Take the hardware out of reset */
2306         writel(0, &ihost->smu_registers->soft_reset_control);
2307
2308         /*
2309          * / @todo Provide meaningfull error code for hardware failure
2310          * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2311         for (i = 100; i >= 1; i--) {
2312                 u32 status;
2313
2314                 /* Loop until the hardware reports success */
2315                 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2316                 status = readl(&ihost->smu_registers->control_status);
2317
2318                 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2319                         break;
2320         }
2321         if (i == 0)
2322                 goto out;
2323
2324         /*
2325          * Determine what are the actaul device capacities that the
2326          * hardware will support */
2327         val = readl(&ihost->smu_registers->device_context_capacity);
2328
2329         /* Record the smaller of the two capacity values */
2330         ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2331         ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2332         ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2333
2334         /*
2335          * Make all PEs that are unassigned match up with the
2336          * logical ports
2337          */
2338         for (i = 0; i < ihost->logical_port_entries; i++) {
2339                 struct scu_port_task_scheduler_group_registers __iomem
2340                         *ptsg = &ihost->scu_registers->peg0.ptsg;
2341
2342                 writel(i, &ptsg->protocol_engine[i]);
2343         }
2344
2345         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2346         val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2347         val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2348         writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2349
2350         val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2351         val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2352         writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2353
2354         /*
2355          * Initialize the PHYs before the PORTs because the PHY registers
2356          * are accessed during the port initialization.
2357          */
2358         for (i = 0; i < SCI_MAX_PHYS; i++) {
2359                 result = sci_phy_initialize(&ihost->phys[i],
2360                                             &ihost->scu_registers->peg0.pe[i].tl,
2361                                             &ihost->scu_registers->peg0.pe[i].ll);
2362                 if (result != SCI_SUCCESS)
2363                         goto out;
2364         }
2365
2366         for (i = 0; i < ihost->logical_port_entries; i++) {
2367                 struct isci_port *iport = &ihost->ports[i];
2368
2369                 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2370                 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2371                 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2372         }
2373
2374         result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2375
2376  out:
2377         /* Advance the controller state machine */
2378         if (result == SCI_SUCCESS)
2379                 state = SCIC_INITIALIZED;
2380         else
2381                 state = SCIC_FAILED;
2382         sci_change_state(sm, state);
2383
2384         return result;
2385 }
2386
2387 static enum sci_status sci_user_parameters_set(struct isci_host *ihost,
2388                                                struct sci_user_parameters *sci_parms)
2389 {
2390         u32 state = ihost->sm.current_state_id;
2391
2392         if (state == SCIC_RESET ||
2393             state == SCIC_INITIALIZING ||
2394             state == SCIC_INITIALIZED) {
2395                 u16 index;
2396
2397                 /*
2398                  * Validate the user parameters.  If they are not legal, then
2399                  * return a failure.
2400                  */
2401                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2402                         struct sci_phy_user_params *user_phy;
2403
2404                         user_phy = &sci_parms->phys[index];
2405
2406                         if (!((user_phy->max_speed_generation <=
2407                                                 SCIC_SDS_PARM_MAX_SPEED) &&
2408                               (user_phy->max_speed_generation >
2409                                                 SCIC_SDS_PARM_NO_SPEED)))
2410                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2411
2412                         if (user_phy->in_connection_align_insertion_frequency <
2413                                         3)
2414                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2415
2416                         if ((user_phy->in_connection_align_insertion_frequency <
2417                                                 3) ||
2418                             (user_phy->align_insertion_frequency == 0) ||
2419                             (user_phy->
2420                                 notify_enable_spin_up_insertion_frequency ==
2421                                                 0))
2422                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2423                 }
2424
2425                 if ((sci_parms->stp_inactivity_timeout == 0) ||
2426                     (sci_parms->ssp_inactivity_timeout == 0) ||
2427                     (sci_parms->stp_max_occupancy_timeout == 0) ||
2428                     (sci_parms->ssp_max_occupancy_timeout == 0) ||
2429                     (sci_parms->no_outbound_task_timeout == 0))
2430                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2431
2432                 memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms));
2433
2434                 return SCI_SUCCESS;
2435         }
2436
2437         return SCI_FAILURE_INVALID_STATE;
2438 }
2439
2440 static int sci_controller_mem_init(struct isci_host *ihost)
2441 {
2442         struct device *dev = &ihost->pdev->dev;
2443         dma_addr_t dma;
2444         size_t size;
2445         int err;
2446
2447         size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2448         ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2449         if (!ihost->completion_queue)
2450                 return -ENOMEM;
2451
2452         writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower);
2453         writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper);
2454
2455         size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2456         ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2457                                                                GFP_KERNEL);
2458         if (!ihost->remote_node_context_table)
2459                 return -ENOMEM;
2460
2461         writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower);
2462         writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper);
2463
2464         size = ihost->task_context_entries * sizeof(struct scu_task_context),
2465         ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2466         if (!ihost->task_context_table)
2467                 return -ENOMEM;
2468
2469         ihost->task_context_dma = dma;
2470         writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower);
2471         writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper);
2472
2473         err = sci_unsolicited_frame_control_construct(ihost);
2474         if (err)
2475                 return err;
2476
2477         /*
2478          * Inform the silicon as to the location of the UF headers and
2479          * address table.
2480          */
2481         writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2482                 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2483         writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2484                 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2485
2486         writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2487                 &ihost->scu_registers->sdma.uf_address_table_lower);
2488         writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2489                 &ihost->scu_registers->sdma.uf_address_table_upper);
2490
2491         return 0;
2492 }
2493
2494 int isci_host_init(struct isci_host *ihost)
2495 {
2496         int err = 0, i;
2497         enum sci_status status;
2498         struct sci_user_parameters sci_user_params;
2499         struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
2500
2501         spin_lock_init(&ihost->state_lock);
2502         spin_lock_init(&ihost->scic_lock);
2503         init_waitqueue_head(&ihost->eventq);
2504
2505         isci_host_change_state(ihost, isci_starting);
2506
2507         status = sci_controller_construct(ihost, scu_base(ihost),
2508                                           smu_base(ihost));
2509
2510         if (status != SCI_SUCCESS) {
2511                 dev_err(&ihost->pdev->dev,
2512                         "%s: sci_controller_construct failed - status = %x\n",
2513                         __func__,
2514                         status);
2515                 return -ENODEV;
2516         }
2517
2518         ihost->sas_ha.dev = &ihost->pdev->dev;
2519         ihost->sas_ha.lldd_ha = ihost;
2520
2521         /*
2522          * grab initial values stored in the controller object for OEM and USER
2523          * parameters
2524          */
2525         isci_user_parameters_get(&sci_user_params);
2526         status = sci_user_parameters_set(ihost, &sci_user_params);
2527         if (status != SCI_SUCCESS) {
2528                 dev_warn(&ihost->pdev->dev,
2529                          "%s: sci_user_parameters_set failed\n",
2530                          __func__);
2531                 return -ENODEV;
2532         }
2533
2534         /* grab any OEM parameters specified in orom */
2535         if (pci_info->orom) {
2536                 status = isci_parse_oem_parameters(&ihost->oem_parameters,
2537                                                    pci_info->orom,
2538                                                    ihost->id);
2539                 if (status != SCI_SUCCESS) {
2540                         dev_warn(&ihost->pdev->dev,
2541                                  "parsing firmware oem parameters failed\n");
2542                         return -EINVAL;
2543                 }
2544         }
2545
2546         status = sci_oem_parameters_set(ihost);
2547         if (status != SCI_SUCCESS) {
2548                 dev_warn(&ihost->pdev->dev,
2549                                 "%s: sci_oem_parameters_set failed\n",
2550                                 __func__);
2551                 return -ENODEV;
2552         }
2553
2554         tasklet_init(&ihost->completion_tasklet,
2555                      isci_host_completion_routine, (unsigned long)ihost);
2556
2557         INIT_LIST_HEAD(&ihost->requests_to_complete);
2558         INIT_LIST_HEAD(&ihost->requests_to_errorback);
2559
2560         spin_lock_irq(&ihost->scic_lock);
2561         status = sci_controller_initialize(ihost);
2562         spin_unlock_irq(&ihost->scic_lock);
2563         if (status != SCI_SUCCESS) {
2564                 dev_warn(&ihost->pdev->dev,
2565                          "%s: sci_controller_initialize failed -"
2566                          " status = 0x%x\n",
2567                          __func__, status);
2568                 return -ENODEV;
2569         }
2570
2571         err = sci_controller_mem_init(ihost);
2572         if (err)
2573                 return err;
2574
2575         for (i = 0; i < SCI_MAX_PORTS; i++)
2576                 isci_port_init(&ihost->ports[i], ihost, i);
2577
2578         for (i = 0; i < SCI_MAX_PHYS; i++)
2579                 isci_phy_init(&ihost->phys[i], ihost, i);
2580
2581         /* enable sgpio */
2582         writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2583         for (i = 0; i < isci_gpio_count(ihost); i++)
2584                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2585         writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2586
2587         for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2588                 struct isci_remote_device *idev = &ihost->devices[i];
2589
2590                 INIT_LIST_HEAD(&idev->reqs_in_process);
2591                 INIT_LIST_HEAD(&idev->node);
2592         }
2593
2594         for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2595                 struct isci_request *ireq;
2596                 dma_addr_t dma;
2597
2598                 ireq = dmam_alloc_coherent(&ihost->pdev->dev,
2599                                            sizeof(struct isci_request), &dma,
2600                                            GFP_KERNEL);
2601                 if (!ireq)
2602                         return -ENOMEM;
2603
2604                 ireq->tc = &ihost->task_context_table[i];
2605                 ireq->owning_controller = ihost;
2606                 spin_lock_init(&ireq->state_lock);
2607                 ireq->request_daddr = dma;
2608                 ireq->isci_host = ihost;
2609                 ihost->reqs[i] = ireq;
2610         }
2611
2612         return 0;
2613 }
2614
2615 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2616                             struct isci_phy *iphy)
2617 {
2618         switch (ihost->sm.current_state_id) {
2619         case SCIC_STARTING:
2620                 sci_del_timer(&ihost->phy_timer);
2621                 ihost->phy_startup_timer_pending = false;
2622                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2623                                                   iport, iphy);
2624                 sci_controller_start_next_phy(ihost);
2625                 break;
2626         case SCIC_READY:
2627                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2628                                                   iport, iphy);
2629                 break;
2630         default:
2631                 dev_dbg(&ihost->pdev->dev,
2632                         "%s: SCIC Controller linkup event from phy %d in "
2633                         "unexpected state %d\n", __func__, iphy->phy_index,
2634                         ihost->sm.current_state_id);
2635         }
2636 }
2637
2638 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2639                               struct isci_phy *iphy)
2640 {
2641         switch (ihost->sm.current_state_id) {
2642         case SCIC_STARTING:
2643         case SCIC_READY:
2644                 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2645                                                    iport, iphy);
2646                 break;
2647         default:
2648                 dev_dbg(&ihost->pdev->dev,
2649                         "%s: SCIC Controller linkdown event from phy %d in "
2650                         "unexpected state %d\n",
2651                         __func__,
2652                         iphy->phy_index,
2653                         ihost->sm.current_state_id);
2654         }
2655 }
2656
2657 static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2658 {
2659         u32 index;
2660
2661         for (index = 0; index < ihost->remote_node_entries; index++) {
2662                 if ((ihost->device_table[index] != NULL) &&
2663                    (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2664                         return true;
2665         }
2666
2667         return false;
2668 }
2669
2670 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2671                                           struct isci_remote_device *idev)
2672 {
2673         if (ihost->sm.current_state_id != SCIC_STOPPING) {
2674                 dev_dbg(&ihost->pdev->dev,
2675                         "SCIC Controller 0x%p remote device stopped event "
2676                         "from device 0x%p in unexpected state %d\n",
2677                         ihost, idev,
2678                         ihost->sm.current_state_id);
2679                 return;
2680         }
2681
2682         if (!sci_controller_has_remote_devices_stopping(ihost))
2683                 sci_change_state(&ihost->sm, SCIC_STOPPED);
2684 }
2685
2686 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2687 {
2688         dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2689                 __func__, ihost->id, request);
2690
2691         writel(request, &ihost->smu_registers->post_context_port);
2692 }
2693
2694 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2695 {
2696         u16 task_index;
2697         u16 task_sequence;
2698
2699         task_index = ISCI_TAG_TCI(io_tag);
2700
2701         if (task_index < ihost->task_context_entries) {
2702                 struct isci_request *ireq = ihost->reqs[task_index];
2703
2704                 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2705                         task_sequence = ISCI_TAG_SEQ(io_tag);
2706
2707                         if (task_sequence == ihost->io_request_sequence[task_index])
2708                                 return ireq;
2709                 }
2710         }
2711
2712         return NULL;
2713 }
2714
2715 /**
2716  * This method allocates remote node index and the reserves the remote node
2717  *    context space for use. This method can fail if there are no more remote
2718  *    node index available.
2719  * @scic: This is the controller object which contains the set of
2720  *    free remote node ids
2721  * @sci_dev: This is the device object which is requesting the a remote node
2722  *    id
2723  * @node_id: This is the remote node id that is assinged to the device if one
2724  *    is available
2725  *
2726  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2727  * node index available.
2728  */
2729 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2730                                                             struct isci_remote_device *idev,
2731                                                             u16 *node_id)
2732 {
2733         u16 node_index;
2734         u32 remote_node_count = sci_remote_device_node_count(idev);
2735
2736         node_index = sci_remote_node_table_allocate_remote_node(
2737                 &ihost->available_remote_nodes, remote_node_count
2738                 );
2739
2740         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2741                 ihost->device_table[node_index] = idev;
2742
2743                 *node_id = node_index;
2744
2745                 return SCI_SUCCESS;
2746         }
2747
2748         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2749 }
2750
2751 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2752                                              struct isci_remote_device *idev,
2753                                              u16 node_id)
2754 {
2755         u32 remote_node_count = sci_remote_device_node_count(idev);
2756
2757         if (ihost->device_table[node_id] == idev) {
2758                 ihost->device_table[node_id] = NULL;
2759
2760                 sci_remote_node_table_release_remote_node_index(
2761                         &ihost->available_remote_nodes, remote_node_count, node_id
2762                         );
2763         }
2764 }
2765
2766 void sci_controller_copy_sata_response(void *response_buffer,
2767                                        void *frame_header,
2768                                        void *frame_buffer)
2769 {
2770         /* XXX type safety? */
2771         memcpy(response_buffer, frame_header, sizeof(u32));
2772
2773         memcpy(response_buffer + sizeof(u32),
2774                frame_buffer,
2775                sizeof(struct dev_to_host_fis) - sizeof(u32));
2776 }
2777
2778 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2779 {
2780         if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2781                 writel(ihost->uf_control.get,
2782                         &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2783 }
2784
2785 void isci_tci_free(struct isci_host *ihost, u16 tci)
2786 {
2787         u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2788
2789         ihost->tci_pool[tail] = tci;
2790         ihost->tci_tail = tail + 1;
2791 }
2792
2793 static u16 isci_tci_alloc(struct isci_host *ihost)
2794 {
2795         u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2796         u16 tci = ihost->tci_pool[head];
2797
2798         ihost->tci_head = head + 1;
2799         return tci;
2800 }
2801
2802 static u16 isci_tci_space(struct isci_host *ihost)
2803 {
2804         return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2805 }
2806
2807 u16 isci_alloc_tag(struct isci_host *ihost)
2808 {
2809         if (isci_tci_space(ihost)) {
2810                 u16 tci = isci_tci_alloc(ihost);
2811                 u8 seq = ihost->io_request_sequence[tci];
2812
2813                 return ISCI_TAG(seq, tci);
2814         }
2815
2816         return SCI_CONTROLLER_INVALID_IO_TAG;
2817 }
2818
2819 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2820 {
2821         u16 tci = ISCI_TAG_TCI(io_tag);
2822         u16 seq = ISCI_TAG_SEQ(io_tag);
2823
2824         /* prevent tail from passing head */
2825         if (isci_tci_active(ihost) == 0)
2826                 return SCI_FAILURE_INVALID_IO_TAG;
2827
2828         if (seq == ihost->io_request_sequence[tci]) {
2829                 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2830
2831                 isci_tci_free(ihost, tci);
2832
2833                 return SCI_SUCCESS;
2834         }
2835         return SCI_FAILURE_INVALID_IO_TAG;
2836 }
2837
2838 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2839                                         struct isci_remote_device *idev,
2840                                         struct isci_request *ireq)
2841 {
2842         enum sci_status status;
2843
2844         if (ihost->sm.current_state_id != SCIC_READY) {
2845                 dev_warn(&ihost->pdev->dev, "invalid state to start I/O");
2846                 return SCI_FAILURE_INVALID_STATE;
2847         }
2848
2849         status = sci_remote_device_start_io(ihost, idev, ireq);
2850         if (status != SCI_SUCCESS)
2851                 return status;
2852
2853         set_bit(IREQ_ACTIVE, &ireq->flags);
2854         sci_controller_post_request(ihost, ireq->post_context);
2855         return SCI_SUCCESS;
2856 }
2857
2858 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2859                                                  struct isci_remote_device *idev,
2860                                                  struct isci_request *ireq)
2861 {
2862         /* terminate an ongoing (i.e. started) core IO request.  This does not
2863          * abort the IO request at the target, but rather removes the IO
2864          * request from the host controller.
2865          */
2866         enum sci_status status;
2867
2868         if (ihost->sm.current_state_id != SCIC_READY) {
2869                 dev_warn(&ihost->pdev->dev,
2870                          "invalid state to terminate request\n");
2871                 return SCI_FAILURE_INVALID_STATE;
2872         }
2873
2874         status = sci_io_request_terminate(ireq);
2875         if (status != SCI_SUCCESS)
2876                 return status;
2877
2878         /*
2879          * Utilize the original post context command and or in the POST_TC_ABORT
2880          * request sub-type.
2881          */
2882         sci_controller_post_request(ihost,
2883                                     ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2884         return SCI_SUCCESS;
2885 }
2886
2887 /**
2888  * sci_controller_complete_io() - This method will perform core specific
2889  *    completion operations for an IO request.  After this method is invoked,
2890  *    the user should consider the IO request as invalid until it is properly
2891  *    reused (i.e. re-constructed).
2892  * @ihost: The handle to the controller object for which to complete the
2893  *    IO request.
2894  * @idev: The handle to the remote device object for which to complete
2895  *    the IO request.
2896  * @ireq: the handle to the io request object to complete.
2897  */
2898 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2899                                            struct isci_remote_device *idev,
2900                                            struct isci_request *ireq)
2901 {
2902         enum sci_status status;
2903         u16 index;
2904
2905         switch (ihost->sm.current_state_id) {
2906         case SCIC_STOPPING:
2907                 /* XXX: Implement this function */
2908                 return SCI_FAILURE;
2909         case SCIC_READY:
2910                 status = sci_remote_device_complete_io(ihost, idev, ireq);
2911                 if (status != SCI_SUCCESS)
2912                         return status;
2913
2914                 index = ISCI_TAG_TCI(ireq->io_tag);
2915                 clear_bit(IREQ_ACTIVE, &ireq->flags);
2916                 return SCI_SUCCESS;
2917         default:
2918                 dev_warn(&ihost->pdev->dev, "invalid state to complete I/O");
2919                 return SCI_FAILURE_INVALID_STATE;
2920         }
2921
2922 }
2923
2924 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2925 {
2926         struct isci_host *ihost = ireq->owning_controller;
2927
2928         if (ihost->sm.current_state_id != SCIC_READY) {
2929                 dev_warn(&ihost->pdev->dev, "invalid state to continue I/O");
2930                 return SCI_FAILURE_INVALID_STATE;
2931         }
2932
2933         set_bit(IREQ_ACTIVE, &ireq->flags);
2934         sci_controller_post_request(ihost, ireq->post_context);
2935         return SCI_SUCCESS;
2936 }
2937
2938 /**
2939  * sci_controller_start_task() - This method is called by the SCIC user to
2940  *    send/start a framework task management request.
2941  * @controller: the handle to the controller object for which to start the task
2942  *    management request.
2943  * @remote_device: the handle to the remote device object for which to start
2944  *    the task management request.
2945  * @task_request: the handle to the task request object to start.
2946  */
2947 enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2948                                                struct isci_remote_device *idev,
2949                                                struct isci_request *ireq)
2950 {
2951         enum sci_status status;
2952
2953         if (ihost->sm.current_state_id != SCIC_READY) {
2954                 dev_warn(&ihost->pdev->dev,
2955                          "%s: SCIC Controller starting task from invalid "
2956                          "state\n",
2957                          __func__);
2958                 return SCI_TASK_FAILURE_INVALID_STATE;
2959         }
2960
2961         status = sci_remote_device_start_task(ihost, idev, ireq);
2962         switch (status) {
2963         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2964                 set_bit(IREQ_ACTIVE, &ireq->flags);
2965
2966                 /*
2967                  * We will let framework know this task request started successfully,
2968                  * although core is still woring on starting the request (to post tc when
2969                  * RNC is resumed.)
2970                  */
2971                 return SCI_SUCCESS;
2972         case SCI_SUCCESS:
2973                 set_bit(IREQ_ACTIVE, &ireq->flags);
2974                 sci_controller_post_request(ihost, ireq->post_context);
2975                 break;
2976         default:
2977                 break;
2978         }
2979
2980         return status;
2981 }
2982
2983 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2984 {
2985         int d;
2986
2987         /* no support for TX_GP_CFG */
2988         if (reg_index == 0)
2989                 return -EINVAL;
2990
2991         for (d = 0; d < isci_gpio_count(ihost); d++) {
2992                 u32 val = 0x444; /* all ODx.n clear */
2993                 int i;
2994
2995                 for (i = 0; i < 3; i++) {
2996                         int bit = (i << 2) + 2;
2997
2998                         bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2999                                                        write_data, reg_index,
3000                                                        reg_count);
3001                         if (bit < 0)
3002                                 break;
3003
3004                         /* if od is set, clear the 'invert' bit */
3005                         val &= ~(bit << ((i << 2) + 2));
3006                 }
3007
3008                 if (i < 3)
3009                         break;
3010                 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
3011         }
3012
3013         /* unless reg_index is > 1, we should always be able to write at
3014          * least one register
3015          */
3016         return d > 0;
3017 }
3018
3019 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
3020                     u8 reg_count, u8 *write_data)
3021 {
3022         struct isci_host *ihost = sas_ha->lldd_ha;
3023         int written;
3024
3025         switch (reg_type) {
3026         case SAS_GPIO_REG_TX_GP:
3027                 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
3028                 break;
3029         default:
3030                 written = -EINVAL;
3031         }
3032
3033         return written;
3034 }