2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 /* general boundary defintions */
25 #define SENSEINFOBYTES 32 /* may vary between hbas */
26 #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
27 #define HPSA_SG_CHAIN 0x80000000
28 #define MAXREPLYQS 256
30 /* Command Status value */
31 #define CMD_SUCCESS 0x0000
32 #define CMD_TARGET_STATUS 0x0001
33 #define CMD_DATA_UNDERRUN 0x0002
34 #define CMD_DATA_OVERRUN 0x0003
35 #define CMD_INVALID 0x0004
36 #define CMD_PROTOCOL_ERR 0x0005
37 #define CMD_HARDWARE_ERR 0x0006
38 #define CMD_CONNECTION_LOST 0x0007
39 #define CMD_ABORTED 0x0008
40 #define CMD_ABORT_FAILED 0x0009
41 #define CMD_UNSOLICITED_ABORT 0x000A
42 #define CMD_TIMEOUT 0x000B
43 #define CMD_UNABORTABLE 0x000C
45 /* Unit Attentions ASC's as defined for the MSA2012sa */
46 #define POWER_OR_RESET 0x29
47 #define STATE_CHANGED 0x2a
48 #define UNIT_ATTENTION_CLEARED 0x2f
49 #define LUN_FAILED 0x3e
50 #define REPORT_LUNS_CHANGED 0x3f
52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
54 /* These ASCQ's defined for ASC = POWER_OR_RESET */
55 #define POWER_ON_RESET 0x00
56 #define POWER_ON_REBOOT 0x01
57 #define SCSI_BUS_RESET 0x02
58 #define MSA_TARGET_RESET 0x03
59 #define CONTROLLER_FAILOVER 0x04
60 #define TRANSCEIVER_SE 0x05
61 #define TRANSCEIVER_LVD 0x06
63 /* These ASCQ's defined for ASC = STATE_CHANGED */
64 #define RESERVATION_PREEMPTED 0x03
65 #define ASYM_ACCESS_CHANGED 0x06
66 #define LUN_CAPACITY_CHANGED 0x09
68 /* transfer direction */
69 #define XFER_NONE 0x00
70 #define XFER_WRITE 0x01
71 #define XFER_READ 0x02
72 #define XFER_RSVD 0x03
75 #define ATTR_UNTAGGED 0x00
76 #define ATTR_SIMPLE 0x04
77 #define ATTR_HEADOFQUEUE 0x05
78 #define ATTR_ORDERED 0x06
86 #define HPSA_TASK_MANAGEMENT 0x00
87 #define HPSA_RESET 0x01
88 #define HPSA_SCAN 0x02
89 #define HPSA_NOOP 0x03
91 #define HPSA_CTLR_RESET_TYPE 0x00
92 #define HPSA_BUS_RESET_TYPE 0x01
93 #define HPSA_TARGET_RESET_TYPE 0x03
94 #define HPSA_LUN_RESET_TYPE 0x04
95 #define HPSA_NEXUS_RESET_TYPE 0x05
97 /* Task Management Functions */
98 #define HPSA_TMF_ABORT_TASK 0x00
99 #define HPSA_TMF_ABORT_TASK_SET 0x01
100 #define HPSA_TMF_CLEAR_ACA 0x02
101 #define HPSA_TMF_CLEAR_TASK_SET 0x03
102 #define HPSA_TMF_QUERY_TASK 0x04
103 #define HPSA_TMF_QUERY_TASK_SET 0x05
104 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
108 /* config space register offsets */
109 #define CFG_VENDORID 0x00
110 #define CFG_DEVICEID 0x02
111 #define CFG_I2OBAR 0x10
112 #define CFG_MEM1BAR 0x14
114 /* i2o space register offsets */
115 #define I2O_IBDB_SET 0x20
116 #define I2O_IBDB_CLEAR 0x70
117 #define I2O_INT_STATUS 0x30
118 #define I2O_INT_MASK 0x34
119 #define I2O_IBPOST_Q 0x40
120 #define I2O_OBPOST_Q 0x44
121 #define I2O_DMA1_CFG 0x214
123 /* Configuration Table */
124 #define CFGTBL_ChangeReq 0x00000001l
125 #define CFGTBL_AccCmds 0x00000001l
126 #define DOORBELL_CTLR_RESET 0x00000004l
127 #define DOORBELL_CTLR_RESET2 0x00000020l
129 #define CFGTBL_Trans_Simple 0x00000002l
130 #define CFGTBL_Trans_Performant 0x00000004l
131 #define CFGTBL_Trans_use_short_tags 0x20000000l
133 #define CFGTBL_BusType_Ultra2 0x00000001l
134 #define CFGTBL_BusType_Ultra3 0x00000002l
135 #define CFGTBL_BusType_Fibre1G 0x00000100l
136 #define CFGTBL_BusType_Fibre2G 0x00000200l
147 /* FIXME this is a per controller value (barf!) */
148 #define HPSA_MAX_LUN 1024
149 #define HPSA_MAX_PHYS_LUN 1024
150 #define MAX_EXT_TARGETS 32
151 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
152 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
154 /* SCSI-3 Commands */
157 #define HPSA_INQUIRY 0x12
162 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
163 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
164 struct ReportLUNdata {
167 u8 LUN[HPSA_MAX_LUN][8];
170 struct ReportExtendedLUNdata {
172 u8 extended_response_flag;
174 u8 LUN[HPSA_MAX_LUN][24];
177 struct SenseSubsystem_info {
184 #define BMIC_READ 0x26
185 #define BMIC_WRITE 0x27
186 #define BMIC_CACHE_FLUSH 0xc2
187 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
189 /* Command List Structure */
213 /* 2 level target device addr */
214 union SCSI3Addr Target[2];
225 union SCSI3Addr SCSI3Lun[4];
226 struct PhysDevAddr PhysDev;
227 struct LogDevAddr LogDev;
230 struct CommandListHeader {
238 struct RequestBlock {
249 struct ErrDescriptor {
254 struct SGDescriptor {
268 u8 offense_size; /* size of offending entry */
269 u8 offense_num; /* byte # of offense 0-base */
278 union MoreErrInfo MoreErrInfo;
279 u8 SenseInfo[SENSEINFOBYTES];
282 #define CMD_IOCTL_PEND 0x01
283 #define CMD_SCSI 0x03
285 #define DIRECT_LOOKUP_SHIFT 5
286 #define DIRECT_LOOKUP_BIT 0x10
287 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
289 #define HPSA_ERROR_BIT 0x02
290 struct ctlr_info; /* defined in hpsa.h */
291 /* The size of this structure needs to be divisible by 32
292 * on all architectures because low 5 bits of the addresses
293 * are used as follows:
295 * bit 0: to device, used to indicate "performant mode" command
296 * from device, indidcates error status.
297 * bit 1-3: to device, indicates block fetch table entry for
298 * reducing DMA in fetching commands from host memory.
299 * bit 4: used to indicate whether tag is "direct lookup" (index),
304 struct CommandListHeader Header;
305 struct RequestBlock Request;
306 struct ErrDescriptor ErrDesc;
307 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
308 /* information associated with the command */
309 u32 busaddr; /* physical addr of this record */
310 struct ErrorInfo *err_info; /* pointer to the allocated mem */
314 struct list_head list;
316 struct completion *waiting;
319 /* on 64 bit architectures, to get this to be 32-byte-aligned
320 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
321 * we need PAD_32 bytes of padding (see below). This does that.
322 * If it happens that 64 bit and 32 bit systems need different
323 * padding, PAD_32 and PAD_64 can be set independently, and.
324 * the code below will do the right thing.
326 #define IS_32_BIT ((8 - sizeof(long))/4)
327 #define IS_64_BIT (!IS_32_BIT)
330 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
331 u8 pad[COMMANDLIST_PAD];
334 /* Configuration Table Structure */
336 u32 TransportRequest;
342 #define SIMPLE_MODE 0x02
343 #define PERFORMANT_MODE 0x04
344 #define MEMQ_MODE 0x08
349 u32 TransportSupport;
351 struct HostWrite HostWrite;
354 u32 TransMethodOffset;
358 u32 MaxScatterGatherElements;
360 u32 MaxPhysicalDevices;
361 u32 MaxPhysicalDrivesPerLogicalUnit;
362 u32 MaxPerformantModeCommands;
364 u32 PowerConservationSupport;
365 u32 PowerConservationEnable;
368 u8 reserved[0x78 - 0x70];
369 u32 misc_fw_support; /* offset 0x78 */
370 #define MISC_FW_DOORBELL_RESET (0x02)
371 #define MISC_FW_DOORBELL_RESET2 (0x010)
372 u8 driver_version[32];
376 #define NUM_BLOCKFETCH_ENTRIES 8
377 struct TransTable_struct {
378 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
381 u32 RepQCtrAddrLow32;
382 u32 RepQCtrAddrHigh32;
387 struct hpsa_pci_info {
389 unsigned char dev_fn;
390 unsigned short domain;
395 #endif /* HPSA_CMD_H */