drivers/scsi/hpsa_cmd.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2014-2015 PMC-Sierra, Inc.
   4  *    Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; version 2 of the License.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  14  *
  15  *    Questions/Comments/Bugfixes to storagedev@pmcs.com
  16  *
  17  */
  18 #ifndef HPSA_CMD_H
  19 #define HPSA_CMD_H
  20
  21 /* general boundary defintions */
  22 #define SENSEINFOBYTES          32 /* may vary between hbas */
  23 #define SG_ENTRIES_IN_CMD       32 /* Max SG entries excluding chain blocks */
  24 #define HPSA_SG_CHAIN           0x80000000
  25 #define HPSA_SG_LAST            0x40000000
  26 #define MAXREPLYQS              256
  27
  28 /* Command Status value */
  29 #define CMD_SUCCESS             0x0000
  30 #define CMD_TARGET_STATUS       0x0001
  31 #define CMD_DATA_UNDERRUN       0x0002
  32 #define CMD_DATA_OVERRUN        0x0003
  33 #define CMD_INVALID             0x0004
  34 #define CMD_PROTOCOL_ERR        0x0005
  35 #define CMD_HARDWARE_ERR        0x0006
  36 #define CMD_CONNECTION_LOST     0x0007
  37 #define CMD_ABORTED             0x0008
  38 #define CMD_ABORT_FAILED        0x0009
  39 #define CMD_UNSOLICITED_ABORT   0x000A
  40 #define CMD_TIMEOUT             0x000B
  41 #define CMD_UNABORTABLE         0x000C
  42 #define CMD_TMF_STATUS          0x000D
  43 #define CMD_IOACCEL_DISABLED    0x000E
  44 #define CMD_CTLR_LOCKUP         0xffff
  45 /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
  46  * it is a value defined by the driver that commands can be marked
  47  * with when a controller lockup has been detected by the driver
  48  */
  49
  50 /* TMF function status values */
  51 #define CISS_TMF_COMPLETE       0x00
  52 #define CISS_TMF_INVALID_FRAME  0x02
  53 #define CISS_TMF_NOT_SUPPORTED  0x04
  54 #define CISS_TMF_FAILED         0x05
  55 #define CISS_TMF_SUCCESS        0x08
  56 #define CISS_TMF_WRONG_LUN      0x09
  57 #define CISS_TMF_OVERLAPPED_TAG 0x0a
  58
  59 /* Unit Attentions ASC's as defined for the MSA2012sa */
  60 #define POWER_OR_RESET                  0x29
  61 #define STATE_CHANGED                   0x2a
  62 #define UNIT_ATTENTION_CLEARED          0x2f
  63 #define LUN_FAILED                      0x3e
  64 #define REPORT_LUNS_CHANGED             0x3f
  65
  66 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  67
  68         /* These ASCQ's defined for ASC = POWER_OR_RESET */
  69 #define POWER_ON_RESET                  0x00
  70 #define POWER_ON_REBOOT                 0x01
  71 #define SCSI_BUS_RESET                  0x02
  72 #define MSA_TARGET_RESET                0x03
  73 #define CONTROLLER_FAILOVER             0x04
  74 #define TRANSCEIVER_SE                  0x05
  75 #define TRANSCEIVER_LVD                 0x06
  76
  77         /* These ASCQ's defined for ASC = STATE_CHANGED */
  78 #define RESERVATION_PREEMPTED           0x03
  79 #define ASYM_ACCESS_CHANGED             0x06
  80 #define LUN_CAPACITY_CHANGED            0x09
  81
  82 /* transfer direction */
  83 #define XFER_NONE               0x00
  84 #define XFER_WRITE              0x01
  85 #define XFER_READ               0x02
  86 #define XFER_RSVD               0x03
  87
  88 /* task attribute */
  89 #define ATTR_UNTAGGED           0x00
  90 #define ATTR_SIMPLE             0x04
  91 #define ATTR_HEADOFQUEUE        0x05
  92 #define ATTR_ORDERED            0x06
  93 #define ATTR_ACA                0x07
  94
  95 /* cdb type */
  96 #define TYPE_CMD                0x00
  97 #define TYPE_MSG                0x01
  98 #define TYPE_IOACCEL2_CMD       0x81 /* 0x81 is not used by hardware */
  99
 100 /* Message Types  */
 101 #define HPSA_TASK_MANAGEMENT    0x00
 102 #define HPSA_RESET              0x01
 103 #define HPSA_SCAN               0x02
 104 #define HPSA_NOOP               0x03
 105
 106 #define HPSA_CTLR_RESET_TYPE    0x00
 107 #define HPSA_BUS_RESET_TYPE     0x01
 108 #define HPSA_TARGET_RESET_TYPE  0x03
 109 #define HPSA_LUN_RESET_TYPE     0x04
 110 #define HPSA_NEXUS_RESET_TYPE   0x05
 111
 112 /* Task Management Functions */
 113 #define HPSA_TMF_ABORT_TASK     0x00
 114 #define HPSA_TMF_ABORT_TASK_SET 0x01
 115 #define HPSA_TMF_CLEAR_ACA      0x02
 116 #define HPSA_TMF_CLEAR_TASK_SET 0x03
 117 #define HPSA_TMF_QUERY_TASK     0x04
 118 #define HPSA_TMF_QUERY_TASK_SET 0x05
 119 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
 120
 121
 122
 123 /* config space register offsets */
 124 #define CFG_VENDORID            0x00
 125 #define CFG_DEVICEID            0x02
 126 #define CFG_I2OBAR              0x10
 127 #define CFG_MEM1BAR             0x14
 128
 129 /* i2o space register offsets */
 130 #define I2O_IBDB_SET            0x20
 131 #define I2O_IBDB_CLEAR          0x70
 132 #define I2O_INT_STATUS          0x30
 133 #define I2O_INT_MASK            0x34
 134 #define I2O_IBPOST_Q            0x40
 135 #define I2O_OBPOST_Q            0x44
 136 #define I2O_DMA1_CFG            0x214
 137
 138 /* Configuration Table */
 139 #define CFGTBL_ChangeReq        0x00000001l
 140 #define CFGTBL_AccCmds          0x00000001l
 141 #define DOORBELL_CTLR_RESET     0x00000004l
 142 #define DOORBELL_CTLR_RESET2    0x00000020l
 143 #define DOORBELL_CLEAR_EVENTS   0x00000040l
 144
 145 #define CFGTBL_Trans_Simple     0x00000002l
 146 #define CFGTBL_Trans_Performant 0x00000004l
 147 #define CFGTBL_Trans_io_accel1  0x00000080l
 148 #define CFGTBL_Trans_io_accel2  0x00000100l
 149 #define CFGTBL_Trans_use_short_tags 0x20000000l
 150 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
 151
 152 #define CFGTBL_BusType_Ultra2   0x00000001l
 153 #define CFGTBL_BusType_Ultra3   0x00000002l
 154 #define CFGTBL_BusType_Fibre1G  0x00000100l
 155 #define CFGTBL_BusType_Fibre2G  0x00000200l
 156
 157 /* VPD Inquiry types */
 158 #define HPSA_VPD_SUPPORTED_PAGES        0x00
 159 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
 160 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
 161 #define HPSA_VPD_LV_STATUS              0xC3
 162 #define HPSA_VPD_HEADER_SZ              4
 163
 164 /* Logical volume states */
 165 #define HPSA_VPD_LV_STATUS_UNSUPPORTED                  0xff
 166 #define HPSA_LV_OK                                      0x0
 167 #define HPSA_LV_NOT_AVAILABLE                           0x0b
 168 #define HPSA_LV_UNDERGOING_ERASE                        0x0F
 169 #define HPSA_LV_UNDERGOING_RPI                          0x12
 170 #define HPSA_LV_PENDING_RPI                             0x13
 171 #define HPSA_LV_ENCRYPTED_NO_KEY                        0x14
 172 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER    0x15
 173 #define HPSA_LV_UNDERGOING_ENCRYPTION                   0x16
 174 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING          0x17
 175 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   0x18
 176 #define HPSA_LV_PENDING_ENCRYPTION                      0x19
 177 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING             0x1A
 178
 179 struct vals32 {
 180         u32   lower;
 181         u32   upper;
 182 };
 183
 184 union u64bit {
 185         struct vals32 val32;
 186         u64 val;
 187 };
 188
 189 /* FIXME this is a per controller value (barf!) */
 190 #define HPSA_MAX_LUN 1024
 191 #define HPSA_MAX_PHYS_LUN 1024
 192 #define MAX_EXT_TARGETS 32
 193 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
 194         MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
 195
 196 /* SCSI-3 Commands */
 197 #pragma pack(1)
 198
 199 #define HPSA_INQUIRY 0x12
 200 struct InquiryData {
 201         u8 data_byte[36];
 202 };
 203
 204 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
 205 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
 206 #define HPSA_REPORT_PHYS_EXTENDED 0x02
 207 #define HPSA_CISS_READ  0xc0    /* CISS Read */
 208 #define HPSA_GET_RAID_MAP 0xc8  /* CISS Get RAID Layout Map */
 209
 210 #define RAID_MAP_MAX_ENTRIES   256
 211
 212 struct raid_map_disk_data {
 213         u32   ioaccel_handle;         /**< Handle to access this disk via the
 214                                         *  I/O accelerator */
 215         u8    xor_mult[2];            /**< XOR multipliers for this position,
 216                                         *  valid for data disks only */
 217         u8    reserved[2];
 218 };
 219
 220 struct raid_map_data {
 221         __le32   structure_size;        /* Size of entire structure in bytes */
 222         __le32   volume_blk_size;       /* bytes / block in the volume */
 223         __le64   volume_blk_cnt;        /* logical blocks on the volume */
 224         u8    phys_blk_shift;           /* Shift factor to convert between
 225                                          * units of logical blocks and physical
 226                                          * disk blocks */
 227         u8    parity_rotation_shift;    /* Shift factor to convert between units
 228                                          * of logical stripes and physical
 229                                          * stripes */
 230         __le16   strip_size;            /* blocks used on each disk / stripe */
 231         __le64   disk_starting_blk;     /* First disk block used in volume */
 232         __le64   disk_blk_cnt;          /* disk blocks used by volume / disk */
 233         __le16   data_disks_per_row;    /* data disk entries / row in the map */
 234         __le16   metadata_disks_per_row;/* mirror/parity disk entries / row
 235                                          * in the map */
 236         __le16   row_cnt;               /* rows in each layout map */
 237         __le16   layout_map_count;      /* layout maps (1 map per mirror/parity
 238                                          * group) */
 239         __le16   flags;                 /* Bit 0 set if encryption enabled */
 240 #define RAID_MAP_FLAG_ENCRYPT_ON  0x01
 241         __le16   dekindex;              /* Data encryption key index. */
 242         u8    reserved[16];
 243         struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
 244 };
 245
 246 struct ReportLUNdata {
 247         u8 LUNListLength[4];
 248         u8 extended_response_flag;
 249         u8 reserved[3];
 250         u8 LUN[HPSA_MAX_LUN][8];
 251 };
 252
 253 struct ext_report_lun_entry {
 254         u8 lunid[8];
 255 #define MASKED_DEVICE(x) ((x)[3] & 0xC0)
 256 #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
 257 #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
 258 #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
 259                         GET_BMIC_LEVEL_TWO_TARGET((lunid)))
 260         u8 wwid[8];
 261         u8 device_type;
 262         u8 device_flags;
 263         u8 lun_count; /* multi-lun device, how many luns */
 264         u8 redundant_paths;
 265         u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
 266 };
 267
 268 struct ReportExtendedLUNdata {
 269         u8 LUNListLength[4];
 270         u8 extended_response_flag;
 271         u8 reserved[3];
 272         struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
 273 };
 274
 275 struct SenseSubsystem_info {
 276         u8 reserved[36];
 277         u8 portname[8];
 278         u8 reserved1[1108];
 279 };
 280
 281 /* BMIC commands */
 282 #define BMIC_READ 0x26
 283 #define BMIC_WRITE 0x27
 284 #define BMIC_CACHE_FLUSH 0xc2
 285 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
 286 #define BMIC_FLASH_FIRMWARE 0xF7
 287 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
 288 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
 289 #define BMIC_IDENTIFY_CONTROLLER 0x11
 290
 291 /* Command List Structure */
 292 union SCSI3Addr {
 293         struct {
 294                 u8 Dev;
 295                 u8 Bus:6;
 296                 u8 Mode:2;        /* b00 */
 297         } PeripDev;
 298         struct {
 299                 u8 DevLSB;
 300                 u8 DevMSB:6;
 301                 u8 Mode:2;        /* b01 */
 302         } LogDev;
 303         struct {
 304                 u8 Dev:5;
 305                 u8 Bus:3;
 306                 u8 Targ:6;
 307                 u8 Mode:2;        /* b10 */
 308         } LogUnit;
 309 };
 310
 311 struct PhysDevAddr {
 312         u32             TargetId:24;
 313         u32             Bus:6;
 314         u32             Mode:2;
 315         /* 2 level target device addr */
 316         union SCSI3Addr  Target[2];
 317 };
 318
 319 struct LogDevAddr {
 320         u32            VolId:30;
 321         u32            Mode:2;
 322         u8             reserved[4];
 323 };
 324
 325 union LUNAddr {
 326         u8               LunAddrBytes[8];
 327         union SCSI3Addr    SCSI3Lun[4];
 328         struct PhysDevAddr PhysDev;
 329         struct LogDevAddr  LogDev;
 330 };
 331
 332 struct CommandListHeader {
 333         u8              ReplyQueue;
 334         u8              SGList;
 335         __le16          SGTotal;
 336         __le64          tag;
 337         union LUNAddr     LUN;
 338 };
 339
 340 struct RequestBlock {
 341         u8   CDBLen;
 342         /*
 343          * type_attr_dir:
 344          * type: low 3 bits
 345          * attr: middle 3 bits
 346          * dir: high 2 bits
 347          */
 348         u8      type_attr_dir;
 349 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
 350                                 (((a) & 0x07) << 3) |\
 351                                 ((t) & 0x07))
 352 #define GET_TYPE(tad) ((tad) & 0x07)
 353 #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
 354 #define GET_DIR(tad) (((tad) >> 6) & 0x03)
 355         u16  Timeout;
 356         u8   CDB[16];
 357 };
 358
 359 struct ErrDescriptor {
 360         __le64 Addr;
 361         __le32 Len;
 362 };
 363
 364 struct SGDescriptor {
 365         __le64 Addr;
 366         __le32 Len;
 367         __le32 Ext;
 368 };
 369
 370 union MoreErrInfo {
 371         struct {
 372                 u8  Reserved[3];
 373                 u8  Type;
 374                 u32 ErrorInfo;
 375         } Common_Info;
 376         struct {
 377                 u8  Reserved[2];
 378                 u8  offense_size; /* size of offending entry */
 379                 u8  offense_num;  /* byte # of offense 0-base */
 380                 u32 offense_value;
 381         } Invalid_Cmd;
 382 };
 383 struct ErrorInfo {
 384         u8               ScsiStatus;
 385         u8               SenseLen;
 386         u16              CommandStatus;
 387         u32              ResidualCnt;
 388         union MoreErrInfo  MoreErrInfo;
 389         u8               SenseInfo[SENSEINFOBYTES];
 390 };
 391 /* Command types */
 392 #define CMD_IOCTL_PEND  0x01
 393 #define CMD_SCSI        0x03
 394 #define CMD_IOACCEL1    0x04
 395 #define CMD_IOACCEL2    0x05
 396 #define IOACCEL2_TMF    0x06
 397
 398 #define DIRECT_LOOKUP_SHIFT 4
 399 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
 400
 401 #define HPSA_ERROR_BIT          0x02
 402 struct ctlr_info; /* defined in hpsa.h */
 403 /* The size of this structure needs to be divisible by 128
 404  * on all architectures.  The low 4 bits of the addresses
 405  * are used as follows:
 406  *
 407  * bit 0: to device, used to indicate "performant mode" command
 408  *        from device, indidcates error status.
 409  * bit 1-3: to device, indicates block fetch table entry for
 410  *          reducing DMA in fetching commands from host memory.
 411  */
 412
 413 #define COMMANDLIST_ALIGNMENT 128
 414 struct CommandList {
 415         struct CommandListHeader Header;
 416         struct RequestBlock      Request;
 417         struct ErrDescriptor     ErrDesc;
 418         struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
 419         /* information associated with the command */
 420         u32                        busaddr; /* physical addr of this record */
 421         struct ErrorInfo *err_info; /* pointer to the allocated mem */
 422         struct ctlr_info           *h;
 423         int                        cmd_type;
 424         long                       cmdindex;
 425         struct completion *waiting;
 426         struct scsi_cmnd *scsi_cmd;
 427         struct work_struct work;
 428
 429         /*
 430          * For commands using either of the two "ioaccel" paths to
 431          * bypass the RAID stack and go directly to the physical disk
 432          * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
 433          * i/o is destined.  We need to store that here because the command
 434          * may potentially encounter TASK SET FULL and need to be resubmitted
 435          * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
 436          * not used.
 437          */
 438         struct hpsa_scsi_dev_t *phys_disk;
 439
 440         int abort_pending;
 441         struct hpsa_scsi_dev_t *reset_pending;
 442         atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
 443 } __aligned(COMMANDLIST_ALIGNMENT);
 444
 445 /* Max S/G elements in I/O accelerator command */
 446 #define IOACCEL1_MAXSGENTRIES           24
 447 #define IOACCEL2_MAXSGENTRIES           28
 448
 449 /*
 450  * Structure for I/O accelerator (mode 1) commands.
 451  * Note that this structure must be 128-byte aligned in size.
 452  */
 453 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
 454 struct io_accel1_cmd {
 455         __le16 dev_handle;              /* 0x00 - 0x01 */
 456         u8  reserved1;                  /* 0x02 */
 457         u8  function;                   /* 0x03 */
 458         u8  reserved2[8];               /* 0x04 - 0x0B */
 459         u32 err_info;                   /* 0x0C - 0x0F */
 460         u8  reserved3[2];               /* 0x10 - 0x11 */
 461         u8  err_info_len;               /* 0x12 */
 462         u8  reserved4;                  /* 0x13 */
 463         u8  sgl_offset;                 /* 0x14 */
 464         u8  reserved5[7];               /* 0x15 - 0x1B */
 465         __le32 transfer_len;            /* 0x1C - 0x1F */
 466         u8  reserved6[4];               /* 0x20 - 0x23 */
 467         __le16 io_flags;                /* 0x24 - 0x25 */
 468         u8  reserved7[14];              /* 0x26 - 0x33 */
 469         u8  LUN[8];                     /* 0x34 - 0x3B */
 470         __le32 control;                 /* 0x3C - 0x3F */
 471         u8  CDB[16];                    /* 0x40 - 0x4F */
 472         u8  reserved8[16];              /* 0x50 - 0x5F */
 473         __le16 host_context_flags;      /* 0x60 - 0x61 */
 474         __le16 timeout_sec;             /* 0x62 - 0x63 */
 475         u8  ReplyQueue;                 /* 0x64 */
 476         u8  reserved9[3];               /* 0x65 - 0x67 */
 477         __le64 tag;                     /* 0x68 - 0x6F */
 478         __le64 host_addr;               /* 0x70 - 0x77 */
 479         u8  CISS_LUN[8];                /* 0x78 - 0x7F */
 480         struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
 481 } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
 482
 483 #define IOACCEL1_FUNCTION_SCSIIO        0x00
 484 #define IOACCEL1_SGLOFFSET              32
 485
 486 #define IOACCEL1_IOFLAGS_IO_REQ         0x4000
 487 #define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
 488 #define IOACCEL1_IOFLAGS_CDBLEN_MAX     16
 489
 490 #define IOACCEL1_CONTROL_NODATAXFER     0x00000000
 491 #define IOACCEL1_CONTROL_DATA_OUT       0x01000000
 492 #define IOACCEL1_CONTROL_DATA_IN        0x02000000
 493 #define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
 494 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
 495 #define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
 496 #define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
 497 #define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
 498 #define IOACCEL1_CONTROL_ACA            0x00000400
 499
 500 #define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013
 501
 502 #define IOACCEL1_BUSADDR_CMDTYPE        0x00000060
 503
 504 struct ioaccel2_sg_element {
 505         __le64 address;
 506         __le32 length;
 507         u8 reserved[3];
 508         u8 chain_indicator;
 509 #define IOACCEL2_CHAIN 0x80
 510 };
 511
 512 /*
 513  * SCSI Response Format structure for IO Accelerator Mode 2
 514  */
 515 struct io_accel2_scsi_response {
 516         u8 IU_type;
 517 #define IOACCEL2_IU_TYPE_SRF                    0x60
 518         u8 reserved1[3];
 519         u8 req_id[4];           /* request identifier */
 520         u8 reserved2[4];
 521         u8 serv_response;               /* service response */
 522 #define IOACCEL2_SERV_RESPONSE_COMPLETE         0x000
 523 #define IOACCEL2_SERV_RESPONSE_FAILURE          0x001
 524 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE     0x002
 525 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS      0x003
 526 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED     0x004
 527 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN    0x005
 528         u8 status;                      /* status */
 529 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD       0x00
 530 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND   0x02
 531 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY       0x08
 532 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON    0x18
 533 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL   0x28
 534 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED    0x40
 535 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED     0x0E
 536 #define IOACCEL2_STATUS_SR_IO_ERROR             0x01
 537 #define IOACCEL2_STATUS_SR_IO_ABORTED           0x02
 538 #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE    0x03
 539 #define IOACCEL2_STATUS_SR_INVALID_DEVICE       0x04
 540 #define IOACCEL2_STATUS_SR_UNDERRUN             0x51
 541 #define IOACCEL2_STATUS_SR_OVERRUN              0x75
 542         u8 data_present;                /* low 2 bits */
 543 #define IOACCEL2_NO_DATAPRESENT         0x000
 544 #define IOACCEL2_RESPONSE_DATAPRESENT   0x001
 545 #define IOACCEL2_SENSE_DATA_PRESENT     0x002
 546 #define IOACCEL2_RESERVED               0x003
 547         u8 sense_data_len;              /* sense/response data length */
 548         u8 resid_cnt[4];                /* residual count */
 549         u8 sense_data_buff[32];         /* sense/response data buffer */
 550 };
 551
 552 /*
 553  * Structure for I/O accelerator (mode 2 or m2) commands.
 554  * Note that this structure must be 128-byte aligned in size.
 555  */
 556 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
 557 struct io_accel2_cmd {
 558         u8  IU_type;                    /* IU Type */
 559         u8  direction;                  /* direction, memtype, and encryption */
 560 #define IOACCEL2_DIRECTION_MASK         0x03 /* bits 0,1: direction  */
 561 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
 562                                              /*     0b=PCIe, 1b=DDR */
 563 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
 564                                              /*     0=off, 1=on */
 565         u8  reply_queue;                /* Reply Queue ID */
 566         u8  reserved1;                  /* Reserved */
 567         __le32 scsi_nexus;              /* Device Handle */
 568         __le32 Tag;                     /* cciss tag, lower 4 bytes only */
 569         __le32 tweak_lower;             /* Encryption tweak, lower 4 bytes */
 570         u8  cdb[16];                    /* SCSI Command Descriptor Block */
 571         u8  cciss_lun[8];               /* 8 byte SCSI address */
 572         __le32 data_len;                /* Total bytes to transfer */
 573         u8  cmd_priority_task_attr;     /* priority and task attrs */
 574 #define IOACCEL2_PRIORITY_MASK 0x78
 575 #define IOACCEL2_ATTR_MASK 0x07
 576         u8  sg_count;                   /* Number of sg elements */
 577         __le16 dekindex;                /* Data encryption key index */
 578         __le64 err_ptr;                 /* Error Pointer */
 579         __le32 err_len;                 /* Error Length*/
 580         __le32 tweak_upper;             /* Encryption tweak, upper 4 bytes */
 581         struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
 582         struct io_accel2_scsi_response error_data;
 583 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
 584
 585 /*
 586  * defines for Mode 2 command struct
 587  * FIXME: this can't be all I need mfm
 588  */
 589 #define IOACCEL2_IU_TYPE        0x40
 590 #define IOACCEL2_IU_TMF_TYPE    0x41
 591 #define IOACCEL2_DIR_NO_DATA    0x00
 592 #define IOACCEL2_DIR_DATA_IN    0x01
 593 #define IOACCEL2_DIR_DATA_OUT   0x02
 594 #define IOACCEL2_TMF_ABORT      0x01
 595 /*
 596  * SCSI Task Management Request format for Accelerator Mode 2
 597  */
 598 struct hpsa_tmf_struct {
 599         u8 iu_type;             /* Information Unit Type */
 600         u8 reply_queue;         /* Reply Queue ID */
 601         u8 tmf;                 /* Task Management Function */
 602         u8 reserved1;           /* byte 3 Reserved */
 603         __le32 it_nexus;        /* SCSI I-T Nexus */
 604         u8 lun_id[8];           /* LUN ID for TMF request */
 605         __le64 tag;             /* cciss tag associated w/ request */
 606         __le64 abort_tag;       /* cciss tag of SCSI cmd or TMF to abort */
 607         __le64 error_ptr;               /* Error Pointer */
 608         __le32 error_len;               /* Error Length */
 609 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
 610
 611 /* Configuration Table Structure */
 612 struct HostWrite {
 613         __le32          TransportRequest;
 614         __le32          command_pool_addr_hi;
 615         __le32          CoalIntDelay;
 616         __le32          CoalIntCount;
 617 };
 618
 619 #define SIMPLE_MODE     0x02
 620 #define PERFORMANT_MODE 0x04
 621 #define MEMQ_MODE       0x08
 622 #define IOACCEL_MODE_1  0x80
 623
 624 #define DRIVER_SUPPORT_UA_ENABLE        0x00000001
 625
 626 struct CfgTable {
 627         u8              Signature[4];
 628         __le32          SpecValence;
 629         __le32          TransportSupport;
 630         __le32          TransportActive;
 631         struct HostWrite HostWrite;
 632         __le32          CmdsOutMax;
 633         __le32          BusTypes;
 634         __le32          TransMethodOffset;
 635         u8              ServerName[16];
 636         __le32          HeartBeat;
 637         __le32          driver_support;
 638 #define                 ENABLE_SCSI_PREFETCH            0x100
 639 #define                 ENABLE_UNIT_ATTN                0x01
 640         __le32          MaxScatterGatherElements;
 641         __le32          MaxLogicalUnits;
 642         __le32          MaxPhysicalDevices;
 643         __le32          MaxPhysicalDrivesPerLogicalUnit;
 644         __le32          MaxPerformantModeCommands;
 645         __le32          MaxBlockFetch;
 646         __le32          PowerConservationSupport;
 647         __le32          PowerConservationEnable;
 648         __le32          TMFSupportFlags;
 649         u8              TMFTagMask[8];
 650         u8              reserved[0x78 - 0x70];
 651         __le32          misc_fw_support;                /* offset 0x78 */
 652 #define                 MISC_FW_DOORBELL_RESET          0x02
 653 #define                 MISC_FW_DOORBELL_RESET2         0x010
 654 #define                 MISC_FW_RAID_OFFLOAD_BASIC      0x020
 655 #define                 MISC_FW_EVENT_NOTIFY            0x080
 656         u8              driver_version[32];
 657         __le32          max_cached_write_size;
 658         u8              driver_scratchpad[16];
 659         __le32          max_error_info_length;
 660         __le32          io_accel_max_embedded_sg_count;
 661         __le32          io_accel_request_size_offset;
 662         __le32          event_notify;
 663 #define         HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
 664 #define         HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
 665         __le32          clear_event_notify;
 666 };
 667
 668 #define NUM_BLOCKFETCH_ENTRIES 8
 669 struct TransTable_struct {
 670         __le32          BlockFetch[NUM_BLOCKFETCH_ENTRIES];
 671         __le32          RepQSize;
 672         __le32          RepQCount;
 673         __le32          RepQCtrAddrLow32;
 674         __le32          RepQCtrAddrHigh32;
 675 #define MAX_REPLY_QUEUES 64
 676         struct vals32  RepQAddr[MAX_REPLY_QUEUES];
 677 };
 678
 679 struct hpsa_pci_info {
 680         unsigned char   bus;
 681         unsigned char   dev_fn;
 682         unsigned short  domain;
 683         u32             board_id;
 684 };
 685
 686 struct bmic_identify_controller {
 687         u8      configured_logical_drive_count; /* offset 0 */
 688         u8      pad1[153];
 689         __le16  extended_logical_unit_count;    /* offset 154 */
 690         u8      pad2[136];
 691         u8      controller_mode;        /* offset 292 */
 692         u8      pad3[32];
 693 };
 694
 695
 696 struct bmic_identify_physical_device {
 697         u8    scsi_bus;          /* SCSI Bus number on controller */
 698         u8    scsi_id;           /* SCSI ID on this bus */
 699         __le16 block_size;           /* sector size in bytes */
 700         __le32 total_blocks;         /* number for sectors on drive */
 701         __le32 reserved_blocks;   /* controller reserved (RIS) */
 702         u8    model[40];         /* Physical Drive Model */
 703         u8    serial_number[40]; /* Drive Serial Number */
 704         u8    firmware_revision[8]; /* drive firmware revision */
 705         u8    scsi_inquiry_bits; /* inquiry byte 7 bits */
 706         u8    compaq_drive_stamp; /* 0 means drive not stamped */
 707         u8    last_failure_reason;
 708 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG              0x01
 709 #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS                     0x02
 710 #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS                      0x03
 711 #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND                    0x04
 712 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED                       0x05
 713 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP       0x06
 714 #define BMIC_LAST_FAILURE_TIMEOUT                               0x07
 715 #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED                      0x08
 716 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1                        0x09
 717 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2                        0x0a
 718 #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE                   0x0b
 719 #define BMIC_LAST_FAILURE_NOT_READY                             0x0c
 720 #define BMIC_LAST_FAILURE_HARDWARE_ERROR                        0x0d
 721 #define BMIC_LAST_FAILURE_ABORTED_COMMAND                       0x0e
 722 #define BMIC_LAST_FAILURE_WRITE_PROTECTED                       0x0f
 723 #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER            0x10
 724 #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR                   0x11
 725 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG                 0x12
 726 #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED            0x13
 727 #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG                   0x14
 728 #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED             0x15
 729 #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED                0x16
 730 #define BMIC_LAST_FAILURE_INQUIRY_FAILED                        0x17
 731 #define BMIC_LAST_FAILURE_NON_DISK_DEVICE                       0x18
 732 #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED                  0x19
 733 #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE                    0x1a
 734 #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED         0x1b
 735 #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED            0x1c
 736 #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP               0x1d
 737 #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED           0x1e
 738 #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR                  0x1f
 739 #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS                   0x20
 740 #define BMIC_LAST_FAILURE_WRONG_REPLACE                         0x21
 741 #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED                0x22
 742 #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED                 0x23
 743 #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE               0x24
 744 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG            0x25
 745 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG            0x26
 746 #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED               0x27
 747 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY                   0x28
 748 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED                0x29
 749 #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY                 0x2a
 750 #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED                  0x2b
 751
 752 #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED                  0x37
 753 #define BMIC_LAST_FAILURE_PHY_RESET_FAILED                      0x38
 754 #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE           0x40
 755 #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED                      0x41
 756 #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT                0x42
 757 #define BMIC_LAST_FAILURE_OFFLINE_ERASE                         0x80
 758 #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL                     0x81
 759 #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX                0x82
 760 #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE                0x83
 761
 762         u8     flags;
 763         u8     more_flags;
 764         u8     scsi_lun;          /* SCSI LUN for phys drive */
 765         u8     yet_more_flags;
 766         u8     even_more_flags;
 767         __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
 768         u8     phys_connector[2];         /* connector number on controller */
 769         u8     phys_box_on_bus;  /* phys enclosure this drive resides */
 770         u8     phys_bay_in_box;  /* phys drv bay this drive resides */
 771         __le32 rpm;              /* Drive rotational speed in rpm */
 772         u8     device_type;       /* type of drive */
 773         u8     sata_version;     /* only valid when drive_type is SATA */
 774         __le64 big_total_block_count;
 775         __le64 ris_starting_lba;
 776         __le32 ris_size;
 777         u8     wwid[20];
 778         u8     controller_phy_map[32];
 779         __le16 phy_count;
 780         u8     phy_connected_dev_type[256];
 781         u8     phy_to_drive_bay_num[256];
 782         __le16 phy_to_attached_dev_index[256];
 783         u8     box_index;
 784         u8     reserved;
 785         __le16 extra_physical_drive_flags;
 786 #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
 787         (idphydrv->extra_physical_drive_flags & (1 << 10))
 788         u8     negotiated_link_rate[256];
 789         u8     phy_to_phy_map[256];
 790         u8     redundant_path_present_map;
 791         u8     redundant_path_failure_map;
 792         u8     active_path_number;
 793         __le16 alternate_paths_phys_connector[8];
 794         u8     alternate_paths_phys_box_on_port[8];
 795         u8     multi_lun_device_lun_count;
 796         u8     minimum_good_fw_revision[8];
 797         u8     unique_inquiry_bytes[20];
 798         u8     current_temperature_degreesC;
 799         u8     temperature_threshold_degreesC;
 800         u8     max_temperature_degreesC;
 801         u8     logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
 802         __le16 current_queue_depth_limit;
 803         u8     switch_name[10];
 804         __le16 switch_port;
 805         u8     alternate_paths_switch_name[40];
 806         u8     alternate_paths_switch_port[8];
 807         __le16 power_on_hours; /* valid only if gas gauge supported */
 808         __le16 percent_endurance_used; /* valid only if gas gauge supported. */
 809 #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
 810         ((idphydrv->percent_endurance_used & 0x80) || \
 811          (idphydrv->percent_endurance_used > 10000))
 812         u8     drive_authentication;
 813 #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
 814         (idphydrv->drive_authentication == 0x80)
 815         u8     smart_carrier_authentication;
 816 #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
 817         (idphydrv->smart_carrier_authentication != 0x0)
 818 #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
 819         (idphydrv->smart_carrier_authentication == 0x01)
 820         u8     smart_carrier_app_fw_version;
 821         u8     smart_carrier_bootloader_fw_version;
 822         u8     encryption_key_name[64];
 823         __le32 misc_drive_flags;
 824         __le16 dek_index;
 825         u8     padding[112];
 826 };
 827
 828 #pragma pack()
 829 #endif /* HPSA_CMD_H */