2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
21 #include <scsi/scsicam.h>
28 struct access_method {
29 void (*submit_command)(struct ctlr_info *h,
30 struct CommandList *c);
31 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
32 bool (*intr_pending)(struct ctlr_info *h);
33 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
36 struct hpsa_scsi_dev_t {
38 int bus, target, lun; /* as presented to the OS */
39 unsigned char scsi3addr[8]; /* as presented to the HW */
40 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
41 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
42 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
43 unsigned char model[16]; /* bytes 16-31 of inquiry data */
44 unsigned char raid_level; /* from inquiry page 0xC1 */
45 unsigned char volume_offline; /* discovered via TUR or VPD */
46 u16 queue_depth; /* max queue_depth for this device */
47 atomic_t reset_cmds_out; /* Count of commands to-be affected */
48 atomic_t ioaccel_cmds_out; /* Only used for physical devices
49 * counts commands sent to physical
50 * device via "ioaccel" path.
57 u16 phys_connector[8];
58 int offload_config; /* I/O accel RAID offload configured */
59 int offload_enabled; /* I/O accel RAID offload enabled */
60 int offload_to_be_enabled;
61 int hba_ioaccel_enabled;
62 int offload_to_mirror; /* Send next I/O accelerator RAID
63 * offload request to mirror drive
65 struct raid_map_data raid_map; /* I/O accelerator RAID map */
68 * Pointers from logical drive map indices to the phys drives that
69 * make those logical drives. Note, multiple logical drives may
70 * share physical drives. You can have for instance 5 physical
71 * drives with 3 logical drives each using those same 5 physical
72 * disks. We need these pointers for counting i/o's out to physical
73 * devices in order to honor physical device queue depth limits.
75 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
78 #define HPSA_DO_NOT_EXPOSE 0x0
79 #define HPSA_SG_ATTACH 0x1
80 #define HPSA_ULD_ATTACH 0x2
81 #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH)
85 struct reply_queue_buffer {
94 struct bmic_controller_parameters {
96 u8 enable_command_list_verification;
97 u8 backed_out_write_drives;
98 u16 stripes_for_parity;
99 u8 parity_distribution_mode_flags;
100 u16 max_driver_requests;
101 u16 elevator_trend_count;
103 u8 force_scan_complete;
104 u8 scsi_transfer_mode;
108 u8 host_sdb_asic_fix;
109 u8 pdpi_burst_from_host_disabled;
110 char software_name[64];
111 char hardware_name[32];
113 u8 snapshot_priority;
115 u8 post_prompt_timeout;
116 u8 automatic_drive_slamming;
119 u8 cache_nvram_flags;
120 u8 drive_config_flags;
122 u8 temp_warning_level;
123 u8 temp_shutdown_level;
124 u8 temp_condition_reset;
125 u8 max_coalesce_commands;
126 u32 max_coalesce_delay;
137 struct pci_dev *pdev;
141 int nr_cmds; /* Number of commands allowed on this controller */
142 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
143 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
144 struct CfgTable __iomem *cfgtable;
145 int interrupts_enabled;
147 atomic_t commands_outstanding;
148 # define PERF_MODE_INT 0
149 # define DOORBELL_INT 1
150 # define SIMPLE_MODE_INT 2
151 # define MEMQ_MODE_INT 3
152 unsigned int intr[MAX_REPLY_QUEUES];
153 unsigned int msix_vector;
154 unsigned int msi_vector;
155 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
156 struct access_method access;
158 /* queue and queue Info */
163 u8 max_cmd_sg_entries;
165 struct SGDescriptor **cmd_sg_list;
166 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
168 /* pointers to command and error info pool */
169 struct CommandList *cmd_pool;
170 dma_addr_t cmd_pool_dhandle;
171 struct io_accel1_cmd *ioaccel_cmd_pool;
172 dma_addr_t ioaccel_cmd_pool_dhandle;
173 struct io_accel2_cmd *ioaccel2_cmd_pool;
174 dma_addr_t ioaccel2_cmd_pool_dhandle;
175 struct ErrorInfo *errinfo_pool;
176 dma_addr_t errinfo_pool_dhandle;
177 unsigned long *cmd_pool_bits;
179 spinlock_t scan_lock;
180 wait_queue_head_t scan_wait_queue;
182 struct Scsi_Host *scsi_host;
183 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
184 int ndevices; /* number of used elements in .dev[] array. */
185 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
187 * Performant mode tables.
191 struct TransTable_struct __iomem *transtable;
192 unsigned long transMethod;
194 /* cap concurrent passthrus at some reasonable maximum */
195 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
196 atomic_t passthru_cmds_avail;
199 * Performant mode completion buffers
201 size_t reply_queue_size;
202 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
204 u32 *blockFetchTable;
205 u32 *ioaccel1_blockFetchTable;
206 u32 *ioaccel2_blockFetchTable;
207 u32 __iomem *ioaccel2_bft2_regs;
208 unsigned char *hba_inquiry_data;
213 u64 last_intr_timestamp;
215 u64 last_heartbeat_timestamp;
216 u32 heartbeat_sample_interval;
217 atomic_t firmware_flash_in_progress;
218 u32 __percpu *lockup_detected;
219 struct delayed_work monitor_ctlr_work;
220 struct delayed_work rescan_ctlr_work;
221 int remove_in_progress;
222 /* Address of h->q[x] is passed to intr handler to know which queue */
223 u8 q[MAX_REPLY_QUEUES];
224 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
225 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
226 #define HPSATMF_BITS_SUPPORTED (1 << 0)
227 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
228 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
229 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
230 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
231 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
232 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
233 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
234 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
235 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
236 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
237 #define HPSATMF_MASK_SUPPORTED (1 << 16)
238 #define HPSATMF_LOG_LUN_RESET (1 << 17)
239 #define HPSATMF_LOG_NEX_RESET (1 << 18)
240 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
241 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
242 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
243 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
244 #define HPSATMF_LOG_QRY_TASK (1 << 23)
245 #define HPSATMF_LOG_QRY_TSET (1 << 24)
246 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
248 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
249 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
250 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
251 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
252 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
253 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
254 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
256 #define RESCAN_REQUIRED_EVENT_BITS \
257 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
258 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
259 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
260 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
261 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
262 spinlock_t offline_device_lock;
263 struct list_head offline_device_list;
264 int acciopath_status;
266 int raid_offload_debug;
267 int needs_abort_tags_swizzled;
268 struct workqueue_struct *resubmit_wq;
269 struct workqueue_struct *rescan_ctlr_wq;
270 atomic_t abort_cmds_available;
271 wait_queue_head_t abort_cmd_wait_queue;
272 wait_queue_head_t event_sync_wait_queue;
273 struct mutex reset_mutex;
274 u8 reset_in_progress;
277 struct offline_device_entry {
278 unsigned char scsi3addr[8];
279 struct list_head offline_list;
282 #define HPSA_ABORT_MSG 0
283 #define HPSA_DEVICE_RESET_MSG 1
284 #define HPSA_RESET_TYPE_CONTROLLER 0x00
285 #define HPSA_RESET_TYPE_BUS 0x01
286 #define HPSA_RESET_TYPE_TARGET 0x03
287 #define HPSA_RESET_TYPE_LUN 0x04
288 #define HPSA_MSG_SEND_RETRY_LIMIT 10
289 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
291 /* Maximum time in seconds driver will wait for command completions
292 * when polling before giving up.
294 #define HPSA_MAX_POLL_TIME_SECS (20)
296 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
297 * how many times to retry TEST UNIT READY on a device
298 * while waiting for it to become ready before giving up.
299 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
300 * between sending TURs while waiting for a device
303 #define HPSA_TUR_RETRY_LIMIT (20)
304 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
306 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
307 * to become ready, in seconds, before giving up on it.
308 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
309 * between polling the board to see if it is ready, in
310 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
311 * HPSA_BOARD_READY_ITERATIONS are derived from those.
313 #define HPSA_BOARD_READY_WAIT_SECS (120)
314 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
315 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
316 #define HPSA_BOARD_READY_POLL_INTERVAL \
317 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
318 #define HPSA_BOARD_READY_ITERATIONS \
319 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
320 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
321 #define HPSA_BOARD_NOT_READY_ITERATIONS \
322 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
323 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
324 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
325 #define HPSA_POST_RESET_NOOP_RETRIES (12)
327 /* Defining the diffent access_menthods */
329 * Memory mapped FIFO interface (SMART 53xx cards)
331 #define SA5_DOORBELL 0x20
332 #define SA5_REQUEST_PORT_OFFSET 0x40
333 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
334 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
335 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
336 #define SA5_REPLY_PORT_OFFSET 0x44
337 #define SA5_INTR_STATUS 0x30
338 #define SA5_SCRATCHPAD_OFFSET 0xB0
340 #define SA5_CTCFG_OFFSET 0xB4
341 #define SA5_CTMEM_OFFSET 0xB8
343 #define SA5_INTR_OFF 0x08
344 #define SA5B_INTR_OFF 0x04
345 #define SA5_INTR_PENDING 0x08
346 #define SA5B_INTR_PENDING 0x04
347 #define FIFO_EMPTY 0xffffffff
348 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
350 #define HPSA_ERROR_BIT 0x02
352 /* Performant mode flags */
353 #define SA5_PERF_INTR_PENDING 0x04
354 #define SA5_PERF_INTR_OFF 0x05
355 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
356 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
357 #define SA5_OUTDB_CLEAR 0xA0
358 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
359 #define SA5_OUTDB_STATUS 0x9C
362 #define HPSA_INTR_ON 1
363 #define HPSA_INTR_OFF 0
366 * Inbound Post Queue offsets for IO Accelerator Mode 2
368 #define IOACCEL2_INBOUND_POSTQ_32 0x48
369 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
370 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
373 Send the command to the hardware
375 static void SA5_submit_command(struct ctlr_info *h,
376 struct CommandList *c)
378 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
379 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
382 static void SA5_submit_command_no_read(struct ctlr_info *h,
383 struct CommandList *c)
385 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
388 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
389 struct CommandList *c)
391 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
395 * This card is the opposite of the other cards.
396 * 0 turns interrupts on...
397 * 0x08 turns them off...
399 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
401 if (val) { /* Turn interrupts on */
402 h->interrupts_enabled = 1;
403 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
404 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
405 } else { /* Turn them off */
406 h->interrupts_enabled = 0;
408 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
409 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
413 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
415 if (val) { /* turn on interrupts */
416 h->interrupts_enabled = 1;
417 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
418 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
420 h->interrupts_enabled = 0;
421 writel(SA5_PERF_INTR_OFF,
422 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
423 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
427 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
429 struct reply_queue_buffer *rq = &h->reply_queue[q];
430 unsigned long register_value = FIFO_EMPTY;
432 /* msi auto clears the interrupt pending bit. */
433 if (unlikely(!(h->msi_vector || h->msix_vector))) {
434 /* flush the controller write of the reply queue by reading
435 * outbound doorbell status register.
437 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
438 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
439 /* Do a read in order to flush the write to the controller
442 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
445 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
446 register_value = rq->head[rq->current_entry];
448 atomic_dec(&h->commands_outstanding);
450 register_value = FIFO_EMPTY;
452 /* Check for wraparound */
453 if (rq->current_entry == h->max_commands) {
454 rq->current_entry = 0;
457 return register_value;
461 * returns value read from hardware.
462 * returns FIFO_EMPTY if there is nothing to read
464 static unsigned long SA5_completed(struct ctlr_info *h,
465 __attribute__((unused)) u8 q)
467 unsigned long register_value
468 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
470 if (register_value != FIFO_EMPTY)
471 atomic_dec(&h->commands_outstanding);
474 if (register_value != FIFO_EMPTY)
475 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
478 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
481 return register_value;
484 * Returns true if an interrupt is pending..
486 static bool SA5_intr_pending(struct ctlr_info *h)
488 unsigned long register_value =
489 readl(h->vaddr + SA5_INTR_STATUS);
490 return register_value & SA5_INTR_PENDING;
493 static bool SA5_performant_intr_pending(struct ctlr_info *h)
495 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
500 /* Read outbound doorbell to flush */
501 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
502 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
505 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
507 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
509 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
511 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
515 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
516 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
517 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
518 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
520 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
523 struct reply_queue_buffer *rq = &h->reply_queue[q];
525 BUG_ON(q >= h->nreply_queues);
527 register_value = rq->head[rq->current_entry];
528 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
529 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
530 if (++rq->current_entry == rq->size)
531 rq->current_entry = 0;
535 * Don't really need to write the new index after each command,
536 * but with current driver design this is easiest.
539 writel((q << 24) | rq->current_entry, h->vaddr +
540 IOACCEL_MODE1_CONSUMER_INDEX);
541 atomic_dec(&h->commands_outstanding);
543 return (unsigned long) register_value;
546 static struct access_method SA5_access = {
553 static struct access_method SA5_ioaccel_mode1_access = {
555 SA5_performant_intr_mask,
556 SA5_ioaccel_mode1_intr_pending,
557 SA5_ioaccel_mode1_completed,
560 static struct access_method SA5_ioaccel_mode2_access = {
561 SA5_submit_command_ioaccel2,
562 SA5_performant_intr_mask,
563 SA5_performant_intr_pending,
564 SA5_performant_completed,
567 static struct access_method SA5_performant_access = {
569 SA5_performant_intr_mask,
570 SA5_performant_intr_pending,
571 SA5_performant_completed,
574 static struct access_method SA5_performant_access_no_read = {
575 SA5_submit_command_no_read,
576 SA5_performant_intr_mask,
577 SA5_performant_intr_pending,
578 SA5_performant_completed,
584 struct access_method *access;