2 * This file is part of the Chelsio FCoE driver for Linux.
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef __CSIO_HW_CHIP_H__
35 #define __CSIO_HW_CHIP_H__
37 #include "csio_defs.h"
39 /* Define MACRO values */
40 #define CSIO_HW_T4 0x4000
41 #define CSIO_T4_FCOE_ASIC 0x4600
42 #define CSIO_HW_T5 0x5000
43 #define CSIO_T5_FCOE_ASIC 0x5600
44 #define CSIO_HW_CHIP_MASK 0xF000
46 #define T4_REGMAP_SIZE (160 * 1024)
47 #define T5_REGMAP_SIZE (332 * 1024)
48 #define FW_FNAME_T4 "cxgb4/t4fw.bin"
49 #define FW_FNAME_T5 "cxgb4/t5fw.bin"
50 #define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
51 #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
53 #define T4FW_VERSION_MAJOR 0x01
54 #define T4FW_VERSION_MINOR 0x0B
55 #define T4FW_VERSION_MICRO 0x1B
56 #define T4FW_VERSION_BUILD 0x00
58 #define T5FW_VERSION_MAJOR 0x01
59 #define T5FW_VERSION_MINOR 0x0B
60 #define T5FW_VERSION_MICRO 0x1B
61 #define T5FW_VERSION_BUILD 0x00
63 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
64 #define CHELSIO_CHIP_FPGA 0x100
65 #define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
66 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
68 #define CHELSIO_T4 0x4
69 #define CHELSIO_T5 0x5
72 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
73 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
77 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
78 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
83 /* Define static functions */
84 static inline int csio_is_t4(uint16_t chip)
86 return (chip == CSIO_HW_T4);
89 static inline int csio_is_t5(uint16_t chip)
91 return (chip == CSIO_HW_T5);
94 /* Define MACRO DEFINITIONS */
95 #define CSIO_DEVICE(devid, idx) \
96 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
98 #define CSIO_HW_PIDX(hw, index) \
99 (csio_is_t4(hw->chip_id) ? (PIDX_V(index)) : \
100 (PIDX_T5_G(index) | DBTYPE_F))
102 #define CSIO_HW_LP_INT_THRESH(hw, val) \
103 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \
104 (LP_INT_THRESH_T5_V(val)))
106 #define CSIO_HW_M_LP_INT_THRESH(hw) \
107 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
109 #define CSIO_MAC_INT_CAUSE_REG(hw, port) \
110 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \
111 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)))
113 #include "t4fw_api.h"
115 #define FW_VERSION(chip) ( \
116 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
117 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
118 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
119 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
120 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
126 struct fw_hdr fw_hdr;
128 #define CSIO_FW_FNAME(hw) \
129 (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
131 #define CSIO_CF_FNAME(hw) \
132 (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
135 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
138 MEMWIN_APERTURE = 2048,
139 MEMWIN_BASE = 0x1b800,
140 MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
143 /* Slow path handlers */
145 unsigned int mask; /* bits to check in interrupt status */
146 const char *msg; /* message to print or NULL */
147 short stat_idx; /* stat counter to increment or -1 */
148 unsigned short fatal; /* whether the condition reported is fatal */
151 /* T4/T5 Chip specific ops */
153 struct csio_hw_chip_ops {
154 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
155 void (*chip_pcie_intr_handler)(struct csio_hw *);
156 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
157 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
158 __be32 *, uint64_t *);
159 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
160 __be32 *, uint64_t *);
161 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
162 u32, uint32_t *, int);
163 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
166 extern struct csio_hw_chip_ops t4_ops;
167 extern struct csio_hw_chip_ops t5_ops;
169 #endif /* #ifndef __CSIO_HW_CHIP_H__ */