2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
12 * Contact Information:
13 * linux-drivers@serverengines.com
16 * 209 N. Fair Oaks Ave
21 #ifndef _BEISCSI_MAIN_
22 #define _BEISCSI_MAIN_
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/if_ether.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <scsi/scsi_device.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/iscsi_proto.h>
33 #include <scsi/libiscsi.h>
34 #include <scsi/scsi_transport_iscsi.h>
37 #define DRV_NAME "be2iscsi"
38 #define BUILD_STR "2.0.527.0"
39 #define BE_NAME "ServerEngines BladeEngine2" \
40 "Linux iSCSI Driver version" BUILD_STR
41 #define DRV_DESC BE_NAME " " "Driver"
43 #define BE_VENDOR_ID 0x19A2
44 /* DEVICE ID's for BE2 */
45 #define BE_DEVICE_ID1 0x212
46 #define OC_DEVICE_ID1 0x702
47 #define OC_DEVICE_ID2 0x703
49 /* DEVICE ID's for BE3 */
50 #define BE_DEVICE_ID2 0x222
51 #define OC_DEVICE_ID3 0x712
53 #define BE2_IO_DEPTH 1024
54 #define BE2_MAX_SESSIONS 256
55 #define BE2_CMDS_PER_CXN 128
57 #define BE2_NOPOUT_REQ 16
59 #define BE2_DEFPDU_HDR_SZ 64
60 #define BE2_DEFPDU_DATA_SZ 8192
63 #define BEISCSI_SGLIST_ELEMENTS 30
65 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
66 #define BEISCSI_MAX_SECTORS 256 /* scsi_host->max_sectors */
68 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
69 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
70 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
71 #define BEISCSI_MAX_FRAGS_INIT 192
72 #define BE_NUM_MSIX_ENTRIES 1
74 #define MPU_EP_CONTROL 0
75 #define MPU_EP_SEMAPHORE 0xac
76 #define BE2_SOFT_RESET 0x5c
77 #define BE2_PCI_ONLINE0 0xb0
78 #define BE2_PCI_ONLINE1 0xb4
79 #define BE2_SET_RESET 0x80
80 #define BE2_MPU_IRAM_ONLINE 0x00000080
82 #define BE_SENSE_INFO_SIZE 258
83 #define BE_ISCSI_PDU_HEADER_SIZE 64
84 #define BE_MIN_MEM_SIZE 16384
85 #define MAX_CMD_SZ 65536
86 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
88 #define DBG_LVL 0x00000001
89 #define DBG_LVL_1 0x00000001
90 #define DBG_LVL_2 0x00000002
91 #define DBG_LVL_3 0x00000004
92 #define DBG_LVL_4 0x00000008
93 #define DBG_LVL_5 0x00000010
94 #define DBG_LVL_6 0x00000020
95 #define DBG_LVL_7 0x00000040
96 #define DBG_LVL_8 0x00000080
98 #define SE_DEBUG(debug_mask, fmt, args...) \
100 if (debug_mask & DBG_LVL) { \
101 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
102 printk(fmt, ##args); \
106 #define BE_ADAPTER_UP 0x00000000
107 #define BE_ADAPTER_LINK_DOWN 0x00000001
109 * hardware needs the async PDU buffers to be posted in multiples of 8
110 * So have atleast 8 of them by default
113 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
115 /********* Memory BAR register ************/
116 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
118 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
119 * Disable" may still globally block interrupts in addition to individual
120 * interrupt masks; a mechanism for the device driver to block all interrupts
121 * atomically without having to arbitrate for the PCI Interrupt Disable bit
124 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
126 /********* ISR0 Register offset **********/
127 #define CEV_ISR0_OFFSET 0xC18
128 #define CEV_ISR_SIZE 4
131 * Macros for reading/writing a protection domain or CSR registers
135 #define DB_TXULP0_OFFSET 0x40
136 #define DB_RXULP0_OFFSET 0xA0
137 /********* Event Q door bell *************/
138 #define DB_EQ_OFFSET DB_CQ_OFFSET
139 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
140 /* Clear the interrupt for this eq */
141 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
143 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
144 /* Number of event entries processed */
145 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
147 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
149 /********* Compl Q door bell *************/
150 #define DB_CQ_OFFSET 0x120
151 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
152 /* Number of event entries processed */
153 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
155 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
157 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
158 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
159 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
160 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
161 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
163 #define PAGES_REQUIRED(x) \
164 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
167 HWI_MEM_ADDN_CONTEXT,
172 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
173 HWI_MEM_ASYNC_DATA_BUF,
174 HWI_MEM_ASYNC_HEADER_RING,
175 HWI_MEM_ASYNC_DATA_RING,
176 HWI_MEM_ASYNC_HEADER_HANDLE,
177 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
178 HWI_MEM_ASYNC_PDU_CONTEXT,
179 ISCSI_MEM_GLOBAL_HEADER,
183 struct be_bus_address32 {
184 unsigned int address_lo;
185 unsigned int address_hi;
188 struct be_bus_address64 {
189 unsigned long long address;
192 struct be_bus_address {
194 struct be_bus_address32 a32;
195 struct be_bus_address64 a64;
200 struct be_bus_address bus_address; /* Bus address of location */
201 void *virtual_address; /* virtual address to the location */
202 unsigned int size; /* Size required by memory block */
205 struct be_mem_descriptor {
206 unsigned int index; /* Index of this memory parameter */
207 unsigned int category; /* type indicates cached/non-cached */
208 unsigned int num_elements; /* number of elements in this
211 unsigned int alignment_mask; /* Alignment mask for this block */
212 unsigned int size_in_bytes; /* Size required by memory block */
213 struct mem_array *mem_array;
217 unsigned int sgl_index;
220 struct iscsi_task *task;
221 struct iscsi_sge *pfrag;
224 struct hba_parameters {
225 unsigned int ios_per_ctrl;
226 unsigned int cxns_per_ctrl;
227 unsigned int asyncpdus_per_ctrl;
228 unsigned int icds_per_ctrl;
229 unsigned int num_sge_per_io;
230 unsigned int defpdu_hdr_sz;
231 unsigned int defpdu_data_sz;
232 unsigned int num_cq_entries;
233 unsigned int num_eq_entries;
234 unsigned int wrbs_per_cxn;
235 unsigned int crashmode;
236 unsigned int hba_num;
238 unsigned int mgmt_ws_sz;
239 unsigned int hwi_ws_sz;
244 unsigned int dbg_flags;
245 unsigned int num_cxn;
247 unsigned int eq_timer;
249 * These are calculated from other params. They're here
252 unsigned int num_mcc_pages;
253 unsigned int num_mcc_cq_pages;
254 unsigned int num_cq_pages;
255 unsigned int num_eq_pages;
257 unsigned int num_async_pdu_buf_pages;
258 unsigned int num_async_pdu_buf_sgl_pages;
259 unsigned int num_async_pdu_buf_cq_pages;
261 unsigned int num_async_pdu_hdr_pages;
262 unsigned int num_async_pdu_hdr_sgl_pages;
263 unsigned int num_async_pdu_hdr_cq_pages;
265 unsigned int num_sge;
268 struct invalidate_command_table {
274 struct hba_parameters params;
275 struct hwi_controller *phwi_ctrlr;
276 unsigned int mem_req[SE_MEM_MAX];
277 /* PCI BAR mapped addresses */
278 u8 __iomem *csr_va; /* CSR */
279 u8 __iomem *db_va; /* Door Bell */
280 u8 __iomem *pci_va; /* PCI Config */
281 struct be_bus_address csr_pa; /* CSR */
282 struct be_bus_address db_pa; /* CSR */
283 struct be_bus_address pci_pa; /* CSR */
284 /* PCI representation of our HBA */
285 struct pci_dev *pcidev;
287 unsigned short asic_revision;
288 unsigned int num_cpus;
289 unsigned int nxt_cqid;
290 struct msix_entry msix_entries[MAX_CPUS + 1];
292 struct be_mem_descriptor *init_mem;
294 unsigned short io_sgl_alloc_index;
295 unsigned short io_sgl_free_index;
296 unsigned short io_sgl_hndl_avbl;
297 struct sgl_handle **io_sgl_hndl_base;
298 struct sgl_handle **sgl_hndl_array;
300 unsigned short eh_sgl_alloc_index;
301 unsigned short eh_sgl_free_index;
302 unsigned short eh_sgl_hndl_avbl;
303 struct sgl_handle **eh_sgl_hndl_base;
304 spinlock_t io_sgl_lock;
305 spinlock_t mgmt_sgl_lock;
308 unsigned short avlbl_cids;
309 unsigned short cid_alloc;
310 unsigned short cid_free;
311 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
312 struct list_head hba_queue;
313 unsigned short *cid_array;
314 struct iscsi_endpoint **ep_array;
315 struct Scsi_Host *shost;
318 * group together since they are used most frequently
319 * for cid to cri conversion
321 unsigned int iscsi_cid_start;
322 unsigned int phys_port;
324 unsigned int isr_offset;
325 unsigned int iscsi_icd_start;
326 unsigned int iscsi_cid_count;
327 unsigned int iscsi_icd_count;
328 unsigned int pci_function;
330 unsigned short cid_alloc;
331 unsigned short cid_free;
332 unsigned short avlbl_cids;
333 unsigned short iscsi_features;
337 u8 mac_address[ETH_ALEN];
338 unsigned short todo_cq;
339 unsigned short todo_mcc_cq;
341 struct workqueue_struct *wq; /* The actuak work queue */
342 struct work_struct work_cqs; /* The work being queued */
343 struct be_ctrl_info ctrl;
344 unsigned int generation;
345 struct invalidate_command_table inv_tbl[128];
349 struct beiscsi_session {
350 struct pci_pool *bhs_pool;
354 * struct beiscsi_conn - iscsi connection structure
356 struct beiscsi_conn {
357 struct iscsi_conn *conn;
358 struct beiscsi_hba *phba;
360 u32 beiscsi_conn_cid;
361 struct beiscsi_endpoint *ep;
362 unsigned short login_in_progress;
363 struct wrb_handle *plogin_wrb_handle;
364 struct sgl_handle *plogin_sgl_handle;
365 struct beiscsi_session *beiscsi_sess;
366 struct iscsi_task *task;
369 /* This structure is used by the chip */
370 struct pdu_data_out {
374 * Pseudo amap definition in which each bit of the actual structure is defined
375 * as a byte: used to calculate offset/shift/mask of each field
377 struct amap_pdu_data_out {
378 u8 opcode[6]; /* opcode */
379 u8 rsvd0[2]; /* should be 0 */
381 u8 final_bit; /* F bit */
383 u8 ahs_length[8]; /* no AHS */
385 u8 data_len_lo[16]; /* DataSegmentLength */
387 u8 itt[32]; /* ITT; initiator task tag */
388 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
393 u8 buffer_offset[32];
398 struct iscsi_cmd iscsi_hdr;
399 unsigned char pad1[16];
400 struct pdu_data_out iscsi_data_pdu;
401 unsigned char pad2[BE_SENSE_INFO_SIZE -
402 sizeof(struct pdu_data_out)];
405 struct beiscsi_io_task {
406 struct wrb_handle *pwrb_handle;
407 struct sgl_handle *psgl_handle;
408 struct beiscsi_conn *conn;
409 struct scsi_cmnd *scsi_cmnd;
413 unsigned short header_len;
415 struct be_cmd_bhs *cmd_bhs;
416 struct be_bus_address bhs_pa;
417 unsigned short bhs_len;
420 struct be_nonio_bhs {
421 struct iscsi_hdr iscsi_hdr;
422 unsigned char pad1[16];
423 struct pdu_data_out iscsi_data_pdu;
424 unsigned char pad2[BE_SENSE_INFO_SIZE -
425 sizeof(struct pdu_data_out)];
428 struct be_status_bhs {
429 struct iscsi_cmd iscsi_hdr;
430 unsigned char pad1[16];
432 * The plus 2 below is to hold the sense info length that gets
435 unsigned char sense_info[BE_SENSE_INFO_SIZE];
443 * Pseudo amap definition in which each bit of the actual structure is defined
444 * as a byte: used to calculate offset/shift/mask of each field
446 struct amap_iscsi_sge {
449 u8 sge_offset[22]; /* DWORD 2 */
450 u8 rsvd0[9]; /* DWORD 2 */
451 u8 last_sge; /* DWORD 2 */
452 u8 len[17]; /* DWORD 3 */
453 u8 rsvd1[15]; /* DWORD 3 */
456 struct beiscsi_offload_params {
460 #define OFFLD_PARAMS_ERL 0x00000003
461 #define OFFLD_PARAMS_DDE 0x00000004
462 #define OFFLD_PARAMS_HDE 0x00000008
463 #define OFFLD_PARAMS_IR2T 0x00000010
464 #define OFFLD_PARAMS_IMD 0x00000020
467 * Pseudo amap definition in which each bit of the actual structure is defined
468 * as a byte: used to calculate offset/shift/mask of each field
470 struct amap_beiscsi_offload_params {
471 u8 max_burst_length[32];
472 u8 max_send_data_segment_length[32];
473 u8 first_burst_length[32];
483 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
484 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
486 struct async_pdu_handle {
487 struct list_head link;
488 struct be_bus_address pa;
490 unsigned int consumed;
492 unsigned char is_header;
494 unsigned long buffer_len;
497 struct hwi_async_entry {
499 unsigned char hdr_received;
500 unsigned char hdr_len;
501 unsigned short bytes_received;
502 unsigned int bytes_needed;
503 struct list_head list;
506 struct list_head header_busy_list;
507 struct list_head data_busy_list;
510 struct hwi_async_pdu_context {
512 struct be_bus_address pa_base;
515 struct async_pdu_handle *handle_base;
517 unsigned int host_write_ptr;
518 unsigned int ep_read_ptr;
519 unsigned int writables;
521 unsigned int free_entries;
522 unsigned int busy_entries;
523 unsigned int buffer_size;
524 unsigned int num_entries;
526 struct list_head free_list;
530 struct be_bus_address pa_base;
533 struct async_pdu_handle *handle_base;
535 unsigned int host_write_ptr;
536 unsigned int ep_read_ptr;
537 unsigned int writables;
539 unsigned int free_entries;
540 unsigned int busy_entries;
541 unsigned int buffer_size;
542 struct list_head free_list;
543 unsigned int num_entries;
547 * This is a varying size list! Do not add anything
550 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
553 #define PDUCQE_CODE_MASK 0x0000003F
554 #define PDUCQE_DPL_MASK 0xFFFF0000
555 #define PDUCQE_INDEX_MASK 0x0000FFFF
557 struct i_t_dpdu_cqe {
562 * Pseudo amap definition in which each bit of the actual structure is defined
563 * as a byte: used to calculate offset/shift/mask of each field
565 struct amap_i_t_dpdu_cqe {
578 #define CQE_VALID_MASK 0x80000000
579 #define CQE_CODE_MASK 0x0000003F
580 #define CQE_CID_MASK 0x0000FFC0
582 #define EQE_VALID_MASK 0x00000001
583 #define EQE_MAJORCODE_MASK 0x0000000E
584 #define EQE_RESID_MASK 0xFFFF0000
591 * Pseudo amap definition in which each bit of the actual structure is defined
592 * as a byte: used to calculate offset/shift/mask of each field
594 struct amap_eq_entry {
595 u8 valid; /* DWORD 0 */
596 u8 major_code[3]; /* DWORD 0 */
597 u8 minor_code[12]; /* DWORD 0 */
598 u8 resource_id[16]; /* DWORD 0 */
607 * Pseudo amap definition in which each bit of the actual structure is defined
608 * as a byte: used to calculate offset/shift/mask of each field
619 void beiscsi_process_eq(struct beiscsi_hba *phba);
625 #define WRB_TYPE_MASK 0xF0000000
628 * Pseudo amap definition in which each bit of the actual structure is defined
629 * as a byte: used to calculate offset/shift/mask of each field
631 struct amap_iscsi_wrb {
632 u8 lun[14]; /* DWORD 0 */
634 u8 invld; /* DWORD 0 */
635 u8 wrb_idx[8]; /* DWORD 0 */
636 u8 dsp; /* DWORD 0 */
637 u8 dmsg; /* DWORD 0 */
638 u8 undr_run; /* DWORD 0 */
639 u8 over_run; /* DWORD 0 */
640 u8 type[4]; /* DWORD 0 */
641 u8 ptr2nextwrb[8]; /* DWORD 1 */
642 u8 r2t_exp_dtl[24]; /* DWORD 1 */
643 u8 sgl_icd_idx[12]; /* DWORD 2 */
644 u8 rsvd0[20]; /* DWORD 2 */
645 u8 exp_data_sn[32]; /* DWORD 3 */
646 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
647 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
648 u8 cmdsn_itt[32]; /* DWORD 6 */
649 u8 dif_ref_tag[32]; /* DWORD 7 */
650 u8 sge0_addr_hi[32]; /* DWORD 8 */
651 u8 sge0_addr_lo[32]; /* DWORD 9 */
652 u8 sge0_offset[22]; /* DWORD 10 */
653 u8 pbs; /* DWORD 10 */
654 u8 dif_mode[2]; /* DWORD 10 */
655 u8 rsvd1[6]; /* DWORD 10 */
656 u8 sge0_last; /* DWORD 10 */
657 u8 sge0_len[17]; /* DWORD 11 */
658 u8 dif_meta_tag[14]; /* DWORD 11 */
659 u8 sge0_in_ddr; /* DWORD 11 */
660 u8 sge1_addr_hi[32]; /* DWORD 12 */
661 u8 sge1_addr_lo[32]; /* DWORD 13 */
662 u8 sge1_r2t_offset[22]; /* DWORD 14 */
663 u8 rsvd2[9]; /* DWORD 14 */
664 u8 sge1_last; /* DWORD 14 */
665 u8 sge1_len[17]; /* DWORD 15 */
666 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
667 u8 rsvd3[2]; /* DWORD 15 */
668 u8 sge1_in_ddr; /* DWORD 15 */
672 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
674 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
676 void beiscsi_process_all_cqs(struct work_struct *work);
683 * Pseudo amap definition in which each bit of the actual structure is defined
684 * as a byte: used to calculate offset/shift/mask of each field
686 struct amap_pdu_nop_out {
687 u8 opcode[6]; /* opcode 0x00 */
688 u8 i_bit; /* I Bit */
689 u8 x_bit; /* reserved; should be 0 */
690 u8 fp_bit_filler1[7];
691 u8 f_bit; /* always 1 */
693 u8 ahs_length[8]; /* no AHS */
695 u8 data_len_lo[16]; /* DataSegmentLength */
697 u8 itt[32]; /* initiator id for ping or 0xffffffff */
698 u8 ttt[32]; /* target id for ping or 0xffffffff */
704 #define PDUBASE_OPCODE_MASK 0x0000003F
705 #define PDUBASE_DATALENHI_MASK 0x0000FF00
706 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
713 * Pseudo amap definition in which each bit of the actual structure is defined
714 * as a byte: used to calculate offset/shift/mask of each field
716 struct amap_pdu_base {
718 u8 i_bit; /* immediate bit */
719 u8 x_bit; /* reserved, always 0 */
720 u8 reserved1[24]; /* opcode-specific fields */
721 u8 ahs_length[8]; /* length units is 4 byte words */
723 u8 data_len_lo[16]; /* DatasegmentLength */
724 u8 lun[64]; /* lun or opcode-specific fields */
725 u8 itt[32]; /* initiator task tag */
729 struct iscsi_target_context_update_wrb {
734 * Pseudo amap definition in which each bit of the actual structure is defined
735 * as a byte: used to calculate offset/shift/mask of each field
737 struct amap_iscsi_target_context_update_wrb {
738 u8 lun[14]; /* DWORD 0 */
740 u8 invld; /* DWORD 0 */
741 u8 wrb_idx[8]; /* DWORD 0 */
742 u8 dsp; /* DWORD 0 */
743 u8 dmsg; /* DWORD 0 */
744 u8 undr_run; /* DWORD 0 */
745 u8 over_run; /* DWORD 0 */
746 u8 type[4]; /* DWORD 0 */
747 u8 ptr2nextwrb[8]; /* DWORD 1 */
748 u8 max_burst_length[19]; /* DWORD 1 */
749 u8 rsvd0[5]; /* DWORD 1 */
750 u8 rsvd1[15]; /* DWORD 2 */
751 u8 max_send_data_segment_length[17]; /* DWORD 2 */
752 u8 first_burst_length[14]; /* DWORD 3 */
753 u8 rsvd2[2]; /* DWORD 3 */
754 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
755 u8 rsvd3[5]; /* DWORD 3 */
756 u8 session_state[3]; /* DWORD 3 */
757 u8 rsvd4[16]; /* DWORD 4 */
758 u8 tx_jumbo; /* DWORD 4 */
759 u8 hde; /* DWORD 4 */
760 u8 dde; /* DWORD 4 */
761 u8 erl[2]; /* DWORD 4 */
762 u8 domain_id[5]; /* DWORD 4 */
763 u8 mode; /* DWORD 4 */
764 u8 imd; /* DWORD 4 */
765 u8 ir2t; /* DWORD 4 */
766 u8 notpredblq[2]; /* DWORD 4 */
767 u8 compltonack; /* DWORD 4 */
768 u8 stat_sn[32]; /* DWORD 5 */
769 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
770 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
771 u8 pad_addr_hi[32]; /* DWORD 8 */
772 u8 pad_addr_lo[32]; /* DWORD 9 */
773 u8 rsvd5[32]; /* DWORD 10 */
774 u8 rsvd6[32]; /* DWORD 11 */
775 u8 rsvd7[32]; /* DWORD 12 */
776 u8 rsvd8[32]; /* DWORD 13 */
777 u8 rsvd9[32]; /* DWORD 14 */
778 u8 rsvd10[32]; /* DWORD 15 */
783 u32 pages; /* queue size in pages */
784 u32 id; /* queue id assigned by beklib */
785 u32 num; /* number of elements in queue */
786 u32 cidx; /* consumer index */
787 u32 pidx; /* producer index -- not used by most rings */
788 u32 item_size; /* size in bytes of one object */
790 void *va; /* The virtual address of the ring. This
791 * should be last to allow 32 & 64 bit debugger
792 * extensions to work.
796 struct hwi_wrb_context {
797 struct list_head wrb_handle_list;
798 struct list_head wrb_handle_drvr_list;
799 struct wrb_handle **pwrb_handle_base;
800 struct wrb_handle **pwrb_handle_basestd;
801 struct iscsi_wrb *plast_wrb;
802 unsigned short alloc_index;
803 unsigned short free_index;
804 unsigned short wrb_handles_available;
808 struct hwi_controller {
809 struct list_head io_sgl_list;
810 struct list_head eh_sgl_list;
811 struct sgl_handle *psgl_handle_base;
812 unsigned int wrb_mem_index;
814 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
815 struct mcc_wrb *pmcc_wrb_base;
816 struct be_ring default_pdu_hdr;
817 struct be_ring default_pdu_data;
818 struct hwi_context_memory *phwi_ctxt;
828 HWH_TYPE_INVALID = 0xFFFFFFFF
832 enum hwh_type_enum type;
833 unsigned short wrb_index;
834 unsigned short nxt_wrb_index;
836 struct iscsi_task *pio_handle;
837 struct iscsi_wrb *pwrb;
840 struct hwi_context_memory {
841 /* Adaptive interrupt coalescing (AIC) info */
842 u16 min_eqd; /* in usecs */
843 u16 max_eqd; /* in usecs */
844 u16 cur_eqd; /* in usecs */
845 struct be_eq_obj be_eq[MAX_CPUS];
846 struct be_queue_info be_cq[MAX_CPUS];
848 struct be_queue_info be_def_hdrq;
849 struct be_queue_info be_def_dataq;
851 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
852 struct be_mcc_wrb_context *pbe_mcc_context;
854 struct hwi_async_pdu_context *pasync_ctx;