2 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
7 * Detailed datasheet of the chip is available here:
9 * http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
11 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/rtc.h>
27 #include <linux/i2c.h>
28 #include <linux/bcd.h>
30 #include <linux/regmap.h>
31 #include <linux/interrupt.h>
33 #define DRV_NAME "rtc-ab-b5ze-s3"
36 #define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
37 #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
38 #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
39 #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
40 #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
41 #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
42 #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
43 #define ABB5ZES3_REG_CTRL1_CAP BIT(7)
45 #define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
46 #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
47 #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
48 #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
49 #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
50 #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
51 #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
52 #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
53 #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
55 #define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
56 #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
57 #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
58 #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
59 #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
60 #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
61 #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
62 #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
64 #define ABB5ZES3_CTRL_SEC_LEN 3
67 #define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
68 #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
69 #define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
70 #define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
71 #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
72 #define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
73 #define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
74 #define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
75 #define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
77 #define ABB5ZES3_RTC_SEC_LEN 7
79 /* Alarm section (enable bits are all active low) */
80 #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
81 #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
82 #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
83 #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
84 #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
85 #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
86 #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
87 #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
89 #define ABB5ZES3_ALRM_SEC_LEN 4
91 /* Frequency offset section */
92 #define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
93 #define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
95 /* CLOCKOUT section */
96 #define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
97 #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
98 #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
99 #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
100 #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
101 #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
102 #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
103 #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
104 #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
106 /* Timer A Section */
107 #define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
108 #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
109 #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
110 #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
111 #define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
113 #define ABB5ZES3_TIMA_SEC_LEN 2
115 /* Timer B Section */
116 #define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
117 #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
118 #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
119 #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
120 #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
121 #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
122 #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
123 #define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
124 #define ABB5ZES3_TIMB_SEC_LEN 2
126 #define ABB5ZES3_MEM_MAP_LEN 0x14
128 struct abb5zes3_rtc_data {
129 struct rtc_device *rtc;
130 struct regmap *regmap;
139 * Try and match register bits w/ fixed null values to see whether we
140 * are dealing with an ABB5ZES3. Note: this function is called early
141 * during init and hence does need mutex protection.
143 static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
145 u8 regs[ABB5ZES3_MEM_MAP_LEN];
146 static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
147 0x80, 0xc0, 0xc0, 0xf8,
148 0xe0, 0x00, 0x00, 0x40,
149 0x40, 0x78, 0x00, 0x00,
150 0xf8, 0x00, 0x88, 0x00 };
153 ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
157 for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
158 if (regs[i] & mask[i]) /* check if bits are cleared */
165 /* Clear alarm status bit. */
166 static int _abb5zes3_rtc_clear_alarm(struct device *dev)
168 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
171 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
172 ABB5ZES3_REG_CTRL2_AF, 0);
174 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
179 /* Enable or disable alarm (i.e. alarm interrupt generation) */
180 static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
182 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
185 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
186 ABB5ZES3_REG_CTRL1_AIE,
187 enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
189 dev_err(dev, "%s: writing alarm INT failed (%d)\n",
196 * Note: we only read, so regmap inner lock protection is sufficient, i.e.
197 * we do not need driver's main lock protection.
199 static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
201 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
202 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
206 * As we need to read CTRL1 register anyway to access 24/12h
207 * mode bit, we do a single bulk read of both control and RTC
208 * sections (they are consecutive). This also ease indexing
209 * of register values after bulk read.
211 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
214 dev_err(dev, "%s: reading RTC time failed (%d)\n",
219 /* If clock integrity is not guaranteed, do not return a time value */
220 if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC) {
225 tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
226 tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
228 if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
229 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
230 if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
232 } else { /* 24hr mode */
233 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
236 tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
237 tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
238 tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
239 tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
241 ret = rtc_valid_tm(tm);
247 static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
249 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
250 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
254 * Year register is 8-bit wide and bcd-coded, i.e records values
255 * between 0 and 99. tm_year is an offset from 1900 and we are
256 * interested in the 2000-2099 range, so any value less than 100
259 if (tm->tm_year < 100)
262 regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
263 regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
264 regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
265 regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
266 regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
267 regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
268 regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
270 mutex_lock(&data->lock);
271 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
272 regs + ABB5ZES3_REG_RTC_SC,
273 ABB5ZES3_RTC_SEC_LEN);
274 mutex_unlock(&data->lock);
280 static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
282 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
283 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
284 unsigned long rtc_secs, alarm_secs;
285 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
289 mutex_lock(&data->lock);
290 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
291 ABB5ZES3_ALRM_SEC_LEN);
293 dev_err(dev, "%s: reading alarm section failed (%d)\n",
298 alarm_tm->tm_sec = 0;
299 alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
300 alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
301 alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
302 alarm_tm->tm_wday = -1;
305 * The alarm section does not store year/month. We use the ones in rtc
306 * section as a basis and increment month and then year if needed to get
307 * alarm after current time.
309 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
313 alarm_tm->tm_year = rtc_tm.tm_year;
314 alarm_tm->tm_mon = rtc_tm.tm_mon;
316 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
320 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
324 if (alarm_secs < rtc_secs) {
325 if (alarm_tm->tm_mon == 11) {
326 alarm_tm->tm_mon = 0;
327 alarm_tm->tm_year += 1;
329 alarm_tm->tm_mon += 1;
333 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, ®);
335 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
340 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
343 mutex_unlock(&data->lock);
348 /* ALARM is only accurate to the minute (not the second) */
349 static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
351 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
352 struct rtc_time *alarm_tm = &alarm->time;
353 unsigned long rtc_secs, alarm_secs;
354 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
355 struct rtc_time rtc_tm;
358 mutex_lock(&data->lock);
359 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
363 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
367 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
371 /* If alarm time is before current time, disable the alarm */
372 if (!alarm->enabled || alarm_secs <= rtc_secs) {
376 * Chip only support alarms up to one month in the future. Let's
377 * return an error if we get something after that limit.
378 * Comparison is done by incrementing rtc_tm month field by one
379 * and checking alarm value is still below.
381 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
388 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
392 if (alarm_secs > rtc_secs) {
393 dev_err(dev, "%s: alarm maximum is one month in the "
394 "future (%d)\n", __func__, ret);
400 /* Disable the alarm before modifying it */
401 ret = _abb5zes3_rtc_update_alarm(dev, 0);
403 dev_err(dev, "%s: unable to disable the alarm (%d)\n",
408 /* Program alarm registers */
409 regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f; /* minute */
410 regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f; /* hour */
411 regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f; /* day of the month */
412 regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
414 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
415 ABB5ZES3_ALRM_SEC_LEN);
417 dev_err(dev, "%s: writing ALARM section failed (%d)\n",
422 /* Enable or disable alarm */
423 ret = _abb5zes3_rtc_update_alarm(dev, enable);
426 mutex_unlock(&data->lock);
432 /* Enable or disable battery low irq generation */
433 static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
436 return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
437 ABB5ZES3_REG_CTRL3_BLIE,
438 enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
442 * Check current RTC status and enable/disable what needs to be. Return 0 if
443 * everything went ok and a negative value upon error. Note: this function
444 * is called early during init and hence does need mutex protection.
446 static int abb5zes3_rtc_check_setup(struct device *dev)
448 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
449 struct regmap *regmap = data->regmap;
455 * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
456 * is disabled here to prevent polluting the interrupt line and
457 * uselessly triggering the IRQ handler we install for alarm and battery
458 * low events. Note: this is done before clearing int. status below
460 * We also disable all timers and set timer interrupt to permanent (not
463 mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
464 ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
465 ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
466 ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
467 ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
468 ABB5ZES3_REG_TIM_CLK_COF0 | ABB5ZES3_REG_TIM_CLK_COF1 |
469 ABB5ZES3_REG_TIM_CLK_COF2);
471 dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
477 * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
478 * individually by clearing/setting MSB of each associated register. So,
479 * we set all alarm enable bits to disable current alarm setting.
481 mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
482 ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
483 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
485 dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
490 /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
491 mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
492 ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
493 ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
494 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
496 dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
502 * Set Control 2 register (timer int. disabled, alarm status cleared).
503 * WTAF is read-only and cleared automatically by reading the register.
505 mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
506 ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
507 ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
508 ABB5ZES3_REG_CTRL2_CTAF);
509 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
511 dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
517 * Enable battery low detection function and battery switchover function
518 * (standard mode). Disable associated interrupts. Clear battery
519 * switchover flag but not battery low flag. The latter is checked
522 mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
523 ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
524 ABB5ZES3_REG_CTRL3_BSIE| ABB5ZES3_REG_CTRL3_BSF);
525 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
527 dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
532 /* Check oscillator integrity flag */
533 ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, ®);
535 dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
540 if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
541 dev_err(dev, "clock integrity not guaranteed. Osc. has stopped "
542 "or has been interrupted.\n");
543 dev_err(dev, "change battery (if not already done) and "
544 "then set time to reset osc. failure flag.\n");
548 * Check battery low flag at startup: this allows reporting battery
549 * is low at startup when IRQ line is not connected. Note: we record
550 * current status to avoid reenabling this interrupt later in probe
551 * function if battery is low.
553 ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, ®);
555 dev_err(dev, "%s: unable to read battery low flag (%d)\n",
560 data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
561 if (data->battery_low) {
562 dev_err(dev, "RTC battery is low; please, consider "
565 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
567 dev_err(dev, "%s: disabling battery low interrupt "
568 "generation failed (%d)\n", __func__, ret);
574 static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
577 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
581 mutex_lock(&rtc_data->lock);
582 ret = _abb5zes3_rtc_update_alarm(dev, enable);
583 mutex_unlock(&rtc_data->lock);
589 static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
591 struct i2c_client *client = data;
592 struct device *dev = &client->dev;
593 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
594 struct rtc_device *rtc = rtc_data->rtc;
595 u8 regs[ABB5ZES3_CTRL_SEC_LEN];
596 int ret, handled = IRQ_NONE;
598 ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
599 ABB5ZES3_CTRL_SEC_LEN);
601 dev_err(dev, "%s: unable to read control section (%d)!\n",
607 * Check battery low detection flag and disable battery low interrupt
608 * generation if flag is set (interrupt can only be cleared when
609 * battery is replaced).
611 if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
612 dev_err(dev, "RTC battery is low; please change it!\n");
614 _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
616 handled = IRQ_HANDLED;
619 /* Check alarm flag */
620 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
621 dev_dbg(dev, "RTC alarm!\n");
623 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
625 /* Acknowledge and disable the alarm */
626 _abb5zes3_rtc_clear_alarm(dev);
627 _abb5zes3_rtc_update_alarm(dev, 0);
629 handled = IRQ_HANDLED;
635 static const struct rtc_class_ops rtc_ops = {
636 .read_time = _abb5zes3_rtc_read_time,
637 .set_time = abb5zes3_rtc_set_time,
638 .read_alarm = abb5zes3_rtc_read_alarm,
639 .set_alarm = abb5zes3_rtc_set_alarm,
640 .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
643 static struct regmap_config abb5zes3_rtc_regmap_config = {
648 static int abb5zes3_probe(struct i2c_client *client,
649 const struct i2c_device_id *id)
651 struct abb5zes3_rtc_data *data = NULL;
652 struct device *dev = &client->dev;
653 struct regmap *regmap;
656 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
657 I2C_FUNC_SMBUS_BYTE_DATA |
658 I2C_FUNC_SMBUS_I2C_BLOCK)) {
663 regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
664 if (IS_ERR(regmap)) {
665 ret = PTR_ERR(regmap);
666 dev_err(dev, "%s: regmap allocation failed: %d\n",
671 ret = abb5zes3_i2c_validate_chip(regmap);
675 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
681 mutex_init(&data->lock);
682 data->regmap = regmap;
683 dev_set_drvdata(dev, data);
685 ret = abb5zes3_rtc_check_setup(dev);
689 if (client->irq > 0) {
690 ret = devm_request_threaded_irq(dev, client->irq, NULL,
691 _abb5zes3_rtc_interrupt,
692 IRQF_SHARED|IRQF_ONESHOT,
695 device_init_wakeup(dev, true);
696 data->irq = client->irq;
697 dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
700 dev_err(dev, "%s: irq %d unavailable (%d)\n",
701 __func__, client->irq, ret);
706 data->rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops,
708 ret = PTR_ERR_OR_ZERO(data->rtc);
710 dev_err(dev, "%s: unable to register RTC device (%d)\n",
716 * AB-B5Z5E only supports a coarse granularity alarm (one minute
717 * resolution up to one month) so we cannot support UIE mode
718 * using the device's alarm. Note it should be feasible to support
719 * such a feature using one of the two timers the device provides.
721 data->rtc->uie_unsupported = 1;
723 /* Enable battery low detection interrupt if battery not already low */
724 if (!data->battery_low && data->irq) {
725 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
727 dev_err(dev, "%s: enabling battery low interrupt "
728 "generation failed (%d)\n", __func__, ret);
734 if (ret && data && data->irq)
735 device_init_wakeup(dev, false);
739 static int abb5zes3_remove(struct i2c_client *client)
741 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(&client->dev);
743 if (rtc_data->irq > 0)
744 device_init_wakeup(&client->dev, false);
749 #ifdef CONFIG_PM_SLEEP
750 static int abb5zes3_rtc_suspend(struct device *dev)
752 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
754 if (device_may_wakeup(dev))
755 return enable_irq_wake(rtc_data->irq);
760 static int abb5zes3_rtc_resume(struct device *dev)
762 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
764 if (device_may_wakeup(dev))
765 return disable_irq_wake(rtc_data->irq);
771 static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
772 abb5zes3_rtc_resume);
775 static const struct of_device_id abb5zes3_dt_match[] = {
776 { .compatible = "abracon,abb5zes3" },
781 static const struct i2c_device_id abb5zes3_id[] = {
785 MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
787 static struct i2c_driver abb5zes3_driver = {
790 .owner = THIS_MODULE,
791 .pm = &abb5zes3_rtc_pm_ops,
792 .of_match_table = of_match_ptr(abb5zes3_dt_match),
794 .probe = abb5zes3_probe,
795 .remove = abb5zes3_remove,
796 .id_table = abb5zes3_id,
798 module_i2c_driver(abb5zes3_driver);
800 MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
801 MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
802 MODULE_LICENSE("GPL");