2 * IDT CPS Gen.2 Serial RapidIO switch family support
4 * Copyright 2010 Integrated Device Technology, Inc.
5 * Alexandre Bounine <alexandre.bounine@idt.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/stat.h>
14 #include <linux/rio.h>
15 #include <linux/rio_drv.h>
16 #include <linux/rio_ids.h>
17 #include <linux/delay.h>
22 #define LOCAL_RTE_CONF_DESTID_SEL 0x010070
23 #define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f
25 #define IDT_LT_ERR_REPORT_EN 0x03100c
27 #define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40)
28 #define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04
30 #define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40)
31 #define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c
32 #define IDT_PORT_INIT_TX_ACQUIRED 0x00000020
34 #define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100)
35 #define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10
37 #define IDT_DEV_CTRL_1 0xf2000c
38 #define IDT_DEV_CTRL_1_GENPW 0x02000000
39 #define IDT_DEV_CTRL_1_PRSTBEH 0x00000001
41 #define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008
42 #define IDT_CFGBLK_ERR_REPORT 0xf20014
43 #define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002
45 #define IDT_AUX_PORT_ERR_CAP_EN 0x020000
46 #define IDT_AUX_ERR_REPORT_EN 0xf20018
47 #define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002
48 #define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001
50 #define IDT_ISLTL_ADDRESS_CAP 0x021014
52 #define IDT_RIO_DOMAIN 0xf20020
53 #define IDT_RIO_DOMAIN_MASK 0x000000ff
55 #define IDT_PW_INFO_CSR 0xf20024
57 #define IDT_SOFT_RESET 0xf20040
58 #define IDT_SOFT_RESET_REQ 0x00030097
60 #define IDT_I2C_MCTRL 0xf20050
61 #define IDT_I2C_MCTRL_GENPW 0x04000000
63 #define IDT_JTAG_CTRL 0xf2005c
64 #define IDT_JTAG_CTRL_GENPW 0x00000002
66 #define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100)
67 #define IDT_LANE_CTRL_BC 0xffff00
68 #define IDT_LANE_CTRL_GENPW 0x00200000
69 #define IDT_LANE_DFE_1_BC 0xffff18
70 #define IDT_LANE_DFE_2_BC 0xffff1c
72 #define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100)
73 #define IDT_PORT_OPS_GENPW 0x08000000
74 #define IDT_PORT_OPS_PL_ELOG 0x00000040
75 #define IDT_PORT_OPS_LL_ELOG 0x00000020
76 #define IDT_PORT_OPS_LT_ELOG 0x00000010
77 #define IDT_PORT_OPS_BC 0xf4ff04
79 #define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100)
81 #define IDT_ERR_CAP 0xfd0000
82 #define IDT_ERR_CAP_LOG_OVERWR 0x00000004
84 #define IDT_ERR_RD 0xfd0004
86 #define IDT_DEFAULT_ROUTE 0xde
87 #define IDT_NO_ROUTE 0xdf
90 idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
91 u16 table, u16 route_destid, u8 route_port)
94 * Select routing table to update
96 if (table == RIO_GLOBAL_TABLE)
101 if (route_port == RIO_INVALID_ROUTE)
102 route_port = IDT_DEFAULT_ROUTE;
104 rio_mport_write_config_32(mport, destid, hopcount,
105 LOCAL_RTE_CONF_DESTID_SEL, table);
108 * Program destination port for the specified destID
110 rio_mport_write_config_32(mport, destid, hopcount,
111 RIO_STD_RTE_CONF_DESTID_SEL_CSR,
114 rio_mport_write_config_32(mport, destid, hopcount,
115 RIO_STD_RTE_CONF_PORT_SEL_CSR,
123 idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
124 u16 table, u16 route_destid, u8 *route_port)
129 * Select routing table to read
131 if (table == RIO_GLOBAL_TABLE)
136 rio_mport_write_config_32(mport, destid, hopcount,
137 LOCAL_RTE_CONF_DESTID_SEL, table);
139 rio_mport_write_config_32(mport, destid, hopcount,
140 RIO_STD_RTE_CONF_DESTID_SEL_CSR,
143 rio_mport_read_config_32(mport, destid, hopcount,
144 RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
146 if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result)
147 *route_port = RIO_INVALID_ROUTE;
149 *route_port = (u8)result;
155 idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
161 * Select routing table to read
163 if (table == RIO_GLOBAL_TABLE)
168 rio_mport_write_config_32(mport, destid, hopcount,
169 LOCAL_RTE_CONF_DESTID_SEL, table);
171 for (i = RIO_STD_RTE_CONF_EXTCFGEN;
172 i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) {
173 rio_mport_write_config_32(mport, destid, hopcount,
174 RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
175 rio_mport_write_config_32(mport, destid, hopcount,
176 RIO_STD_RTE_CONF_PORT_SEL_CSR,
177 (IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) |
178 (IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE);
187 idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
191 * Switch domain configuration operates only at global level
193 rio_mport_write_config_32(mport, destid, hopcount,
194 IDT_RIO_DOMAIN, (u32)sw_domain);
199 idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
205 * Switch domain configuration operates only at global level
207 rio_mport_read_config_32(mport, destid, hopcount,
208 IDT_RIO_DOMAIN, ®val);
210 *sw_domain = (u8)(regval & 0xff);
216 idtg2_em_init(struct rio_dev *rdev)
222 * This routine performs device-specific initialization only.
223 * All standard EM configuration should be performed at upper level.
226 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
228 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */
229 rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
232 * Configure LT LAYER error reporting.
235 /* Enable standard (RIO.p8) error reporting */
236 rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
237 REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
238 REM_LTL_ERR_UNSUPTR);
240 /* Use Port-Writes for LT layer error reporting.
241 * Enable per-port reset
243 rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val);
244 rio_write_config_32(rdev, IDT_DEV_CTRL_1,
245 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
248 * Configure PORT error reporting.
251 /* Report all RIO.p8 errors supported by device */
252 rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
254 /* Configure reporting of implementation specific errors/events */
255 rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
256 IDT_PORT_INIT_TX_ACQUIRED);
258 /* Use Port-Writes for port error reporting and enable error logging */
259 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
260 for (i = 0; i < tmp; i++) {
261 rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val);
262 rio_write_config_32(rdev,
263 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
264 IDT_PORT_OPS_PL_ELOG |
265 IDT_PORT_OPS_LL_ELOG |
266 IDT_PORT_OPS_LT_ELOG);
268 /* Overwrite error log if full */
269 rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
272 * Configure LANE error reporting.
275 /* Disable line error reporting */
276 rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
278 /* Use Port-Writes for lane error reporting (when enabled)
279 * (do per-lane update because lanes may have different configuration)
281 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
282 for (i = 0; i < tmp; i++) {
283 rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val);
284 rio_write_config_32(rdev, IDT_LANE_CTRL(i),
285 regval | IDT_LANE_CTRL_GENPW);
289 * Configure AUX error reporting.
292 /* Disable JTAG and I2C Error capture */
293 rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
295 /* Disable JTAG and I2C Error reporting/logging */
296 rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
298 /* Disable Port-Write notification from JTAG */
299 rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
301 /* Disable Port-Write notification from I2C */
302 rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val);
303 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
306 * Configure CFG_BLK error reporting.
309 /* Disable Configuration Block error capture */
310 rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
312 /* Disable Port-Writes for Configuration Block error reporting */
313 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val);
314 rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
315 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
317 /* set TVAL = ~50us */
318 rio_write_config_32(rdev,
319 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
325 idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
327 u32 regval, em_perrdet, em_ltlerrdet;
329 rio_read_config_32(rdev,
330 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
332 /* Service Logical/Transport Layer Error(s) */
333 if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
334 /* Implementation specific error reported */
335 rio_read_config_32(rdev,
336 IDT_ISLTL_ADDRESS_CAP, ®val);
338 pr_debug("RIO: %s Implementation Specific LTL errors" \
340 rio_name(rdev), em_ltlerrdet, regval);
342 /* Clear implementation specific address capture CSR */
343 rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
348 rio_read_config_32(rdev,
349 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
351 /* Service Port-Level Error(s) */
352 if (em_perrdet & REM_PED_IMPL_SPEC) {
353 /* Implementation Specific port error reported */
355 /* Get IS errors reported */
356 rio_read_config_32(rdev,
357 IDT_PORT_ISERR_DET(portnum), ®val);
359 pr_debug("RIO: %s Implementation Specific Port" \
360 " errors 0x%x\n", rio_name(rdev), regval);
362 /* Clear all implementation specific events */
363 rio_write_config_32(rdev,
364 IDT_PORT_ISERR_DET(portnum), 0);
372 idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
374 struct rio_dev *rdev = to_rio_dev(dev);
378 while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) {
379 if (!regval) /* 0 = end of log */
381 len += snprintf(buf + len, PAGE_SIZE - len,
383 if (len >= (PAGE_SIZE - 10))
390 static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);
392 static int idtg2_sysfs(struct rio_dev *rdev, int create)
394 struct device *dev = &rdev->dev;
397 if (create == RIO_SW_SYSFS_CREATE) {
398 /* Initialize sysfs entries */
399 err = device_create_file(dev, &dev_attr_errlog);
401 dev_err(dev, "Unable create sysfs errlog file\n");
403 device_remove_file(dev, &dev_attr_errlog);
408 static int idtg2_switch_init(struct rio_dev *rdev, int do_enum)
410 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
411 rdev->rswitch->add_entry = idtg2_route_add_entry;
412 rdev->rswitch->get_entry = idtg2_route_get_entry;
413 rdev->rswitch->clr_table = idtg2_route_clr_table;
414 rdev->rswitch->set_domain = idtg2_set_domain;
415 rdev->rswitch->get_domain = idtg2_get_domain;
416 rdev->rswitch->em_init = idtg2_em_init;
417 rdev->rswitch->em_handle = idtg2_em_handler;
418 rdev->rswitch->sw_sysfs = idtg2_sysfs;
421 /* Ensure that default routing is disabled on startup */
422 rio_write_config_32(rdev,
423 RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
429 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init);
430 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init);
431 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init);
432 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init);
433 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1432, idtg2_switch_init);