2 * PWM driver for Rockchip SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * Copyright (C) 2014 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
12 #include <linux/clk.h>
14 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/time.h>
21 #define PWM_CTRL_TIMER_EN (1 << 0)
22 #define PWM_CTRL_OUTPUT_EN (1 << 3)
24 #define PWM_ENABLE (1 << 0)
25 #define PWM_CONTINUOUS (1 << 1)
26 #define PWM_DUTY_POSITIVE (1 << 3)
27 #define PWM_INACTIVE_NEGATIVE (0 << 4)
28 #define PWM_OUTPUT_LEFT (0 << 5)
29 #define PWM_LP_DISABLE (0 << 8)
31 struct rockchip_pwm_chip {
34 const struct rockchip_pwm_data *data;
38 struct rockchip_pwm_regs {
45 struct rockchip_pwm_data {
46 struct rockchip_pwm_regs regs;
47 unsigned int prescaler;
49 void (*set_enable)(struct pwm_chip *chip, bool enable);
52 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
54 return container_of(c, struct rockchip_pwm_chip, chip);
57 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
59 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
60 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
63 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
70 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
73 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
75 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
76 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
77 PWM_CONTINUOUS | PWM_DUTY_POSITIVE |
78 PWM_INACTIVE_NEGATIVE;
81 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
88 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
91 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
92 int duty_ns, int period_ns)
94 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
95 unsigned long period, duty;
99 clk_rate = clk_get_rate(pc->clk);
102 * Since period and duty cycle registers have a width of 32
103 * bits, every possible input period can be obtained using the
104 * default prescaler value for all practical clock rate values.
106 div = clk_rate * period_ns;
107 do_div(div, pc->data->prescaler * NSEC_PER_SEC);
110 div = clk_rate * duty_ns;
111 do_div(div, pc->data->prescaler * NSEC_PER_SEC);
114 ret = clk_enable(pc->clk);
118 writel(period, pc->base + pc->data->regs.period);
119 writel(duty, pc->base + pc->data->regs.duty);
120 writel(0, pc->base + pc->data->regs.cntr);
122 clk_disable(pc->clk);
127 static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
129 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
132 ret = clk_enable(pc->clk);
136 pc->data->set_enable(chip, true);
141 static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
143 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
145 pc->data->set_enable(chip, false);
147 clk_disable(pc->clk);
150 static const struct pwm_ops rockchip_pwm_ops = {
151 .config = rockchip_pwm_config,
152 .enable = rockchip_pwm_enable,
153 .disable = rockchip_pwm_disable,
154 .owner = THIS_MODULE,
157 static const struct rockchip_pwm_data pwm_data_v1 = {
165 .set_enable = rockchip_pwm_set_enable_v1,
168 static const struct rockchip_pwm_data pwm_data_v2 = {
176 .set_enable = rockchip_pwm_set_enable_v2,
179 static const struct rockchip_pwm_data pwm_data_vop = {
187 .set_enable = rockchip_pwm_set_enable_v2,
190 static const struct of_device_id rockchip_pwm_dt_ids[] = {
191 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
192 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
193 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
196 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
198 static int rockchip_pwm_probe(struct platform_device *pdev)
200 const struct of_device_id *id;
201 struct rockchip_pwm_chip *pc;
205 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
209 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
213 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
214 pc->base = devm_ioremap_resource(&pdev->dev, r);
215 if (IS_ERR(pc->base))
216 return PTR_ERR(pc->base);
218 pc->clk = devm_clk_get(&pdev->dev, NULL);
220 return PTR_ERR(pc->clk);
222 ret = clk_prepare(pc->clk);
226 platform_set_drvdata(pdev, pc);
229 pc->chip.dev = &pdev->dev;
230 pc->chip.ops = &rockchip_pwm_ops;
234 ret = pwmchip_add(&pc->chip);
236 clk_unprepare(pc->clk);
237 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
243 static int rockchip_pwm_remove(struct platform_device *pdev)
245 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
247 clk_unprepare(pc->clk);
249 return pwmchip_remove(&pc->chip);
252 static struct platform_driver rockchip_pwm_driver = {
254 .name = "rockchip-pwm",
255 .of_match_table = rockchip_pwm_dt_ids,
257 .probe = rockchip_pwm_probe,
258 .remove = rockchip_pwm_remove,
260 module_platform_driver(rockchip_pwm_driver);
262 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
263 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
264 MODULE_LICENSE("GPL v2");