drivers/pwm/pwm-rockchip.c

   1 /*
   2  * PWM driver for Rockchip SoCs
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/time.h>
  20 #include <linux/rk_fb.h>
  21
  22 #define PWM_CTRL_TIMER_EN       (1 << 0)
  23 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
  24
  25 #define PWM_ENABLE              (1 << 0)
  26 #define PWM_CONTINUOUS          (1 << 1)
  27 #define PWM_DUTY_POSITIVE       (1 << 3)
  28 #define PWM_DUTY_NEGATIVE       (0 << 3)
  29 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
  30 #define PWM_INACTIVE_POSITIVE   (1 << 4)
  31 #define PWM_OUTPUT_LEFT         (0 << 5)
  32 #define PWM_LP_DISABLE          (0 << 8)
  33
  34 struct rockchip_pwm_chip {
  35         struct pwm_chip chip;
  36         struct clk *clk;
  37         struct clk *pclk;
  38         const struct rockchip_pwm_data *data;
  39         void __iomem *base;
  40 };
  41
  42 struct rockchip_pwm_regs {
  43         unsigned long duty;
  44         unsigned long period;
  45         unsigned long cntr;
  46         unsigned long ctrl;
  47 };
  48
  49 struct rockchip_pwm_data {
  50         struct rockchip_pwm_regs regs;
  51         unsigned int prescaler;
  52         bool supports_polarity;
  53         const struct pwm_ops *ops;
  54
  55         void (*set_enable)(struct pwm_chip *chip,
  56                            struct pwm_device *pwm, bool enable,
  57                            enum pwm_polarity polarity);
  58         void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
  59                           struct pwm_state *state);
  60 };
  61
  62 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  63 {
  64         return container_of(c, struct rockchip_pwm_chip, chip);
  65 }
  66
  67 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
  68                                        struct pwm_device *pwm, bool enable,
  69                                        enum pwm_polarity polarity)
  70 {
  71         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  72         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  73         u32 val;
  74
  75         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  76
  77         if (enable)
  78                 val |= enable_conf;
  79         else
  80                 val &= ~enable_conf;
  81
  82         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
  83 }
  84
  85 static void rockchip_pwm_get_state_v1(struct pwm_chip *chip,
  86                                       struct pwm_device *pwm,
  87                                       struct pwm_state *state)
  88 {
  89         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  90         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  91         u32 val;
  92
  93         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  94         if ((val & enable_conf) == enable_conf)
  95                 state->enabled = true;
  96 }
  97
  98 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
  99                                        struct pwm_device *pwm, bool enable,
 100                                        enum pwm_polarity polarity)
 101 {
 102         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 103         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 104                           PWM_CONTINUOUS;
 105         u32 val;
 106
 107         if (polarity == PWM_POLARITY_INVERSED)
 108                 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
 109         else
 110                 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
 111
 112         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 113         val &= ~(GENMASK(5, 0) | BIT(8));
 114
 115         if (enable)
 116                 val |= enable_conf;
 117         else
 118                 val &= ~enable_conf;
 119
 120         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
 121 }
 122
 123 static void rockchip_pwm_get_state_v2(struct pwm_chip *chip,
 124                                       struct pwm_device *pwm,
 125                                       struct pwm_state *state)
 126 {
 127         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 128         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 129                           PWM_CONTINUOUS;
 130         u32 val;
 131
 132         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 133         if ((val & enable_conf) != enable_conf)
 134                 return;
 135
 136         state->enabled = true;
 137
 138         if (!(val & PWM_DUTY_POSITIVE))
 139                 state->polarity = PWM_POLARITY_INVERSED;
 140 }
 141
 142 static void rockchip_pwm_get_state(struct pwm_chip *chip,
 143                                    struct pwm_device *pwm,
 144                                    struct pwm_state *state)
 145 {
 146         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 147         unsigned long clk_rate;
 148         u64 tmp;
 149         int ret;
 150
 151         ret = clk_enable(pc->pclk);
 152         if (ret)
 153                 return;
 154
 155         clk_rate = clk_get_rate(pc->clk);
 156
 157         tmp = readl_relaxed(pc->base + pc->data->regs.period);
 158         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 159         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 160
 161         tmp = readl_relaxed(pc->base + pc->data->regs.duty);
 162         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 163         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 164
 165         pc->data->get_state(chip, pwm, state);
 166
 167         clk_disable(pc->pclk);
 168 }
 169
 170 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 171                                int duty_ns, int period_ns)
 172 {
 173         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 174         unsigned long period, duty;
 175         u64 clk_rate, div;
 176
 177         clk_rate = clk_get_rate(pc->clk);
 178
 179         /*
 180          * Since period and duty cycle registers have a width of 32
 181          * bits, every possible input period can be obtained using the
 182          * default prescaler value for all practical clock rate values.
 183          */
 184         div = clk_rate * period_ns;
 185         period = DIV_ROUND_CLOSEST_ULL(div,
 186                                        pc->data->prescaler * NSEC_PER_SEC);
 187
 188         div = clk_rate * duty_ns;
 189         duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
 190
 191         writel(period, pc->base + pc->data->regs.period);
 192         writel(duty, pc->base + pc->data->regs.duty);
 193
 194 #ifdef CONFIG_FB_ROCKCHIP
 195         if (!pc->data->regs.ctrl) {
 196                 int ret;
 197
 198                 ret = rk_fb_set_vop_pwm();
 199                 if (ret)
 200                         dev_err(pc->chip.dev, "rk_fb_set_vop_pwm failed: %d\n", ret);
 201         }
 202 #endif
 203
 204         return 0;
 205 }
 206
 207 static int rockchip_pwm_enable(struct pwm_chip *chip,
 208                          struct pwm_device *pwm,
 209                          bool enable,
 210                          enum pwm_polarity polarity)
 211 {
 212         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 213         int ret;
 214
 215         if (enable) {
 216                 ret = clk_enable(pc->clk);
 217                 if (ret)
 218                         return ret;
 219         }
 220
 221         pc->data->set_enable(chip, pwm, enable, polarity);
 222
 223         if (!enable)
 224                 clk_disable(pc->clk);
 225
 226         return 0;
 227 }
 228
 229 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 230                               struct pwm_state *state)
 231 {
 232         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 233         struct pwm_state curstate;
 234         bool enabled;
 235         int ret;
 236
 237         pwm_get_state(pwm, &curstate);
 238         enabled = curstate.enabled;
 239
 240         ret = clk_enable(pc->pclk);
 241         if (ret)
 242                 return ret;
 243
 244         if (state->polarity != curstate.polarity && enabled) {
 245                 ret = rockchip_pwm_enable(chip, pwm, false, state->polarity);
 246                 if (ret)
 247                         goto out;
 248                 enabled = false;
 249         }
 250
 251         ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
 252         if (ret) {
 253                 if (enabled != curstate.enabled)
 254                         rockchip_pwm_enable(chip, pwm, !enabled,
 255                                       state->polarity);
 256                 goto out;
 257         }
 258
 259         if (state->enabled != enabled) {
 260                 ret = rockchip_pwm_enable(chip, pwm, state->enabled,
 261                                     state->polarity);
 262                 if (ret)
 263                         goto out;
 264         }
 265
 266         /*
 267          * Update the state with the real hardware, which can differ a bit
 268          * because of period/duty_cycle approximation.
 269          */
 270         rockchip_pwm_get_state(chip, pwm, state);
 271
 272 out:
 273         clk_disable(pc->pclk);
 274
 275         return ret;
 276 }
 277
 278 static const struct pwm_ops rockchip_pwm_ops_v1 = {
 279         .get_state = rockchip_pwm_get_state,
 280         .apply = rockchip_pwm_apply,
 281         .owner = THIS_MODULE,
 282 };
 283
 284 static const struct pwm_ops rockchip_pwm_ops_v2 = {
 285         .get_state = rockchip_pwm_get_state,
 286         .apply = rockchip_pwm_apply,
 287         .owner = THIS_MODULE,
 288 };
 289
 290 static const struct rockchip_pwm_data pwm_data_v1 = {
 291         .regs = {
 292                 .duty = 0x04,
 293                 .period = 0x08,
 294                 .cntr = 0x00,
 295                 .ctrl = 0x0c,
 296         },
 297         .prescaler = 2,
 298         .ops = &rockchip_pwm_ops_v1,
 299         .set_enable = rockchip_pwm_set_enable_v1,
 300         .get_state = rockchip_pwm_get_state_v1,
 301 };
 302
 303 static const struct rockchip_pwm_data pwm_data_v2 = {
 304         .regs = {
 305                 .duty = 0x08,
 306                 .period = 0x04,
 307                 .cntr = 0x00,
 308                 .ctrl = 0x0c,
 309         },
 310         .prescaler = 1,
 311         .supports_polarity = true,
 312         .ops = &rockchip_pwm_ops_v2,
 313         .set_enable = rockchip_pwm_set_enable_v2,
 314         .get_state = rockchip_pwm_get_state_v2,
 315 };
 316
 317 static const struct rockchip_pwm_data pwm_data_vop = {
 318         .regs = {
 319                 .duty = 0x08,
 320                 .period = 0x04,
 321                 .cntr = 0x0c,
 322                 .ctrl = 0x00,
 323         },
 324         .prescaler = 1,
 325         .supports_polarity = true,
 326         .ops = &rockchip_pwm_ops_v2,
 327         .set_enable = rockchip_pwm_set_enable_v2,
 328         .get_state = rockchip_pwm_get_state_v2,
 329 };
 330
 331 static const struct of_device_id rockchip_pwm_dt_ids[] = {
 332         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
 333         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
 334         { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v2},
 335         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
 336         { .compatible = "rockchip,rk3399-pwm", .data = &pwm_data_v2},
 337         { /* sentinel */ }
 338 };
 339 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
 340
 341 static int rockchip_pwm_probe(struct platform_device *pdev)
 342 {
 343         const struct of_device_id *id;
 344         struct rockchip_pwm_chip *pc;
 345         struct resource *r;
 346         int ret, count;
 347
 348         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
 349         if (!id)
 350                 return -EINVAL;
 351
 352         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 353         if (!pc)
 354                 return -ENOMEM;
 355
 356         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 357         pc->base = devm_ioremap(&pdev->dev, r->start,
 358                                 resource_size(r));
 359         if (IS_ERR(pc->base))
 360                 return PTR_ERR(pc->base);
 361
 362         pc->clk = devm_clk_get(&pdev->dev, "pwm");
 363         count = of_property_count_strings(pdev->dev.of_node, "clock-names");
 364         if (count == 2)
 365                 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
 366         else
 367                 pc->pclk = pc->clk;
 368
 369         if (IS_ERR(pc->clk)) {
 370                 ret = PTR_ERR(pc->clk);
 371                 if (ret != -EPROBE_DEFER)
 372                         dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret);
 373                 return ret;
 374         }
 375
 376         if (IS_ERR(pc->pclk)) {
 377                 ret = PTR_ERR(pc->pclk);
 378                 if (ret != -EPROBE_DEFER)
 379                         dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret);
 380                 return ret;
 381         }
 382
 383         ret = clk_prepare_enable(pc->clk);
 384         if (ret) {
 385                 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
 386                 return ret;
 387         }
 388
 389         ret = clk_prepare(pc->pclk);
 390         if (ret) {
 391                 dev_err(&pdev->dev, "Can't prepare periph clk: %d\n", ret);
 392                 goto err_clk;
 393         }
 394
 395         platform_set_drvdata(pdev, pc);
 396
 397         pc->data = id->data;
 398         pc->chip.dev = &pdev->dev;
 399         pc->chip.ops = pc->data->ops;
 400         pc->chip.base = -1;
 401         pc->chip.npwm = 1;
 402
 403         if (pc->data->supports_polarity) {
 404                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
 405                 pc->chip.of_pwm_n_cells = 3;
 406         }
 407
 408         ret = pwmchip_add(&pc->chip);
 409         if (ret < 0) {
 410                 clk_unprepare(pc->clk);
 411                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 412                 goto err_pclk;
 413         }
 414
 415         /* Keep the PWM clk enabled if the PWM appears to be up and running. */
 416         if (!pwm_is_enabled(pc->chip.pwms))
 417                 clk_disable(pc->clk);
 418
 419         return 0;
 420
 421 err_pclk:
 422         clk_unprepare(pc->pclk);
 423 err_clk:
 424         clk_disable_unprepare(pc->clk);
 425
 426         return ret;
 427 }
 428
 429 static int rockchip_pwm_remove(struct platform_device *pdev)
 430 {
 431         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
 432
 433         /*
 434          * Disable the PWM clk before unpreparing it if the PWM device is still
 435          * running. This should only happen when the last PWM user left it
 436          * enabled, or when nobody requested a PWM that was previously enabled
 437          * by the bootloader.
 438          *
 439          * FIXME: Maybe the core should disable all PWM devices in
 440          * pwmchip_remove(). In this case we'd only have to call
 441          * clk_unprepare() after pwmchip_remove().
 442          *
 443          */
 444         if (pwm_is_enabled(pc->chip.pwms))
 445                 clk_disable(pc->clk);
 446
 447         clk_unprepare(pc->pclk);
 448         clk_unprepare(pc->clk);
 449
 450         return pwmchip_remove(&pc->chip);
 451 }
 452
 453 static struct platform_driver rockchip_pwm_driver = {
 454         .driver = {
 455                 .name = "rockchip-pwm",
 456                 .of_match_table = rockchip_pwm_dt_ids,
 457         },
 458         .probe = rockchip_pwm_probe,
 459         .remove = rockchip_pwm_remove,
 460 };
 461 module_platform_driver(rockchip_pwm_driver);
 462
 463 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 464 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
 465 MODULE_LICENSE("GPL v2");