drivers/pwm/pwm-rockchip.c

   1 /*
   2  * PWM driver for Rockchip SoCs
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/time.h>
  20 #include <linux/rk_fb.h>
  21
  22 #define PWM_CTRL_TIMER_EN       (1 << 0)
  23 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
  24
  25 #define PWM_ENABLE              (1 << 0)
  26 #define PWM_CONTINUOUS          (1 << 1)
  27 #define PWM_DUTY_POSITIVE       (1 << 3)
  28 #define PWM_DUTY_NEGATIVE       (0 << 3)
  29 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
  30 #define PWM_INACTIVE_POSITIVE   (1 << 4)
  31 #define PWM_OUTPUT_LEFT         (0 << 5)
  32 #define PWM_LP_DISABLE          (0 << 8)
  33
  34 struct rockchip_pwm_chip {
  35         struct pwm_chip chip;
  36         struct clk *clk;
  37         struct clk *pclk;
  38         const struct rockchip_pwm_data *data;
  39         void __iomem *base;
  40 };
  41
  42 struct rockchip_pwm_regs {
  43         unsigned long duty;
  44         unsigned long period;
  45         unsigned long cntr;
  46         unsigned long ctrl;
  47 };
  48
  49 struct rockchip_pwm_data {
  50         struct rockchip_pwm_regs regs;
  51         unsigned int prescaler;
  52         const struct pwm_ops *ops;
  53
  54         void (*set_enable)(struct pwm_chip *chip,
  55                            struct pwm_device *pwm, bool enable);
  56 };
  57
  58 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  59 {
  60         return container_of(c, struct rockchip_pwm_chip, chip);
  61 }
  62
  63 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
  64                                        struct pwm_device *pwm, bool enable)
  65 {
  66         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  67         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  68         u32 val;
  69
  70         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  71
  72         if (enable)
  73                 val |= enable_conf;
  74         else
  75                 val &= ~enable_conf;
  76
  77         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
  78 }
  79
  80 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
  81                                        struct pwm_device *pwm, bool enable)
  82 {
  83         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  84         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
  85                           PWM_CONTINUOUS;
  86         u32 val;
  87
  88         if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
  89                 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
  90         else
  91                 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
  92
  93         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  94         val &= ~(GENMASK(5, 0) | BIT(8));
  95
  96         if (enable)
  97                 val |= enable_conf;
  98         else
  99                 val &= ~enable_conf;
 100
 101         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
 102 }
 103
 104 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 105                                int duty_ns, int period_ns)
 106 {
 107         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 108         unsigned long period, duty;
 109         u64 clk_rate, div;
 110         int ret;
 111
 112         clk_rate = clk_get_rate(pc->clk);
 113
 114         /*
 115          * Since period and duty cycle registers have a width of 32
 116          * bits, every possible input period can be obtained using the
 117          * default prescaler value for all practical clock rate values.
 118          */
 119         div = clk_rate * period_ns;
 120         do_div(div, pc->data->prescaler * NSEC_PER_SEC);
 121         period = div;
 122
 123         div = clk_rate * duty_ns;
 124         do_div(div, pc->data->prescaler * NSEC_PER_SEC);
 125         duty = div;
 126
 127         ret = clk_enable(pc->pclk);
 128         if (ret)
 129                 return ret;
 130
 131         writel(period, pc->base + pc->data->regs.period);
 132         writel(duty, pc->base + pc->data->regs.duty);
 133         writel(0, pc->base + pc->data->regs.cntr);
 134
 135         clk_disable(pc->pclk);
 136
 137 #ifdef CONFIG_FB_ROCKCHIP
 138         if (!pc->data->regs.ctrl) {
 139                 ret = rk_fb_set_vop_pwm();
 140                 if (ret)
 141                         dev_err(pc->chip.dev, "rk_fb_set_vop_pwm failed: %d\n", ret);
 142         }
 143 #endif
 144
 145         return 0;
 146 }
 147
 148 static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
 149                                      struct pwm_device *pwm,
 150                                      enum pwm_polarity polarity)
 151 {
 152         /*
 153          * No action needed here because pwm->polarity will be set by the core
 154          * and the core will only change polarity when the PWM is not enabled.
 155          * We'll handle things in set_enable().
 156          */
 157
 158         return 0;
 159 }
 160
 161 static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 162 {
 163         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 164         int ret;
 165
 166         ret = clk_enable(pc->clk);
 167         if (ret)
 168                 return ret;
 169         ret = clk_enable(pc->pclk);
 170         if (ret)
 171                 return ret;
 172
 173         pc->data->set_enable(chip, pwm, true);
 174
 175         return 0;
 176 }
 177
 178 static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 179 {
 180         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 181
 182         pc->data->set_enable(chip, pwm, false);
 183
 184         clk_disable(pc->pclk);
 185         clk_disable(pc->clk);
 186 }
 187
 188 static const struct pwm_ops rockchip_pwm_ops_v1 = {
 189         .config = rockchip_pwm_config,
 190         .enable = rockchip_pwm_enable,
 191         .disable = rockchip_pwm_disable,
 192         .owner = THIS_MODULE,
 193 };
 194
 195 static const struct pwm_ops rockchip_pwm_ops_v2 = {
 196         .config = rockchip_pwm_config,
 197         .set_polarity = rockchip_pwm_set_polarity,
 198         .enable = rockchip_pwm_enable,
 199         .disable = rockchip_pwm_disable,
 200         .owner = THIS_MODULE,
 201 };
 202
 203 static const struct rockchip_pwm_data pwm_data_v1 = {
 204         .regs = {
 205                 .duty = 0x04,
 206                 .period = 0x08,
 207                 .cntr = 0x00,
 208                 .ctrl = 0x0c,
 209         },
 210         .prescaler = 2,
 211         .ops = &rockchip_pwm_ops_v1,
 212         .set_enable = rockchip_pwm_set_enable_v1,
 213 };
 214
 215 static const struct rockchip_pwm_data pwm_data_v2 = {
 216         .regs = {
 217                 .duty = 0x08,
 218                 .period = 0x04,
 219                 .cntr = 0x00,
 220                 .ctrl = 0x0c,
 221         },
 222         .prescaler = 1,
 223         .ops = &rockchip_pwm_ops_v2,
 224         .set_enable = rockchip_pwm_set_enable_v2,
 225 };
 226
 227 static const struct rockchip_pwm_data pwm_data_vop = {
 228         .regs = {
 229                 .duty = 0x08,
 230                 .period = 0x04,
 231                 .cntr = 0x0c,
 232                 .ctrl = 0x00,
 233         },
 234         .prescaler = 1,
 235         .ops = &rockchip_pwm_ops_v2,
 236         .set_enable = rockchip_pwm_set_enable_v2,
 237 };
 238
 239 static const struct of_device_id rockchip_pwm_dt_ids[] = {
 240         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
 241         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
 242         { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v2},
 243         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
 244         { .compatible = "rockchip,rk3399-pwm", .data = &pwm_data_v2},
 245         { /* sentinel */ }
 246 };
 247 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
 248
 249 static int rockchip_pwm_probe(struct platform_device *pdev)
 250 {
 251         const struct of_device_id *id;
 252         struct rockchip_pwm_chip *pc;
 253         struct resource *r;
 254         int ret, count;
 255
 256         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
 257         if (!id)
 258                 return -EINVAL;
 259
 260         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 261         if (!pc)
 262                 return -ENOMEM;
 263
 264         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265         pc->base = devm_ioremap(&pdev->dev, r->start,
 266                                 resource_size(r));
 267         if (IS_ERR(pc->base))
 268                 return PTR_ERR(pc->base);
 269
 270         pc->clk = devm_clk_get(&pdev->dev, "pwm");
 271         count = of_property_count_strings(pdev->dev.of_node, "clock-names");
 272         if (count == 2)
 273                 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
 274         else
 275                 pc->pclk = pc->clk;
 276
 277         if (IS_ERR(pc->clk)) {
 278                 ret = PTR_ERR(pc->clk);
 279                 if (ret != -EPROBE_DEFER)
 280                         dev_err(&pdev->dev, "Can't get pwm clk: %d\n", ret);
 281                 return ret;
 282         }
 283
 284         if (IS_ERR(pc->pclk)) {
 285                 ret = PTR_ERR(pc->pclk);
 286                 if (ret != -EPROBE_DEFER)
 287                         dev_err(&pdev->dev, "Can't get pclk: %d\n", ret);
 288                 return ret;
 289         }
 290
 291         ret = clk_prepare(pc->clk);
 292         if (ret) {
 293                 dev_err(&pdev->dev, "Can't prepare pwm clk: %d\n", ret);
 294                 return ret;
 295         }
 296
 297         ret = clk_prepare(pc->pclk);
 298         if (ret) {
 299                 dev_err(&pdev->dev, "Can't prepare pclk: %d\n", ret);
 300                 goto err_clk;
 301         }
 302
 303         platform_set_drvdata(pdev, pc);
 304
 305         pc->data = id->data;
 306         pc->chip.dev = &pdev->dev;
 307         pc->chip.ops = pc->data->ops;
 308         pc->chip.base = -1;
 309         pc->chip.npwm = 1;
 310
 311         if (pc->data->ops->set_polarity) {
 312                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
 313                 pc->chip.of_pwm_n_cells = 3;
 314         }
 315
 316         ret = pwmchip_add(&pc->chip);
 317         if (ret < 0) {
 318                 clk_unprepare(pc->clk);
 319                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 320                 goto err_pclk;
 321         }
 322
 323         return 0;
 324
 325 err_pclk:
 326         clk_unprepare(pc->pclk);
 327 err_clk:
 328         clk_unprepare(pc->clk);
 329
 330         return ret;
 331 }
 332
 333 static int rockchip_pwm_remove(struct platform_device *pdev)
 334 {
 335         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
 336
 337         clk_unprepare(pc->pclk);
 338         clk_unprepare(pc->clk);
 339
 340         return pwmchip_remove(&pc->chip);
 341 }
 342
 343 static struct platform_driver rockchip_pwm_driver = {
 344         .driver = {
 345                 .name = "rockchip-pwm",
 346                 .of_match_table = rockchip_pwm_dt_ids,
 347         },
 348         .probe = rockchip_pwm_probe,
 349         .remove = rockchip_pwm_remove,
 350 };
 351 module_platform_driver(rockchip_pwm_driver);
 352
 353 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 354 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
 355 MODULE_LICENSE("GPL v2");