drivers/pwm/pwm-rockchip.c

   1 /*
   2  * PWM driver for Rockchip SoCs
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/time.h>
  20 #include <linux/rk_fb.h>
  21
  22 #define PWM_CTRL_TIMER_EN       (1 << 0)
  23 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
  24
  25 #define PWM_ENABLE              (1 << 0)
  26 #define PWM_CONTINUOUS          (1 << 1)
  27 #define PWM_DUTY_POSITIVE       (1 << 3)
  28 #define PWM_DUTY_NEGATIVE       (0 << 3)
  29 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
  30 #define PWM_INACTIVE_POSITIVE   (1 << 4)
  31 #define PWM_OUTPUT_LEFT         (0 << 5)
  32 #define PWM_LP_DISABLE          (0 << 8)
  33
  34 struct rockchip_pwm_chip {
  35         struct pwm_chip chip;
  36         struct clk *clk;
  37         struct clk *pclk;
  38         const struct rockchip_pwm_data *data;
  39         void __iomem *base;
  40 };
  41
  42 struct rockchip_pwm_regs {
  43         unsigned long duty;
  44         unsigned long period;
  45         unsigned long cntr;
  46         unsigned long ctrl;
  47 };
  48
  49 struct rockchip_pwm_data {
  50         struct rockchip_pwm_regs regs;
  51         unsigned int prescaler;
  52         bool supports_polarity;
  53         const struct pwm_ops *ops;
  54
  55         void (*set_enable)(struct pwm_chip *chip,
  56                            struct pwm_device *pwm, bool enable,
  57                            enum pwm_polarity polarity);
  58         void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
  59                           struct pwm_state *state);
  60 };
  61
  62 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  63 {
  64         return container_of(c, struct rockchip_pwm_chip, chip);
  65 }
  66
  67 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
  68                                        struct pwm_device *pwm, bool enable,
  69                                        enum pwm_polarity polarity)
  70 {
  71         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  72         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  73         u32 val;
  74
  75         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  76
  77         if (enable)
  78                 val |= enable_conf;
  79         else
  80                 val &= ~enable_conf;
  81
  82         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
  83 }
  84
  85 static void rockchip_pwm_get_state_v1(struct pwm_chip *chip,
  86                                       struct pwm_device *pwm,
  87                                       struct pwm_state *state)
  88 {
  89         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  90         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  91         u32 val;
  92
  93         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  94         if ((val & enable_conf) == enable_conf)
  95                 state->enabled = true;
  96 }
  97
  98 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
  99                                        struct pwm_device *pwm, bool enable,
 100                                        enum pwm_polarity polarity)
 101 {
 102         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 103         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 104                           PWM_CONTINUOUS;
 105         u32 val;
 106
 107         if (polarity == PWM_POLARITY_INVERSED)
 108                 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
 109         else
 110                 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
 111
 112         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 113         val &= ~(GENMASK(5, 0) | BIT(8));
 114
 115         if (enable)
 116                 val |= enable_conf;
 117         else
 118                 val &= ~enable_conf;
 119
 120         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
 121 }
 122
 123 static void rockchip_pwm_get_state_v2(struct pwm_chip *chip,
 124                                       struct pwm_device *pwm,
 125                                       struct pwm_state *state)
 126 {
 127         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 128         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 129                           PWM_CONTINUOUS;
 130         u32 val;
 131
 132         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 133         if ((val & enable_conf) != enable_conf)
 134                 return;
 135
 136         state->enabled = true;
 137
 138         if (!(val & PWM_DUTY_POSITIVE))
 139                 state->polarity = PWM_POLARITY_INVERSED;
 140 }
 141
 142 static void rockchip_pwm_get_state(struct pwm_chip *chip,
 143                                    struct pwm_device *pwm,
 144                                    struct pwm_state *state)
 145 {
 146         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 147         unsigned long clk_rate;
 148         u64 tmp;
 149         int ret;
 150
 151         ret = clk_enable(pc->clk);
 152         if (ret)
 153                 return;
 154
 155         clk_rate = clk_get_rate(pc->clk);
 156
 157         tmp = readl_relaxed(pc->base + pc->data->regs.period);
 158         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 159         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 160
 161         tmp = readl_relaxed(pc->base + pc->data->regs.duty);
 162         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 163         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 164
 165         pc->data->get_state(chip, pwm, state);
 166
 167         clk_disable(pc->clk);
 168 }
 169
 170 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 171                                int duty_ns, int period_ns)
 172 {
 173         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 174         unsigned long period, duty;
 175         u64 clk_rate, div;
 176         int ret;
 177
 178         clk_rate = clk_get_rate(pc->clk);
 179
 180         /*
 181          * Since period and duty cycle registers have a width of 32
 182          * bits, every possible input period can be obtained using the
 183          * default prescaler value for all practical clock rate values.
 184          */
 185         div = clk_rate * period_ns;
 186         period = DIV_ROUND_CLOSEST_ULL(div,
 187                                        pc->data->prescaler * NSEC_PER_SEC);
 188
 189         div = clk_rate * duty_ns;
 190         duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
 191
 192         writel(period, pc->base + pc->data->regs.period);
 193         writel(duty, pc->base + pc->data->regs.duty);
 194
 195 #ifdef CONFIG_FB_ROCKCHIP
 196         if (!pc->data->regs.ctrl) {
 197                 ret = rk_fb_set_vop_pwm();
 198                 if (ret)
 199                         dev_err(pc->chip.dev, "rk_fb_set_vop_pwm failed: %d\n", ret);
 200         }
 201 #endif
 202
 203         return 0;
 204 }
 205
 206 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 207                               struct pwm_state *state)
 208 {
 209         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 210         struct pwm_state curstate;
 211         bool enabled;
 212         int ret;
 213
 214         pwm_get_state(pwm, &curstate);
 215         enabled = curstate.enabled;
 216
 217         ret = clk_enable(pc->pclk);
 218         if (ret)
 219                 return ret;
 220
 221         ret = clk_enable(pc->clk);
 222         if (ret)
 223                 return ret;
 224
 225         if (state->polarity != curstate.polarity && enabled) {
 226                 pc->data->set_enable(chip, pwm, false, state->polarity);
 227                 enabled = false;
 228         }
 229
 230         ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
 231         if (ret) {
 232                 if (enabled != curstate.enabled)
 233                         pc->data->set_enable(chip, pwm, !enabled,
 234                                              state->polarity);
 235
 236                 goto out;
 237         }
 238
 239         if (state->enabled != enabled)
 240                 pc->data->set_enable(chip, pwm, state->enabled,
 241                                      state->polarity);
 242
 243         /*
 244          * Update the state with the real hardware, which can differ a bit
 245          * because of period/duty_cycle approximation.
 246          */
 247         rockchip_pwm_get_state(chip, pwm, state);
 248
 249 out:
 250         clk_disable(pc->clk);
 251         clk_disable(pc->pclk);
 252
 253         return ret;
 254 }
 255
 256 static const struct pwm_ops rockchip_pwm_ops_v1 = {
 257         .get_state = rockchip_pwm_get_state,
 258         .apply = rockchip_pwm_apply,
 259         .owner = THIS_MODULE,
 260 };
 261
 262 static const struct pwm_ops rockchip_pwm_ops_v2 = {
 263         .get_state = rockchip_pwm_get_state,
 264         .apply = rockchip_pwm_apply,
 265         .owner = THIS_MODULE,
 266 };
 267
 268 static const struct rockchip_pwm_data pwm_data_v1 = {
 269         .regs = {
 270                 .duty = 0x04,
 271                 .period = 0x08,
 272                 .cntr = 0x00,
 273                 .ctrl = 0x0c,
 274         },
 275         .prescaler = 2,
 276         .ops = &rockchip_pwm_ops_v1,
 277         .set_enable = rockchip_pwm_set_enable_v1,
 278         .get_state = rockchip_pwm_get_state_v1,
 279 };
 280
 281 static const struct rockchip_pwm_data pwm_data_v2 = {
 282         .regs = {
 283                 .duty = 0x08,
 284                 .period = 0x04,
 285                 .cntr = 0x00,
 286                 .ctrl = 0x0c,
 287         },
 288         .prescaler = 1,
 289         .supports_polarity = true,
 290         .ops = &rockchip_pwm_ops_v2,
 291         .set_enable = rockchip_pwm_set_enable_v2,
 292         .get_state = rockchip_pwm_get_state_v2,
 293 };
 294
 295 static const struct rockchip_pwm_data pwm_data_vop = {
 296         .regs = {
 297                 .duty = 0x08,
 298                 .period = 0x04,
 299                 .cntr = 0x0c,
 300                 .ctrl = 0x00,
 301         },
 302         .prescaler = 1,
 303         .supports_polarity = true,
 304         .ops = &rockchip_pwm_ops_v2,
 305         .set_enable = rockchip_pwm_set_enable_v2,
 306         .get_state = rockchip_pwm_get_state_v2,
 307 };
 308
 309 static const struct of_device_id rockchip_pwm_dt_ids[] = {
 310         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
 311         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
 312         { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v2},
 313         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
 314         { .compatible = "rockchip,rk3399-pwm", .data = &pwm_data_v2},
 315         { /* sentinel */ }
 316 };
 317 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
 318
 319 static int rockchip_pwm_probe(struct platform_device *pdev)
 320 {
 321         const struct of_device_id *id;
 322         struct rockchip_pwm_chip *pc;
 323         struct resource *r;
 324         int ret, count;
 325
 326         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
 327         if (!id)
 328                 return -EINVAL;
 329
 330         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 331         if (!pc)
 332                 return -ENOMEM;
 333
 334         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 335         pc->base = devm_ioremap(&pdev->dev, r->start,
 336                                 resource_size(r));
 337         if (IS_ERR(pc->base))
 338                 return PTR_ERR(pc->base);
 339
 340         pc->clk = devm_clk_get(&pdev->dev, "pwm");
 341         count = of_property_count_strings(pdev->dev.of_node, "clock-names");
 342         if (count == 2)
 343                 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
 344         else
 345                 pc->pclk = pc->clk;
 346
 347         if (IS_ERR(pc->clk)) {
 348                 ret = PTR_ERR(pc->clk);
 349                 if (ret != -EPROBE_DEFER)
 350                         dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret);
 351                 return ret;
 352         }
 353
 354         if (IS_ERR(pc->pclk)) {
 355                 ret = PTR_ERR(pc->pclk);
 356                 if (ret != -EPROBE_DEFER)
 357                         dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret);
 358                 return ret;
 359         }
 360
 361         ret = clk_prepare_enable(pc->clk);
 362         if (ret) {
 363                 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
 364                 return ret;
 365         }
 366
 367         ret = clk_prepare_enable(pc->pclk);
 368         if (ret) {
 369                 dev_err(&pdev->dev, "Can't prepare periph clk: %d\n", ret);
 370                 goto err_clk;
 371         }
 372
 373         platform_set_drvdata(pdev, pc);
 374
 375         pc->data = id->data;
 376         pc->chip.dev = &pdev->dev;
 377         pc->chip.ops = pc->data->ops;
 378         pc->chip.base = -1;
 379         pc->chip.npwm = 1;
 380
 381         if (pc->data->supports_polarity) {
 382                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
 383                 pc->chip.of_pwm_n_cells = 3;
 384         }
 385
 386         ret = pwmchip_add(&pc->chip);
 387         if (ret < 0) {
 388                 clk_unprepare(pc->clk);
 389                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 390                 goto err_pclk;
 391         }
 392
 393         /* Keep the PWM clk enabled if the PWM appears to be up and running. */
 394         if (!pwm_is_enabled(pc->chip.pwms)) {
 395                 clk_disable(pc->pclk);
 396                 clk_disable(pc->clk);
 397         }
 398
 399         return 0;
 400
 401 err_pclk:
 402         clk_unprepare(pc->pclk);
 403 err_clk:
 404         clk_unprepare(pc->clk);
 405
 406         return ret;
 407 }
 408
 409 static int rockchip_pwm_remove(struct platform_device *pdev)
 410 {
 411         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
 412
 413         /*
 414          * Disable the PWM clk before unpreparing it if the PWM device is still
 415          * running. This should only happen when the last PWM user left it
 416          * enabled, or when nobody requested a PWM that was previously enabled
 417          * by the bootloader.
 418          *
 419          * FIXME: Maybe the core should disable all PWM devices in
 420          * pwmchip_remove(). In this case we'd only have to call
 421          * clk_unprepare() after pwmchip_remove().
 422          *
 423          */
 424         if (pwm_is_enabled(pc->chip.pwms)) {
 425                 clk_disable(pc->pclk);
 426                 clk_disable(pc->clk);
 427         }
 428
 429         clk_unprepare(pc->pclk);
 430         clk_unprepare(pc->clk);
 431
 432         return pwmchip_remove(&pc->chip);
 433 }
 434
 435 static struct platform_driver rockchip_pwm_driver = {
 436         .driver = {
 437                 .name = "rockchip-pwm",
 438                 .of_match_table = rockchip_pwm_dt_ids,
 439         },
 440         .probe = rockchip_pwm_probe,
 441         .remove = rockchip_pwm_remove,
 442 };
 443 module_platform_driver(rockchip_pwm_driver);
 444
 445 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 446 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
 447 MODULE_LICENSE("GPL v2");