2 * PTP 1588 clock using the EG20T PCH
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
7 * This code was derived from the IXP46X driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/ptp_clock_kernel.h>
33 #include <linux/slab.h>
35 #define STATION_ADDR_LEN 20
36 #define PCI_DEVICE_ID_PCH_1588 0x8819
39 #define DEFAULT_ADDEND 0xA0000000
40 #define TICKS_NS_SHIFT 5
47 PCH_INTERRUPTMODEINUSE,
52 * struct pch_ts_regs - IEEE 1588 registers
91 #define PCH_TSC_RESET (1 << 0)
92 #define PCH_TSC_TTM_MASK (1 << 1)
93 #define PCH_TSC_ASMS_MASK (1 << 2)
94 #define PCH_TSC_AMMS_MASK (1 << 3)
95 #define PCH_TSC_PPSM_MASK (1 << 4)
96 #define PCH_TSE_TTIPEND (1 << 1)
97 #define PCH_TSE_SNS (1 << 2)
98 #define PCH_TSE_SNM (1 << 3)
99 #define PCH_TSE_PPS (1 << 4)
100 #define PCH_CC_MM (1 << 0)
101 #define PCH_CC_TA (1 << 1)
103 #define PCH_CC_MODE_SHIFT 16
104 #define PCH_CC_MODE_MASK 0x001F0000
105 #define PCH_CC_VERSION (1 << 31)
106 #define PCH_CE_TXS (1 << 0)
107 #define PCH_CE_RXS (1 << 1)
108 #define PCH_CE_OVR (1 << 0)
109 #define PCH_CE_VAL (1 << 1)
110 #define PCH_ECS_ETH (1 << 0)
112 #define PCH_ECS_CAN (1 << 1)
113 #define PCH_STATION_BYTES 6
115 #define PCH_IEEE1588_ETH (1 << 0)
116 #define PCH_IEEE1588_CAN (1 << 1)
118 * struct pch_dev - Driver private data
121 struct pch_ts_regs __iomem *regs;
122 struct ptp_clock *ptp_clock;
123 struct ptp_clock_info caps;
130 struct pci_dev *pdev;
131 spinlock_t register_lock;
135 * struct pch_params - 1588 module parameter
138 u8 station[STATION_ADDR_LEN];
141 /* structure to hold the module parameters */
142 static struct pch_params pch_param = {
147 * Register access functions
149 static inline void pch_eth_enable_set(struct pch_dev *chip)
152 /* SET the eth_enable bit */
153 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
154 iowrite32(val, (&chip->regs->ts_sel));
157 static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
162 lo = ioread32(®s->systime_lo);
163 hi = ioread32(®s->systime_hi);
165 ns = ((u64) hi) << 32;
167 ns <<= TICKS_NS_SHIFT;
172 static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
176 ns >>= TICKS_NS_SHIFT;
178 lo = ns & 0xffffffff;
180 iowrite32(lo, ®s->systime_lo);
181 iowrite32(hi, ®s->systime_hi);
184 static inline void pch_block_reset(struct pch_dev *chip)
187 /* Reset Hardware Assist block */
188 val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
189 iowrite32(val, (&chip->regs->control));
190 val = val & ~PCH_TSC_RESET;
191 iowrite32(val, (&chip->regs->control));
194 u32 pch_ch_control_read(struct pci_dev *pdev)
196 struct pch_dev *chip = pci_get_drvdata(pdev);
199 val = ioread32(&chip->regs->ch_control);
203 EXPORT_SYMBOL(pch_ch_control_read);
205 void pch_ch_control_write(struct pci_dev *pdev, u32 val)
207 struct pch_dev *chip = pci_get_drvdata(pdev);
209 iowrite32(val, (&chip->regs->ch_control));
211 EXPORT_SYMBOL(pch_ch_control_write);
213 u32 pch_ch_event_read(struct pci_dev *pdev)
215 struct pch_dev *chip = pci_get_drvdata(pdev);
218 val = ioread32(&chip->regs->ch_event);
222 EXPORT_SYMBOL(pch_ch_event_read);
224 void pch_ch_event_write(struct pci_dev *pdev, u32 val)
226 struct pch_dev *chip = pci_get_drvdata(pdev);
228 iowrite32(val, (&chip->regs->ch_event));
230 EXPORT_SYMBOL(pch_ch_event_write);
232 u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
234 struct pch_dev *chip = pci_get_drvdata(pdev);
237 val = ioread32(&chip->regs->src_uuid_lo);
241 EXPORT_SYMBOL(pch_src_uuid_lo_read);
243 u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
245 struct pch_dev *chip = pci_get_drvdata(pdev);
248 val = ioread32(&chip->regs->src_uuid_hi);
252 EXPORT_SYMBOL(pch_src_uuid_hi_read);
254 u64 pch_rx_snap_read(struct pci_dev *pdev)
256 struct pch_dev *chip = pci_get_drvdata(pdev);
260 lo = ioread32(&chip->regs->rx_snap_lo);
261 hi = ioread32(&chip->regs->rx_snap_hi);
263 ns = ((u64) hi) << 32;
265 ns <<= TICKS_NS_SHIFT;
269 EXPORT_SYMBOL(pch_rx_snap_read);
271 u64 pch_tx_snap_read(struct pci_dev *pdev)
273 struct pch_dev *chip = pci_get_drvdata(pdev);
277 lo = ioread32(&chip->regs->tx_snap_lo);
278 hi = ioread32(&chip->regs->tx_snap_hi);
280 ns = ((u64) hi) << 32;
282 ns <<= TICKS_NS_SHIFT;
286 EXPORT_SYMBOL(pch_tx_snap_read);
288 /* This function enables all 64 bits in system time registers [high & low].
289 This is a work-around for non continuous value in the SystemTime Register*/
290 static void pch_set_system_time_count(struct pch_dev *chip)
292 iowrite32(0x01, &chip->regs->stl_max_set_en);
293 iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
294 iowrite32(0x00, &chip->regs->stl_max_set_en);
297 static void pch_reset(struct pch_dev *chip)
299 /* Reset Hardware Assist */
300 pch_block_reset(chip);
302 /* enable all 32 bits in system time registers */
303 pch_set_system_time_count(chip);
307 * pch_set_station_address() - This API sets the station address used by
308 * IEEE 1588 hardware when looking at PTP
309 * traffic on the ethernet interface
310 * @addr: dress which contain the column separated address to be used.
312 int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
315 struct pch_dev *chip = pci_get_drvdata(pdev);
317 /* Verify the parameter */
318 if ((chip->regs == NULL) || addr == (u8 *)NULL) {
320 "invalid params returning PCH_INVALIDPARAM\n");
321 return PCH_INVALIDPARAM;
323 /* For all station address bytes */
324 for (i = 0; i < PCH_STATION_BYTES; i++) {
328 tmp = hex_to_bin(addr[i * 3]);
331 "invalid params returning PCH_INVALIDPARAM\n");
332 return PCH_INVALIDPARAM;
335 tmp = hex_to_bin(addr[(i * 3) + 1]);
338 "invalid params returning PCH_INVALIDPARAM\n");
339 return PCH_INVALIDPARAM;
342 /* Expects ':' separated addresses */
343 if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
345 "invalid params returning PCH_INVALIDPARAM\n");
346 return PCH_INVALIDPARAM;
349 /* Ideally we should set the address only after validating
351 dev_dbg(&pdev->dev, "invoking pch_station_set\n");
352 iowrite32(val, &chip->regs->ts_st[i]);
356 EXPORT_SYMBOL(pch_set_station_address);
359 * Interrupt service routine
361 static irqreturn_t isr(int irq, void *priv)
363 struct pch_dev *pch_dev = priv;
364 struct pch_ts_regs __iomem *regs = pch_dev->regs;
365 struct ptp_clock_event event;
366 u32 ack = 0, lo, hi, val;
368 val = ioread32(®s->event);
370 if (val & PCH_TSE_SNS) {
372 if (pch_dev->exts0_enabled) {
373 hi = ioread32(®s->asms_hi);
374 lo = ioread32(®s->asms_lo);
375 event.type = PTP_CLOCK_EXTTS;
377 event.timestamp = ((u64) hi) << 32;
378 event.timestamp |= lo;
379 event.timestamp <<= TICKS_NS_SHIFT;
380 ptp_clock_event(pch_dev->ptp_clock, &event);
384 if (val & PCH_TSE_SNM) {
386 if (pch_dev->exts1_enabled) {
387 hi = ioread32(®s->amms_hi);
388 lo = ioread32(®s->amms_lo);
389 event.type = PTP_CLOCK_EXTTS;
391 event.timestamp = ((u64) hi) << 32;
392 event.timestamp |= lo;
393 event.timestamp <<= TICKS_NS_SHIFT;
394 ptp_clock_event(pch_dev->ptp_clock, &event);
398 if (val & PCH_TSE_TTIPEND)
399 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
402 iowrite32(ack, ®s->event);
409 * PTP clock operations
412 static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
417 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
418 struct pch_ts_regs __iomem *regs = pch_dev->regs;
424 addend = DEFAULT_ADDEND;
427 diff = div_u64(adj, 1000000000ULL);
429 addend = neg_adj ? addend - diff : addend + diff;
431 iowrite32(addend, ®s->addend);
436 static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
440 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
441 struct pch_ts_regs __iomem *regs = pch_dev->regs;
443 spin_lock_irqsave(&pch_dev->register_lock, flags);
444 now = pch_systime_read(regs);
446 pch_systime_write(regs, now);
447 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
452 static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
457 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
458 struct pch_ts_regs __iomem *regs = pch_dev->regs;
460 spin_lock_irqsave(&pch_dev->register_lock, flags);
461 ns = pch_systime_read(regs);
462 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
464 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
465 ts->tv_nsec = remainder;
469 static int ptp_pch_settime(struct ptp_clock_info *ptp,
470 const struct timespec64 *ts)
474 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
475 struct pch_ts_regs __iomem *regs = pch_dev->regs;
477 ns = ts->tv_sec * 1000000000ULL;
480 spin_lock_irqsave(&pch_dev->register_lock, flags);
481 pch_systime_write(regs, ns);
482 spin_unlock_irqrestore(&pch_dev->register_lock, flags);
487 static int ptp_pch_enable(struct ptp_clock_info *ptp,
488 struct ptp_clock_request *rq, int on)
490 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
493 case PTP_CLK_REQ_EXTTS:
494 switch (rq->extts.index) {
496 pch_dev->exts0_enabled = on ? 1 : 0;
499 pch_dev->exts1_enabled = on ? 1 : 0;
512 static struct ptp_clock_info ptp_pch_caps = {
513 .owner = THIS_MODULE,
516 .n_ext_ts = N_EXT_TS,
519 .adjfreq = ptp_pch_adjfreq,
520 .adjtime = ptp_pch_adjtime,
521 .gettime64 = ptp_pch_gettime,
522 .settime64 = ptp_pch_settime,
523 .enable = ptp_pch_enable,
528 static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
530 pci_disable_device(pdev);
531 pci_enable_wake(pdev, PCI_D3hot, 0);
533 if (pci_save_state(pdev) != 0) {
534 dev_err(&pdev->dev, "could not save PCI config state\n");
537 pci_set_power_state(pdev, pci_choose_state(pdev, state));
542 static s32 pch_resume(struct pci_dev *pdev)
546 pci_set_power_state(pdev, PCI_D0);
547 pci_restore_state(pdev);
548 ret = pci_enable_device(pdev);
550 dev_err(&pdev->dev, "pci_enable_device failed\n");
553 pci_enable_wake(pdev, PCI_D3hot, 0);
557 #define pch_suspend NULL
558 #define pch_resume NULL
561 static void pch_remove(struct pci_dev *pdev)
563 struct pch_dev *chip = pci_get_drvdata(pdev);
565 ptp_clock_unregister(chip->ptp_clock);
566 /* free the interrupt */
568 free_irq(pdev->irq, chip);
570 /* unmap the virtual IO memory space */
571 if (chip->regs != NULL) {
575 /* release the reserved IO memory space */
576 if (chip->mem_base != 0) {
577 release_mem_region(chip->mem_base, chip->mem_size);
580 pci_disable_device(pdev);
582 dev_info(&pdev->dev, "complete\n");
586 pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
590 struct pch_dev *chip;
592 chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
596 /* enable the 1588 pci device */
597 ret = pci_enable_device(pdev);
599 dev_err(&pdev->dev, "could not enable the pci device\n");
603 chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
604 if (!chip->mem_base) {
605 dev_err(&pdev->dev, "could not locate IO memory address\n");
610 /* retrieve the available length of the IO memory space */
611 chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
613 /* allocate the memory for the device registers */
614 if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
616 "could not allocate register memory space\n");
618 goto err_req_mem_region;
621 /* get the virtual address to the 1588 registers */
622 chip->regs = ioremap(chip->mem_base, chip->mem_size);
625 dev_err(&pdev->dev, "Could not get virtual address\n");
630 chip->caps = ptp_pch_caps;
631 chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
632 if (IS_ERR(chip->ptp_clock)) {
633 ret = PTR_ERR(chip->ptp_clock);
634 goto err_ptp_clock_reg;
637 spin_lock_init(&chip->register_lock);
639 ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
641 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
645 /* indicate success */
646 chip->irq = pdev->irq;
648 pci_set_drvdata(pdev, chip);
650 spin_lock_irqsave(&chip->register_lock, flags);
651 /* reset the ieee1588 h/w */
654 iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
655 iowrite32(1, &chip->regs->trgt_lo);
656 iowrite32(0, &chip->regs->trgt_hi);
657 iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
659 pch_eth_enable_set(chip);
661 if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
662 if (pch_set_station_address(pch_param.station, pdev) != 0) {
664 "Invalid station address parameter\n"
665 "Module loaded but station address not set correctly\n"
669 spin_unlock_irqrestore(&chip->register_lock, flags);
673 ptp_clock_unregister(chip->ptp_clock);
679 release_mem_region(chip->mem_base, chip->mem_size);
685 pci_disable_device(pdev);
689 dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
694 static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
696 .vendor = PCI_VENDOR_ID_INTEL,
697 .device = PCI_DEVICE_ID_PCH_1588
702 static struct pci_driver pch_driver = {
703 .name = KBUILD_MODNAME,
704 .id_table = pch_ieee1588_pcidev_id,
706 .remove = pch_remove,
707 .suspend = pch_suspend,
708 .resume = pch_resume,
711 static void __exit ptp_pch_exit(void)
713 pci_unregister_driver(&pch_driver);
716 static s32 __init ptp_pch_init(void)
720 /* register the driver with the pci core */
721 ret = pci_register_driver(&pch_driver);
726 module_init(ptp_pch_init);
727 module_exit(ptp_pch_exit);
729 module_param_string(station,
730 pch_param.station, sizeof(pch_param.station), 0444);
731 MODULE_PARM_DESC(station,
732 "IEEE 1588 station address to use - colon separated hex values");
734 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
735 MODULE_DESCRIPTION("PTP clock using the EG20T timer");
736 MODULE_LICENSE("GPL");