2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/bitops.h>
27 #include <linux/gpio.h>
28 #include <linux/of_gpio.h>
29 #include <asm/mach/irq.h>
31 #include "pinctrl-sirf.h"
33 #define DRIVER_NAME "pinmux-sirf"
35 struct sirfsoc_gpio_bank {
36 struct of_mm_gpio_chip chip;
37 struct irq_domain *domain;
41 bool is_marco; /* for marco, some registers are different with prima2 */
44 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45 static DEFINE_SPINLOCK(sgpio_lock);
47 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
48 static int sirfsoc_pingrp_cnt;
50 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
52 return sirfsoc_pingrp_cnt;
55 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
58 return sirfsoc_pin_groups[selector].name;
61 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
62 const unsigned **pins,
65 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins;
70 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
73 seq_printf(s, " " DRIVER_NAME);
76 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
77 struct device_node *np_config,
78 struct pinctrl_map **map, unsigned *num_maps)
80 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
81 struct device_node *np;
82 struct property *prop;
83 const char *function, *group;
84 int ret, index = 0, count = 0;
86 /* calculate number of maps required */
87 for_each_child_of_node(np_config, np) {
88 ret = of_property_read_string(np, "sirf,function", &function);
92 ret = of_property_count_strings(np, "sirf,pins");
100 dev_err(spmx->dev, "No child nodes passed via DT\n");
104 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
108 for_each_child_of_node(np_config, np) {
109 of_property_read_string(np, "sirf,function", &function);
110 of_property_for_each_string(np, "sirf,pins", prop, group) {
111 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
112 (*map)[index].data.mux.group = group;
113 (*map)[index].data.mux.function = function;
123 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
124 struct pinctrl_map *map, unsigned num_maps)
129 static struct pinctrl_ops sirfsoc_pctrl_ops = {
130 .get_groups_count = sirfsoc_get_groups_count,
131 .get_group_name = sirfsoc_get_group_name,
132 .get_group_pins = sirfsoc_get_group_pins,
133 .pin_dbg_show = sirfsoc_pin_dbg_show,
134 .dt_node_to_map = sirfsoc_dt_node_to_map,
135 .dt_free_map = sirfsoc_dt_free_map,
138 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139 static int sirfsoc_pmxfunc_cnt;
141 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask;
148 for (i = 0; i < mux->muxmask_counts; i++) {
150 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
153 muxval = muxval & ~mask[i].mask;
155 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
159 writel(mask[i].mask, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
162 writel(mask[i].mask, spmx->gpio_virtbase +
163 SIRFSOC_GPIO_PAD_EN(mask[i].group));
167 if (mux->funcmask && enable) {
171 readl(spmx->rsc_virtbase + mux->ctrlreg);
173 (func_en_val & ~mux->funcmask) | (mux->funcval);
174 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
178 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
181 struct sirfsoc_pmx *spmx;
183 spmx = pinctrl_dev_get_drvdata(pmxdev);
184 sirfsoc_pinmux_endisable(spmx, selector, true);
189 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
192 struct sirfsoc_pmx *spmx;
194 spmx = pinctrl_dev_get_drvdata(pmxdev);
195 sirfsoc_pinmux_endisable(spmx, selector, false);
198 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
200 return sirfsoc_pmxfunc_cnt;
203 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
206 return sirfsoc_pmx_functions[selector].name;
209 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
210 const char * const **groups,
211 unsigned * const num_groups)
213 *groups = sirfsoc_pmx_functions[selector].groups;
214 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
218 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
219 struct pinctrl_gpio_range *range, unsigned offset)
221 struct sirfsoc_pmx *spmx;
223 int group = range->id;
227 spmx = pinctrl_dev_get_drvdata(pmxdev);
229 if (!spmx->is_marco) {
230 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
231 muxval = muxval | (1 << (offset - range->pin_base));
232 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
234 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
235 SIRFSOC_GPIO_PAD_EN(group));
241 static struct pinmux_ops sirfsoc_pinmux_ops = {
242 .enable = sirfsoc_pinmux_enable,
243 .disable = sirfsoc_pinmux_disable,
244 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
245 .get_function_name = sirfsoc_pinmux_get_func_name,
246 .get_function_groups = sirfsoc_pinmux_get_groups,
247 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
250 static struct pinctrl_desc sirfsoc_pinmux_desc = {
252 .pctlops = &sirfsoc_pctrl_ops,
253 .pmxops = &sirfsoc_pinmux_ops,
254 .owner = THIS_MODULE,
258 * Todo: bind irq_chip to every pinctrl_gpio_range
260 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
262 .name = "sirfsoc-gpio*",
268 .name = "sirfsoc-gpio*",
274 .name = "sirfsoc-gpio*",
280 .name = "sirfsoc-gpio*",
288 static void __iomem *sirfsoc_rsc_of_iomap(void)
290 const struct of_device_id rsc_ids[] = {
291 { .compatible = "sirf,prima2-rsc" },
292 { .compatible = "sirf,marco-rsc" },
295 struct device_node *np;
297 np = of_find_matching_node(NULL, rsc_ids);
299 panic("unable to find compatible rsc node in dtb\n");
301 return of_iomap(np, 0);
304 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
305 const struct of_phandle_args *gpiospec,
308 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
311 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
315 *flags = gpiospec->args[1];
317 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
320 static const struct of_device_id pinmux_ids[] = {
321 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
322 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
323 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
327 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
330 struct sirfsoc_pmx *spmx;
331 struct device_node *np = pdev->dev.of_node;
332 const struct sirfsoc_pinctrl_data *pdata;
335 /* Create state holders etc for this driver */
336 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
340 spmx->dev = &pdev->dev;
342 platform_set_drvdata(pdev, spmx);
344 spmx->gpio_virtbase = of_iomap(np, 0);
345 if (!spmx->gpio_virtbase) {
346 dev_err(&pdev->dev, "can't map gpio registers\n");
350 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
351 if (!spmx->rsc_virtbase) {
353 dev_err(&pdev->dev, "can't map rsc registers\n");
354 goto out_no_rsc_remap;
357 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
360 pdata = of_match_node(pinmux_ids, np)->data;
361 sirfsoc_pin_groups = pdata->grps;
362 sirfsoc_pingrp_cnt = pdata->grps_cnt;
363 sirfsoc_pmx_functions = pdata->funcs;
364 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
365 sirfsoc_pinmux_desc.pins = pdata->pads;
366 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
369 /* Now register the pin controller and all pins it handles */
370 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
372 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
377 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
378 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
379 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
382 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
387 iounmap(spmx->rsc_virtbase);
389 iounmap(spmx->gpio_virtbase);
393 #ifdef CONFIG_PM_SLEEP
394 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
397 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
399 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
400 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
401 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
402 SIRFSOC_GPIO_CTRL(i, j));
404 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
405 SIRFSOC_GPIO_INT_STATUS(i));
406 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
407 SIRFSOC_GPIO_PAD_EN(i));
409 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
411 for (i = 0; i < 3; i++)
412 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
417 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
420 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
422 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
423 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
424 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
425 SIRFSOC_GPIO_CTRL(i, j));
427 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
428 SIRFSOC_GPIO_INT_STATUS(i));
429 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
430 SIRFSOC_GPIO_PAD_EN(i));
432 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
434 for (i = 0; i < 3; i++)
435 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
440 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
441 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
442 .resume_noirq = sirfsoc_pinmux_resume_noirq,
443 .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
444 .restore_noirq = sirfsoc_pinmux_resume_noirq,
448 static struct platform_driver sirfsoc_pinmux_driver = {
451 .owner = THIS_MODULE,
452 .of_match_table = pinmux_ids,
453 #ifdef CONFIG_PM_SLEEP
454 .pm = &sirfsoc_pinmux_pm_ops,
457 .probe = sirfsoc_pinmux_probe,
460 static int __init sirfsoc_pinmux_init(void)
462 return platform_driver_register(&sirfsoc_pinmux_driver);
464 arch_initcall(sirfsoc_pinmux_init);
466 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
468 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
469 struct sirfsoc_gpio_bank, chip);
471 return irq_create_mapping(bank->domain, offset);
474 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
476 return gpio % SIRFSOC_GPIO_BANK_SIZE;
479 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
481 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
484 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
486 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
489 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
491 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
492 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
496 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
498 spin_lock_irqsave(&sgpio_lock, flags);
500 val = readl(bank->chip.regs + offset);
502 writel(val, bank->chip.regs + offset);
504 spin_unlock_irqrestore(&sgpio_lock, flags);
507 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
512 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
514 spin_lock_irqsave(&sgpio_lock, flags);
516 val = readl(bank->chip.regs + offset);
517 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
518 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
519 writel(val, bank->chip.regs + offset);
521 spin_unlock_irqrestore(&sgpio_lock, flags);
524 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
526 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
528 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
531 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
533 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
534 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
538 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
540 spin_lock_irqsave(&sgpio_lock, flags);
542 val = readl(bank->chip.regs + offset);
543 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
544 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
545 writel(val, bank->chip.regs + offset);
547 spin_unlock_irqrestore(&sgpio_lock, flags);
550 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
552 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
553 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
557 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
559 spin_lock_irqsave(&sgpio_lock, flags);
561 val = readl(bank->chip.regs + offset);
562 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
567 case IRQ_TYPE_EDGE_RISING:
568 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
569 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
571 case IRQ_TYPE_EDGE_FALLING:
572 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
573 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
575 case IRQ_TYPE_EDGE_BOTH:
576 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
577 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
579 case IRQ_TYPE_LEVEL_LOW:
580 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
581 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
583 case IRQ_TYPE_LEVEL_HIGH:
584 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
585 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
589 writel(val, bank->chip.regs + offset);
591 spin_unlock_irqrestore(&sgpio_lock, flags);
596 static struct irq_chip sirfsoc_irq_chip = {
597 .name = "sirf-gpio-irq",
598 .irq_ack = sirfsoc_gpio_irq_ack,
599 .irq_mask = sirfsoc_gpio_irq_mask,
600 .irq_unmask = sirfsoc_gpio_irq_unmask,
601 .irq_set_type = sirfsoc_gpio_irq_type,
604 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
606 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
609 struct irq_chip *chip = irq_get_chip(irq);
611 chained_irq_enter(chip, desc);
613 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
616 "%s: gpio id %d status %#x no interrupt is flaged\n",
617 __func__, bank->id, status);
618 handle_bad_irq(irq, desc);
623 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
626 * Here we must check whether the corresponding GPIO's interrupt
627 * has been enabled, otherwise just skip it
629 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
630 pr_debug("%s: gpio id %d idx %d happens\n",
631 __func__, bank->id, idx);
632 generic_handle_irq(irq_find_mapping(bank->domain, idx));
636 status = status >> 1;
639 chained_irq_exit(chip, desc);
642 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
646 val = readl(bank->chip.regs + ctrl_offset);
647 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
648 writel(val, bank->chip.regs + ctrl_offset);
651 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
653 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
656 if (pinctrl_request_gpio(chip->base + offset))
659 spin_lock_irqsave(&bank->lock, flags);
663 * set direction as input and mask irq
665 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
666 __sirfsoc_gpio_irq_mask(bank, offset);
668 spin_unlock_irqrestore(&bank->lock, flags);
673 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
675 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
678 spin_lock_irqsave(&bank->lock, flags);
680 __sirfsoc_gpio_irq_mask(bank, offset);
681 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
683 spin_unlock_irqrestore(&bank->lock, flags);
685 pinctrl_free_gpio(chip->base + offset);
688 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
690 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
691 int idx = sirfsoc_gpio_to_offset(gpio);
695 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
697 spin_lock_irqsave(&bank->lock, flags);
699 sirfsoc_gpio_set_input(bank, offset);
701 spin_unlock_irqrestore(&bank->lock, flags);
706 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
712 spin_lock_irqsave(&bank->lock, flags);
714 out_ctrl = readl(bank->chip.regs + offset);
716 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
718 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
720 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
721 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
722 writel(out_ctrl, bank->chip.regs + offset);
724 spin_unlock_irqrestore(&bank->lock, flags);
727 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
729 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
730 int idx = sirfsoc_gpio_to_offset(gpio);
734 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
736 spin_lock_irqsave(&sgpio_lock, flags);
738 sirfsoc_gpio_set_output(bank, offset, value);
740 spin_unlock_irqrestore(&sgpio_lock, flags);
745 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
747 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
751 spin_lock_irqsave(&bank->lock, flags);
753 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
755 spin_unlock_irqrestore(&bank->lock, flags);
757 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
760 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
763 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
767 spin_lock_irqsave(&bank->lock, flags);
769 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
771 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
773 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
774 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
776 spin_unlock_irqrestore(&bank->lock, flags);
779 static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
780 irq_hw_number_t hwirq)
782 struct sirfsoc_gpio_bank *bank = d->host_data;
787 irq_set_chip(irq, &sirfsoc_irq_chip);
788 irq_set_handler(irq, handle_level_irq);
789 irq_set_chip_data(irq, bank);
790 set_irq_flags(irq, IRQF_VALID);
795 static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
796 .map = sirfsoc_gpio_irq_map,
797 .xlate = irq_domain_xlate_twocell,
800 static void sirfsoc_gpio_set_pullup(const u32 *pullups)
803 const unsigned long *p = (const unsigned long *)pullups;
805 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
806 for_each_set_bit(n, p + i, BITS_PER_LONG) {
807 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
808 u32 val = readl(sgpio_bank[i].chip.regs + offset);
809 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
810 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
811 writel(val, sgpio_bank[i].chip.regs + offset);
816 static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
819 const unsigned long *p = (const unsigned long *)pulldowns;
821 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
822 for_each_set_bit(n, p + i, BITS_PER_LONG) {
823 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
824 u32 val = readl(sgpio_bank[i].chip.regs + offset);
825 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
826 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
827 writel(val, sgpio_bank[i].chip.regs + offset);
832 static int sirfsoc_gpio_probe(struct device_node *np)
835 struct sirfsoc_gpio_bank *bank;
837 struct platform_device *pdev;
838 bool is_marco = false;
840 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
842 pdev = of_find_device_by_node(np);
846 regs = of_iomap(np, 0);
850 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
853 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
854 bank = &sgpio_bank[i];
855 spin_lock_init(&bank->lock);
856 bank->chip.gc.request = sirfsoc_gpio_request;
857 bank->chip.gc.free = sirfsoc_gpio_free;
858 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
859 bank->chip.gc.get = sirfsoc_gpio_get_value;
860 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
861 bank->chip.gc.set = sirfsoc_gpio_set_value;
862 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
863 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
864 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
865 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
866 bank->chip.gc.of_node = np;
867 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
868 bank->chip.gc.of_gpio_n_cells = 2;
869 bank->chip.regs = regs;
871 bank->is_marco = is_marco;
872 bank->parent_irq = platform_get_irq(pdev, i);
873 if (bank->parent_irq < 0) {
874 err = bank->parent_irq;
878 err = gpiochip_add(&bank->chip.gc);
880 pr_err("%s: error in probe function with status %d\n",
885 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
886 &sirfsoc_gpio_irq_simple_ops, bank);
889 pr_err("%s: Failed to create irqdomain\n", np->full_name);
894 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
895 irq_set_handler_data(bank->parent_irq, bank);
898 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
899 SIRFSOC_GPIO_NO_OF_BANKS))
900 sirfsoc_gpio_set_pullup(pullups);
902 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
903 SIRFSOC_GPIO_NO_OF_BANKS))
904 sirfsoc_gpio_set_pulldown(pulldowns);
913 static int __init sirfsoc_gpio_init(void)
916 struct device_node *np;
918 np = of_find_matching_node(NULL, pinmux_ids);
923 return sirfsoc_gpio_probe(np);
925 subsys_initcall(sirfsoc_gpio_init);
927 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
928 "Yuping Luo <yuping.luo@csr.com>, "
929 "Barry Song <baohua.song@csr.com>");
930 MODULE_DESCRIPTION("SIRFSOC pin control driver");
931 MODULE_LICENSE("GPL");