2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/irq.h>
13 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
29 #include "pinctrl-sirf.h"
31 #define DRIVER_NAME "pinmux-sirf"
33 struct sirfsoc_gpio_bank {
39 struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip;
41 bool is_marco; /* for marco, some registers are different with prima2 */
42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45 static DEFINE_SPINLOCK(sgpio_lock);
47 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
48 static int sirfsoc_pingrp_cnt;
50 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
52 return sirfsoc_pingrp_cnt;
55 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
58 return sirfsoc_pin_groups[selector].name;
61 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
63 const unsigned **pins,
66 *pins = sirfsoc_pin_groups[selector].pins;
67 *num_pins = sirfsoc_pin_groups[selector].num_pins;
71 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
72 struct seq_file *s, unsigned offset)
74 seq_printf(s, " " DRIVER_NAME);
77 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
78 struct device_node *np_config,
79 struct pinctrl_map **map, unsigned *num_maps)
81 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
82 struct device_node *np;
83 struct property *prop;
84 const char *function, *group;
85 int ret, index = 0, count = 0;
87 /* calculate number of maps required */
88 for_each_child_of_node(np_config, np) {
89 ret = of_property_read_string(np, "sirf,function", &function);
93 ret = of_property_count_strings(np, "sirf,pins");
101 dev_err(spmx->dev, "No child nodes passed via DT\n");
105 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
109 for_each_child_of_node(np_config, np) {
110 of_property_read_string(np, "sirf,function", &function);
111 of_property_for_each_string(np, "sirf,pins", prop, group) {
112 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
113 (*map)[index].data.mux.group = group;
114 (*map)[index].data.mux.function = function;
124 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
125 struct pinctrl_map *map, unsigned num_maps)
130 static struct pinctrl_ops sirfsoc_pctrl_ops = {
131 .get_groups_count = sirfsoc_get_groups_count,
132 .get_group_name = sirfsoc_get_group_name,
133 .get_group_pins = sirfsoc_get_group_pins,
134 .pin_dbg_show = sirfsoc_pin_dbg_show,
135 .dt_node_to_map = sirfsoc_dt_node_to_map,
136 .dt_free_map = sirfsoc_dt_free_map,
139 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
140 static int sirfsoc_pmxfunc_cnt;
142 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
143 unsigned selector, bool enable)
146 const struct sirfsoc_padmux *mux =
147 sirfsoc_pmx_functions[selector].padmux;
148 const struct sirfsoc_muxmask *mask = mux->muxmask;
150 for (i = 0; i < mux->muxmask_counts; i++) {
152 if (!spmx->is_marco) {
153 muxval = readl(spmx->gpio_virtbase +
154 SIRFSOC_GPIO_PAD_EN(mask[i].group));
156 muxval = muxval & ~mask[i].mask;
158 muxval = muxval | mask[i].mask;
159 writel(muxval, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN(mask[i].group));
163 writel(mask[i].mask, spmx->gpio_virtbase +
164 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
166 writel(mask[i].mask, spmx->gpio_virtbase +
167 SIRFSOC_GPIO_PAD_EN(mask[i].group));
171 if (mux->funcmask && enable) {
175 readl(spmx->rsc_virtbase + mux->ctrlreg);
177 (func_en_val & ~mux->funcmask) | (mux->funcval);
178 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
182 static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
186 struct sirfsoc_pmx *spmx;
188 spmx = pinctrl_dev_get_drvdata(pmxdev);
189 sirfsoc_pinmux_endisable(spmx, selector, true);
194 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
196 return sirfsoc_pmxfunc_cnt;
199 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
202 return sirfsoc_pmx_functions[selector].name;
205 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
207 const char * const **groups,
208 unsigned * const num_groups)
210 *groups = sirfsoc_pmx_functions[selector].groups;
211 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
215 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
216 struct pinctrl_gpio_range *range, unsigned offset)
218 struct sirfsoc_pmx *spmx;
220 int group = range->id;
224 spmx = pinctrl_dev_get_drvdata(pmxdev);
226 if (!spmx->is_marco) {
227 muxval = readl(spmx->gpio_virtbase +
228 SIRFSOC_GPIO_PAD_EN(group));
229 muxval = muxval | (1 << (offset - range->pin_base));
230 writel(muxval, spmx->gpio_virtbase +
231 SIRFSOC_GPIO_PAD_EN(group));
233 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
234 SIRFSOC_GPIO_PAD_EN(group));
240 static struct pinmux_ops sirfsoc_pinmux_ops = {
241 .set_mux = sirfsoc_pinmux_set_mux,
242 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
243 .get_function_name = sirfsoc_pinmux_get_func_name,
244 .get_function_groups = sirfsoc_pinmux_get_groups,
245 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
248 static struct pinctrl_desc sirfsoc_pinmux_desc = {
250 .pctlops = &sirfsoc_pctrl_ops,
251 .pmxops = &sirfsoc_pinmux_ops,
252 .owner = THIS_MODULE,
255 static void __iomem *sirfsoc_rsc_of_iomap(void)
257 const struct of_device_id rsc_ids[] = {
258 { .compatible = "sirf,prima2-rsc" },
259 { .compatible = "sirf,marco-rsc" },
262 struct device_node *np;
264 np = of_find_matching_node(NULL, rsc_ids);
266 panic("unable to find compatible rsc node in dtb\n");
268 return of_iomap(np, 0);
271 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
272 const struct of_phandle_args *gpiospec,
275 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
279 *flags = gpiospec->args[1];
281 return gpiospec->args[0];
284 static const struct of_device_id pinmux_ids[] = {
285 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
286 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
287 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
291 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
294 struct sirfsoc_pmx *spmx;
295 struct device_node *np = pdev->dev.of_node;
296 const struct sirfsoc_pinctrl_data *pdata;
298 /* Create state holders etc for this driver */
299 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
303 spmx->dev = &pdev->dev;
305 platform_set_drvdata(pdev, spmx);
307 spmx->gpio_virtbase = of_iomap(np, 0);
308 if (!spmx->gpio_virtbase) {
309 dev_err(&pdev->dev, "can't map gpio registers\n");
313 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
314 if (!spmx->rsc_virtbase) {
316 dev_err(&pdev->dev, "can't map rsc registers\n");
317 goto out_no_rsc_remap;
320 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
323 pdata = of_match_node(pinmux_ids, np)->data;
324 sirfsoc_pin_groups = pdata->grps;
325 sirfsoc_pingrp_cnt = pdata->grps_cnt;
326 sirfsoc_pmx_functions = pdata->funcs;
327 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
328 sirfsoc_pinmux_desc.pins = pdata->pads;
329 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
332 /* Now register the pin controller and all pins it handles */
333 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
335 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
340 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
345 iounmap(spmx->rsc_virtbase);
347 iounmap(spmx->gpio_virtbase);
351 #ifdef CONFIG_PM_SLEEP
352 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
355 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
357 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
358 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
359 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
360 SIRFSOC_GPIO_CTRL(i, j));
362 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
363 SIRFSOC_GPIO_INT_STATUS(i));
364 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
365 SIRFSOC_GPIO_PAD_EN(i));
367 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
369 for (i = 0; i < 3; i++)
370 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
375 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
378 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
380 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
381 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
382 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
383 SIRFSOC_GPIO_CTRL(i, j));
385 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
386 SIRFSOC_GPIO_INT_STATUS(i));
387 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
388 SIRFSOC_GPIO_PAD_EN(i));
390 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
392 for (i = 0; i < 3; i++)
393 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
398 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
399 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
400 .resume_noirq = sirfsoc_pinmux_resume_noirq,
401 .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
402 .restore_noirq = sirfsoc_pinmux_resume_noirq,
406 static struct platform_driver sirfsoc_pinmux_driver = {
409 .owner = THIS_MODULE,
410 .of_match_table = pinmux_ids,
411 #ifdef CONFIG_PM_SLEEP
412 .pm = &sirfsoc_pinmux_pm_ops,
415 .probe = sirfsoc_pinmux_probe,
418 static int __init sirfsoc_pinmux_init(void)
420 return platform_driver_register(&sirfsoc_pinmux_driver);
422 arch_initcall(sirfsoc_pinmux_init);
424 static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
426 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
429 static inline struct sirfsoc_gpio_bank *
430 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
432 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
435 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
437 return offset % SIRFSOC_GPIO_BANK_SIZE;
440 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
442 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
443 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
444 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
445 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
449 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
451 spin_lock_irqsave(&sgpio_lock, flags);
453 val = readl(sgpio->chip.regs + offset);
455 writel(val, sgpio->chip.regs + offset);
457 spin_unlock_irqrestore(&sgpio_lock, flags);
460 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
461 struct sirfsoc_gpio_bank *bank,
467 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
469 spin_lock_irqsave(&sgpio_lock, flags);
471 val = readl(sgpio->chip.regs + offset);
472 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
473 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
474 writel(val, sgpio->chip.regs + offset);
476 spin_unlock_irqrestore(&sgpio_lock, flags);
479 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
481 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
482 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
483 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
485 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
488 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
490 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
491 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
492 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
493 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
497 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
499 spin_lock_irqsave(&sgpio_lock, flags);
501 val = readl(sgpio->chip.regs + offset);
502 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
503 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
504 writel(val, sgpio->chip.regs + offset);
506 spin_unlock_irqrestore(&sgpio_lock, flags);
509 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
511 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
512 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
513 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
514 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
518 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
520 spin_lock_irqsave(&sgpio_lock, flags);
522 val = readl(sgpio->chip.regs + offset);
523 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
528 case IRQ_TYPE_EDGE_RISING:
529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
531 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
533 case IRQ_TYPE_EDGE_FALLING:
534 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
535 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
536 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
538 case IRQ_TYPE_EDGE_BOTH:
539 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
540 SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
541 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
543 case IRQ_TYPE_LEVEL_LOW:
544 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
545 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
546 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
548 case IRQ_TYPE_LEVEL_HIGH:
549 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
550 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
551 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
555 writel(val, sgpio->chip.regs + offset);
557 spin_unlock_irqrestore(&sgpio_lock, flags);
562 static struct irq_chip sirfsoc_irq_chip = {
563 .name = "sirf-gpio-irq",
564 .irq_ack = sirfsoc_gpio_irq_ack,
565 .irq_mask = sirfsoc_gpio_irq_mask,
566 .irq_unmask = sirfsoc_gpio_irq_unmask,
567 .irq_set_type = sirfsoc_gpio_irq_type,
570 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
572 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
573 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
574 struct sirfsoc_gpio_bank *bank;
577 struct irq_chip *chip = irq_get_chip(irq);
580 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
581 bank = &sgpio->sgpio_bank[i];
582 if (bank->parent_irq == irq)
585 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
587 chained_irq_enter(chip, desc);
589 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
592 "%s: gpio id %d status %#x no interrupt is flaged\n",
593 __func__, bank->id, status);
594 handle_bad_irq(irq, desc);
599 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
602 * Here we must check whether the corresponding GPIO's interrupt
603 * has been enabled, otherwise just skip it
605 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
606 pr_debug("%s: gpio id %d idx %d happens\n",
607 __func__, bank->id, idx);
608 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
609 bank->id * SIRFSOC_GPIO_BANK_SIZE));
613 status = status >> 1;
616 chained_irq_exit(chip, desc);
619 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
620 unsigned ctrl_offset)
624 val = readl(sgpio->chip.regs + ctrl_offset);
625 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
626 writel(val, sgpio->chip.regs + ctrl_offset);
629 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
631 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
632 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
635 if (pinctrl_request_gpio(chip->base + offset))
638 spin_lock_irqsave(&bank->lock, flags);
642 * set direction as input and mask irq
644 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
645 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
647 spin_unlock_irqrestore(&bank->lock, flags);
652 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
654 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
655 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
658 spin_lock_irqsave(&bank->lock, flags);
660 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
661 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
663 spin_unlock_irqrestore(&bank->lock, flags);
665 pinctrl_free_gpio(chip->base + offset);
668 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
670 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
671 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
672 int idx = sirfsoc_gpio_to_bankoff(gpio);
676 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
678 spin_lock_irqsave(&bank->lock, flags);
680 sirfsoc_gpio_set_input(sgpio, offset);
682 spin_unlock_irqrestore(&bank->lock, flags);
687 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
688 struct sirfsoc_gpio_bank *bank,
695 spin_lock_irqsave(&bank->lock, flags);
697 out_ctrl = readl(sgpio->chip.regs + offset);
699 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
701 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
703 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
704 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
705 writel(out_ctrl, sgpio->chip.regs + offset);
707 spin_unlock_irqrestore(&bank->lock, flags);
710 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
711 unsigned gpio, int value)
713 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
715 int idx = sirfsoc_gpio_to_bankoff(gpio);
719 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
721 spin_lock_irqsave(&sgpio_lock, flags);
723 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
725 spin_unlock_irqrestore(&sgpio_lock, flags);
730 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
732 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
733 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
737 spin_lock_irqsave(&bank->lock, flags);
739 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
741 spin_unlock_irqrestore(&bank->lock, flags);
743 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
746 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
749 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
750 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
754 spin_lock_irqsave(&bank->lock, flags);
756 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
758 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
760 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
761 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
763 spin_unlock_irqrestore(&bank->lock, flags);
766 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
770 const unsigned long *p = (const unsigned long *)pullups;
772 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
773 for_each_set_bit(n, p + i, BITS_PER_LONG) {
774 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
775 u32 val = readl(sgpio->chip.regs + offset);
776 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
777 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
778 writel(val, sgpio->chip.regs + offset);
783 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
784 const u32 *pulldowns)
787 const unsigned long *p = (const unsigned long *)pulldowns;
789 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
790 for_each_set_bit(n, p + i, BITS_PER_LONG) {
791 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
792 u32 val = readl(sgpio->chip.regs + offset);
793 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
794 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
795 writel(val, sgpio->chip.regs + offset);
800 static int sirfsoc_gpio_probe(struct device_node *np)
803 static struct sirfsoc_gpio_chip *sgpio;
804 struct sirfsoc_gpio_bank *bank;
806 struct platform_device *pdev;
807 bool is_marco = false;
809 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
811 pdev = of_find_device_by_node(np);
815 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
819 regs = of_iomap(np, 0);
823 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
826 sgpio->chip.gc.request = sirfsoc_gpio_request;
827 sgpio->chip.gc.free = sirfsoc_gpio_free;
828 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
829 sgpio->chip.gc.get = sirfsoc_gpio_get_value;
830 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
831 sgpio->chip.gc.set = sirfsoc_gpio_set_value;
832 sgpio->chip.gc.base = 0;
833 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
834 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
835 sgpio->chip.gc.of_node = np;
836 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
837 sgpio->chip.gc.of_gpio_n_cells = 2;
838 sgpio->chip.gc.dev = &pdev->dev;
839 sgpio->chip.regs = regs;
840 sgpio->is_marco = is_marco;
842 err = gpiochip_add(&sgpio->chip.gc);
844 dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
849 err = gpiochip_irqchip_add(&sgpio->chip.gc,
855 "could not connect irqchip to gpiochip\n");
859 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
860 bank = &sgpio->sgpio_bank[i];
861 spin_lock_init(&bank->lock);
862 bank->parent_irq = platform_get_irq(pdev, i);
863 if (bank->parent_irq < 0) {
864 err = bank->parent_irq;
868 gpiochip_set_chained_irqchip(&sgpio->chip.gc,
871 sirfsoc_gpio_handle_irq);
874 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
875 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
878 "could not add gpiochip pin range\n");
882 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
883 SIRFSOC_GPIO_NO_OF_BANKS))
884 sirfsoc_gpio_set_pullup(sgpio, pullups);
886 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
887 SIRFSOC_GPIO_NO_OF_BANKS))
888 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
894 gpiochip_remove(&sgpio->chip.gc);
900 static int __init sirfsoc_gpio_init(void)
903 struct device_node *np;
905 np = of_find_matching_node(NULL, pinmux_ids);
910 return sirfsoc_gpio_probe(np);
912 subsys_initcall(sirfsoc_gpio_init);
914 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
915 MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
916 MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
917 MODULE_DESCRIPTION("SIRFSOC pin control driver");
918 MODULE_LICENSE("GPL");