drivers/pinctrl/sh-pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <linux/bitops.h>
  15 #include <linux/err.h>
  16 #include <linux/errno.h>
  17 #include <linux/io.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/pinctrl/machine.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26
  27 #include "core.h"
  28
  29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  30                                 struct platform_device *pdev)
  31 {
  32         unsigned int num_windows = 0;
  33         unsigned int num_irqs = 0;
  34         struct sh_pfc_window *windows;
  35         unsigned int *irqs = NULL;
  36         struct resource *res;
  37         unsigned int i;
  38
  39         /* Count the MEM and IRQ resources. */
  40         for (i = 0; i < pdev->num_resources; ++i) {
  41                 switch (resource_type(&pdev->resource[i])) {
  42                 case IORESOURCE_MEM:
  43                         num_windows++;
  44                         break;
  45
  46                 case IORESOURCE_IRQ:
  47                         num_irqs++;
  48                         break;
  49                 }
  50         }
  51
  52         if (num_windows == 0)
  53                 return -EINVAL;
  54
  55         /* Allocate memory windows and IRQs arrays. */
  56         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
  57                                GFP_KERNEL);
  58         if (windows == NULL)
  59                 return -ENOMEM;
  60
  61         pfc->num_windows = num_windows;
  62         pfc->windows = windows;
  63
  64         if (num_irqs) {
  65                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
  66                                     GFP_KERNEL);
  67                 if (irqs == NULL)
  68                         return -ENOMEM;
  69
  70                 pfc->num_irqs = num_irqs;
  71                 pfc->irqs = irqs;
  72         }
  73
  74         /* Fill them. */
  75         for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
  76                 switch (resource_type(res)) {
  77                 case IORESOURCE_MEM:
  78                         windows->phys = res->start;
  79                         windows->size = resource_size(res);
  80                         windows->virt = devm_ioremap_resource(pfc->dev, res);
  81                         if (IS_ERR(windows->virt))
  82                                 return -ENOMEM;
  83                         windows++;
  84                         break;
  85
  86                 case IORESOURCE_IRQ:
  87                         *irqs++ = res->start;
  88                         break;
  89                 }
  90         }
  91
  92         return 0;
  93 }
  94
  95 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
  96                                          unsigned long address)
  97 {
  98         struct sh_pfc_window *window;
  99         unsigned int i;
 100
 101         /* scan through physical windows and convert address */
 102         for (i = 0; i < pfc->num_windows; i++) {
 103                 window = pfc->windows + i;
 104
 105                 if (address < window->phys)
 106                         continue;
 107
 108                 if (address >= (window->phys + window->size))
 109                         continue;
 110
 111                 return window->virt + (address - window->phys);
 112         }
 113
 114         BUG();
 115         return NULL;
 116 }
 117
 118 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 119 {
 120         unsigned int offset;
 121         unsigned int i;
 122
 123         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 124                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 125
 126                 if (pin <= range->end)
 127                         return pin >= range->start
 128                              ? offset + pin - range->start : -1;
 129
 130                 offset += range->end - range->start + 1;
 131         }
 132
 133         return -EINVAL;
 134 }
 135
 136 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 137 {
 138         if (enum_id < r->begin)
 139                 return 0;
 140
 141         if (enum_id > r->end)
 142                 return 0;
 143
 144         return 1;
 145 }
 146
 147 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned long reg_width)
 148 {
 149         switch (reg_width) {
 150         case 8:
 151                 return ioread8(mapped_reg);
 152         case 16:
 153                 return ioread16(mapped_reg);
 154         case 32:
 155                 return ioread32(mapped_reg);
 156         }
 157
 158         BUG();
 159         return 0;
 160 }
 161
 162 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
 163                           u32 data)
 164 {
 165         switch (reg_width) {
 166         case 8:
 167                 iowrite8(data, mapped_reg);
 168                 return;
 169         case 16:
 170                 iowrite16(data, mapped_reg);
 171                 return;
 172         case 32:
 173                 iowrite32(data, mapped_reg);
 174                 return;
 175         }
 176
 177         BUG();
 178 }
 179
 180 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 181                                      const struct pinmux_cfg_reg *crp,
 182                                      unsigned long in_pos,
 183                                      void __iomem **mapped_regp, u32 *maskp,
 184                                      unsigned long *posp)
 185 {
 186         unsigned int k;
 187
 188         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 189
 190         if (crp->field_width) {
 191                 *maskp = (1 << crp->field_width) - 1;
 192                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 193         } else {
 194                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 195                 *posp = crp->reg_width;
 196                 for (k = 0; k <= in_pos; k++)
 197                         *posp -= crp->var_field_width[k];
 198         }
 199 }
 200
 201 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 202                                     const struct pinmux_cfg_reg *crp,
 203                                     unsigned long field, u32 value)
 204 {
 205         void __iomem *mapped_reg;
 206         unsigned long pos;
 207         u32 mask, data;
 208
 209         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 210
 211         dev_dbg(pfc->dev, "write_reg addr = %lx, value = 0x%x, field = %ld, "
 212                 "r_width = %u, f_width = %u\n",
 213                 crp->reg, value, field, crp->reg_width, crp->field_width);
 214
 215         mask = ~(mask << pos);
 216         value = value << pos;
 217
 218         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 219         data &= mask;
 220         data |= value;
 221
 222         if (pfc->info->unlock_reg)
 223                 sh_pfc_write_raw_reg(
 224                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 225                         ~data);
 226
 227         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 228 }
 229
 230 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 231                                  const struct pinmux_cfg_reg **crp, int *fieldp,
 232                                  u32 *valuep)
 233 {
 234         const struct pinmux_cfg_reg *config_reg;
 235         unsigned long r_width, f_width, curr_width;
 236         unsigned int k, m, pos, bit_pos;
 237         u32 ncomb, n;
 238
 239         k = 0;
 240         while (1) {
 241                 config_reg = pfc->info->cfg_regs + k;
 242
 243                 r_width = config_reg->reg_width;
 244                 f_width = config_reg->field_width;
 245
 246                 if (!r_width)
 247                         break;
 248
 249                 pos = 0;
 250                 m = 0;
 251                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 252                         if (f_width)
 253                                 curr_width = f_width;
 254                         else
 255                                 curr_width = config_reg->var_field_width[m];
 256
 257                         ncomb = 1 << curr_width;
 258                         for (n = 0; n < ncomb; n++) {
 259                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 260                                         *crp = config_reg;
 261                                         *fieldp = m;
 262                                         *valuep = n;
 263                                         return 0;
 264                                 }
 265                         }
 266                         pos += ncomb;
 267                         m++;
 268                 }
 269                 k++;
 270         }
 271
 272         return -EINVAL;
 273 }
 274
 275 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 276                               u16 *enum_idp)
 277 {
 278         const u16 *data = pfc->info->gpio_data;
 279         unsigned int k;
 280
 281         if (pos) {
 282                 *enum_idp = data[pos + 1];
 283                 return pos + 1;
 284         }
 285
 286         for (k = 0; k < pfc->info->gpio_data_size; k++) {
 287                 if (data[k] == mark) {
 288                         *enum_idp = data[k + 1];
 289                         return k + 1;
 290                 }
 291         }
 292
 293         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 294                 mark);
 295         return -EINVAL;
 296 }
 297
 298 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 299 {
 300         const struct pinmux_cfg_reg *cr = NULL;
 301         u16 enum_id;
 302         const struct pinmux_range *range;
 303         int in_range, pos, field;
 304         u32 value;
 305         int ret;
 306
 307         switch (pinmux_type) {
 308         case PINMUX_TYPE_GPIO:
 309         case PINMUX_TYPE_FUNCTION:
 310                 range = NULL;
 311                 break;
 312
 313         case PINMUX_TYPE_OUTPUT:
 314                 range = &pfc->info->output;
 315                 break;
 316
 317         case PINMUX_TYPE_INPUT:
 318                 range = &pfc->info->input;
 319                 break;
 320
 321         default:
 322                 return -EINVAL;
 323         }
 324
 325         pos = 0;
 326         enum_id = 0;
 327         field = 0;
 328         value = 0;
 329
 330         /* Iterate over all the configuration fields we need to update. */
 331         while (1) {
 332                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 333                 if (pos < 0)
 334                         return pos;
 335
 336                 if (!enum_id)
 337                         break;
 338
 339                 /* Check if the configuration field selects a function. If it
 340                  * doesn't, skip the field if it's not applicable to the
 341                  * requested pinmux type.
 342                  */
 343                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 344                 if (!in_range) {
 345                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 346                                 /* Functions are allowed to modify all
 347                                  * fields.
 348                                  */
 349                                 in_range = 1;
 350                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 351                                 /* Input/output types can only modify fields
 352                                  * that correspond to their respective ranges.
 353                                  */
 354                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 355
 356                                 /*
 357                                  * special case pass through for fixed
 358                                  * input-only or output-only pins without
 359                                  * function enum register association.
 360                                  */
 361                                 if (in_range && enum_id == range->force)
 362                                         continue;
 363                         }
 364                         /* GPIOs are only allowed to modify function fields. */
 365                 }
 366
 367                 if (!in_range)
 368                         continue;
 369
 370                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 371                 if (ret < 0)
 372                         return ret;
 373
 374                 sh_pfc_write_config_reg(pfc, cr, field, value);
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 381 {
 382         struct sh_pfc_pin_range *range;
 383         unsigned int nr_ranges;
 384         unsigned int i;
 385
 386         if (pfc->info->pins[0].pin == (u16)-1) {
 387                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 388                  * in its pin arrays yet. Consider the pin numbers range as
 389                  * continuous and allocate a single range.
 390                  */
 391                 pfc->nr_ranges = 1;
 392                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 393                                            GFP_KERNEL);
 394                 if (pfc->ranges == NULL)
 395                         return -ENOMEM;
 396
 397                 pfc->ranges->start = 0;
 398                 pfc->ranges->end = pfc->info->nr_pins - 1;
 399                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 400
 401                 return 0;
 402         }
 403
 404         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 405          * be sorted by pin numbers, and pins without a GPIO port must come
 406          * last.
 407          */
 408         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 409                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 410                         nr_ranges++;
 411         }
 412
 413         pfc->nr_ranges = nr_ranges;
 414         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
 415                                    GFP_KERNEL);
 416         if (pfc->ranges == NULL)
 417                 return -ENOMEM;
 418
 419         range = pfc->ranges;
 420         range->start = pfc->info->pins[0].pin;
 421
 422         for (i = 1; i < pfc->info->nr_pins; ++i) {
 423                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 424                         continue;
 425
 426                 range->end = pfc->info->pins[i-1].pin;
 427                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 428                         pfc->nr_gpio_pins = range->end + 1;
 429
 430                 range++;
 431                 range->start = pfc->info->pins[i].pin;
 432         }
 433
 434         range->end = pfc->info->pins[i-1].pin;
 435         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 436                 pfc->nr_gpio_pins = range->end + 1;
 437
 438         return 0;
 439 }
 440
 441 #ifdef CONFIG_OF
 442 static const struct of_device_id sh_pfc_of_table[] = {
 443 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 444         {
 445                 .compatible = "renesas,pfc-emev2",
 446                 .data = &emev2_pinmux_info,
 447         },
 448 #endif
 449 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 450         {
 451                 .compatible = "renesas,pfc-r8a73a4",
 452                 .data = &r8a73a4_pinmux_info,
 453         },
 454 #endif
 455 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 456         {
 457                 .compatible = "renesas,pfc-r8a7740",
 458                 .data = &r8a7740_pinmux_info,
 459         },
 460 #endif
 461 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 462         {
 463                 .compatible = "renesas,pfc-r8a7778",
 464                 .data = &r8a7778_pinmux_info,
 465         },
 466 #endif
 467 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 468         {
 469                 .compatible = "renesas,pfc-r8a7779",
 470                 .data = &r8a7779_pinmux_info,
 471         },
 472 #endif
 473 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 474         {
 475                 .compatible = "renesas,pfc-r8a7790",
 476                 .data = &r8a7790_pinmux_info,
 477         },
 478 #endif
 479 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 480         {
 481                 .compatible = "renesas,pfc-r8a7791",
 482                 .data = &r8a7791_pinmux_info,
 483         },
 484 #endif
 485 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 486         {
 487                 .compatible = "renesas,pfc-sh73a0",
 488                 .data = &sh73a0_pinmux_info,
 489         },
 490 #endif
 491         { },
 492 };
 493 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
 494 #endif
 495
 496 static int sh_pfc_probe(struct platform_device *pdev)
 497 {
 498         const struct platform_device_id *platid = platform_get_device_id(pdev);
 499 #ifdef CONFIG_OF
 500         struct device_node *np = pdev->dev.of_node;
 501 #endif
 502         const struct sh_pfc_soc_info *info;
 503         struct sh_pfc *pfc;
 504         int ret;
 505
 506 #ifdef CONFIG_OF
 507         if (np)
 508                 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
 509         else
 510 #endif
 511                 info = platid ? (const void *)platid->driver_data : NULL;
 512
 513         if (info == NULL)
 514                 return -ENODEV;
 515
 516         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
 517         if (pfc == NULL)
 518                 return -ENOMEM;
 519
 520         pfc->info = info;
 521         pfc->dev = &pdev->dev;
 522
 523         ret = sh_pfc_map_resources(pfc, pdev);
 524         if (unlikely(ret < 0))
 525                 return ret;
 526
 527         spin_lock_init(&pfc->lock);
 528
 529         if (info->ops && info->ops->init) {
 530                 ret = info->ops->init(pfc);
 531                 if (ret < 0)
 532                         return ret;
 533         }
 534
 535         pinctrl_provide_dummies();
 536
 537         ret = sh_pfc_init_ranges(pfc);
 538         if (ret < 0)
 539                 return ret;
 540
 541         /*
 542          * Initialize pinctrl bindings first
 543          */
 544         ret = sh_pfc_register_pinctrl(pfc);
 545         if (unlikely(ret != 0))
 546                 return ret;
 547
 548 #ifdef CONFIG_GPIO_SH_PFC
 549         /*
 550          * Then the GPIO chip
 551          */
 552         ret = sh_pfc_register_gpiochip(pfc);
 553         if (unlikely(ret != 0)) {
 554                 /*
 555                  * If the GPIO chip fails to come up we still leave the
 556                  * PFC state as it is, given that there are already
 557                  * extant users of it that have succeeded by this point.
 558                  */
 559                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
 560         }
 561 #endif
 562
 563         platform_set_drvdata(pdev, pfc);
 564
 565         dev_info(pfc->dev, "%s support registered\n", info->name);
 566
 567         return 0;
 568 }
 569
 570 static int sh_pfc_remove(struct platform_device *pdev)
 571 {
 572         struct sh_pfc *pfc = platform_get_drvdata(pdev);
 573
 574 #ifdef CONFIG_GPIO_SH_PFC
 575         sh_pfc_unregister_gpiochip(pfc);
 576 #endif
 577         sh_pfc_unregister_pinctrl(pfc);
 578
 579         return 0;
 580 }
 581
 582 static const struct platform_device_id sh_pfc_id_table[] = {
 583 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 584         { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
 585 #endif
 586 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 587         { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
 588 #endif
 589 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 590         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 591 #endif
 592 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 593         { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
 594 #endif
 595 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 596         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 597 #endif
 598 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 599         { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
 600 #endif
 601 #ifdef CONFIG_PINCTRL_PFC_SH7203
 602         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 603 #endif
 604 #ifdef CONFIG_PINCTRL_PFC_SH7264
 605         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 606 #endif
 607 #ifdef CONFIG_PINCTRL_PFC_SH7269
 608         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 609 #endif
 610 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 611         { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
 612 #endif
 613 #ifdef CONFIG_PINCTRL_PFC_SH7720
 614         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 615 #endif
 616 #ifdef CONFIG_PINCTRL_PFC_SH7722
 617         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 618 #endif
 619 #ifdef CONFIG_PINCTRL_PFC_SH7723
 620         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 621 #endif
 622 #ifdef CONFIG_PINCTRL_PFC_SH7724
 623         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 624 #endif
 625 #ifdef CONFIG_PINCTRL_PFC_SH7734
 626         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 627 #endif
 628 #ifdef CONFIG_PINCTRL_PFC_SH7757
 629         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
 630 #endif
 631 #ifdef CONFIG_PINCTRL_PFC_SH7785
 632         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
 633 #endif
 634 #ifdef CONFIG_PINCTRL_PFC_SH7786
 635         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
 636 #endif
 637 #ifdef CONFIG_PINCTRL_PFC_SHX3
 638         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
 639 #endif
 640         { "sh-pfc", 0 },
 641         { },
 642 };
 643 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
 644
 645 static struct platform_driver sh_pfc_driver = {
 646         .probe          = sh_pfc_probe,
 647         .remove         = sh_pfc_remove,
 648         .id_table       = sh_pfc_id_table,
 649         .driver         = {
 650                 .name   = DRV_NAME,
 651                 .of_match_table = of_match_ptr(sh_pfc_of_table),
 652         },
 653 };
 654
 655 static int __init sh_pfc_init(void)
 656 {
 657         return platform_driver_register(&sh_pfc_driver);
 658 }
 659 postcore_initcall(sh_pfc_init);
 660
 661 static void __exit sh_pfc_exit(void)
 662 {
 663         platform_driver_unregister(&sh_pfc_driver);
 664 }
 665 module_exit(sh_pfc_exit);
 666
 667 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
 668 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
 669 MODULE_LICENSE("GPL v2");