2 * SuperH Pin Function Controller support.
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #define DRV_NAME "sh-pfc"
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
32 unsigned int num_windows, num_irqs;
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
39 /* Count the MEM and IRQ resources. */
40 for (num_windows = 0;; num_windows++) {
41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
45 for (num_irqs = 0;; num_irqs++) {
46 irq = platform_get_irq(pdev, num_irqs);
47 if (irq == -EPROBE_DEFER)
56 /* Allocate memory windows and IRQs arrays. */
57 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
62 pfc->num_windows = num_windows;
63 pfc->windows = windows;
66 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
71 pfc->num_irqs = num_irqs;
76 for (i = 0; i < num_windows; i++) {
77 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
85 for (i = 0; i < num_irqs; i++)
86 *irqs++ = platform_get_irq(pdev, i);
91 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
93 struct sh_pfc_window *window;
94 phys_addr_t address = reg;
97 /* scan through physical windows and convert address */
98 for (i = 0; i < pfc->num_windows; i++) {
99 window = pfc->windows + i;
101 if (address < window->phys)
104 if (address >= (window->phys + window->size))
107 return window->virt + (address - window->phys);
114 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
119 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
120 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
122 if (pin <= range->end)
123 return pin >= range->start
124 ? offset + pin - range->start : -1;
126 offset += range->end - range->start + 1;
132 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
134 if (enum_id < r->begin)
137 if (enum_id > r->end)
143 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
147 return ioread8(mapped_reg);
149 return ioread16(mapped_reg);
151 return ioread32(mapped_reg);
158 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
163 iowrite8(data, mapped_reg);
166 iowrite16(data, mapped_reg);
169 iowrite32(data, mapped_reg);
176 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
177 const struct pinmux_cfg_reg *crp,
179 void __iomem **mapped_regp, u32 *maskp,
184 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
186 if (crp->field_width) {
187 *maskp = (1 << crp->field_width) - 1;
188 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
190 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
191 *posp = crp->reg_width;
192 for (k = 0; k <= in_pos; k++)
193 *posp -= crp->var_field_width[k];
197 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
198 const struct pinmux_cfg_reg *crp,
199 unsigned int field, u32 value)
201 void __iomem *mapped_reg;
205 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
207 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
208 "r_width = %u, f_width = %u\n",
209 crp->reg, value, field, crp->reg_width, crp->field_width);
211 mask = ~(mask << pos);
212 value = value << pos;
214 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
218 if (pfc->info->unlock_reg)
219 sh_pfc_write_raw_reg(
220 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
223 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
226 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
227 const struct pinmux_cfg_reg **crp,
228 unsigned int *fieldp, u32 *valuep)
233 const struct pinmux_cfg_reg *config_reg =
234 pfc->info->cfg_regs + k;
235 unsigned int r_width = config_reg->reg_width;
236 unsigned int f_width = config_reg->field_width;
237 unsigned int curr_width;
238 unsigned int bit_pos;
239 unsigned int pos = 0;
245 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
250 curr_width = f_width;
252 curr_width = config_reg->var_field_width[m];
254 ncomb = 1 << curr_width;
255 for (n = 0; n < ncomb; n++) {
256 if (config_reg->enum_ids[pos + n] == enum_id) {
272 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
275 const u16 *data = pfc->info->gpio_data;
279 *enum_idp = data[pos + 1];
283 for (k = 0; k < pfc->info->gpio_data_size; k++) {
284 if (data[k] == mark) {
285 *enum_idp = data[k + 1];
290 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
295 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
297 const struct pinmux_range *range;
300 switch (pinmux_type) {
301 case PINMUX_TYPE_GPIO:
302 case PINMUX_TYPE_FUNCTION:
306 case PINMUX_TYPE_OUTPUT:
307 range = &pfc->info->output;
310 case PINMUX_TYPE_INPUT:
311 range = &pfc->info->input;
318 /* Iterate over all the configuration fields we need to update. */
320 const struct pinmux_cfg_reg *cr;
327 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
334 /* Check if the configuration field selects a function. If it
335 * doesn't, skip the field if it's not applicable to the
336 * requested pinmux type.
338 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
340 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
341 /* Functions are allowed to modify all
345 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
346 /* Input/output types can only modify fields
347 * that correspond to their respective ranges.
349 in_range = sh_pfc_enum_in_range(enum_id, range);
352 * special case pass through for fixed
353 * input-only or output-only pins without
354 * function enum register association.
356 if (in_range && enum_id == range->force)
359 /* GPIOs are only allowed to modify function fields. */
365 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
369 sh_pfc_write_config_reg(pfc, cr, field, value);
375 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
377 struct sh_pfc_pin_range *range;
378 unsigned int nr_ranges;
381 if (pfc->info->pins[0].pin == (u16)-1) {
382 /* Pin number -1 denotes that the SoC doesn't report pin numbers
383 * in its pin arrays yet. Consider the pin numbers range as
384 * continuous and allocate a single range.
387 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
389 if (pfc->ranges == NULL)
392 pfc->ranges->start = 0;
393 pfc->ranges->end = pfc->info->nr_pins - 1;
394 pfc->nr_gpio_pins = pfc->info->nr_pins;
399 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
400 * be sorted by pin numbers, and pins without a GPIO port must come
403 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
404 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
408 pfc->nr_ranges = nr_ranges;
409 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
411 if (pfc->ranges == NULL)
415 range->start = pfc->info->pins[0].pin;
417 for (i = 1; i < pfc->info->nr_pins; ++i) {
418 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
421 range->end = pfc->info->pins[i-1].pin;
422 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
423 pfc->nr_gpio_pins = range->end + 1;
426 range->start = pfc->info->pins[i].pin;
429 range->end = pfc->info->pins[i-1].pin;
430 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
431 pfc->nr_gpio_pins = range->end + 1;
437 static const struct of_device_id sh_pfc_of_table[] = {
438 #ifdef CONFIG_PINCTRL_PFC_EMEV2
440 .compatible = "renesas,pfc-emev2",
441 .data = &emev2_pinmux_info,
444 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
446 .compatible = "renesas,pfc-r8a73a4",
447 .data = &r8a73a4_pinmux_info,
450 #ifdef CONFIG_PINCTRL_PFC_R8A7740
452 .compatible = "renesas,pfc-r8a7740",
453 .data = &r8a7740_pinmux_info,
456 #ifdef CONFIG_PINCTRL_PFC_R8A7778
458 .compatible = "renesas,pfc-r8a7778",
459 .data = &r8a7778_pinmux_info,
462 #ifdef CONFIG_PINCTRL_PFC_R8A7779
464 .compatible = "renesas,pfc-r8a7779",
465 .data = &r8a7779_pinmux_info,
468 #ifdef CONFIG_PINCTRL_PFC_R8A7790
470 .compatible = "renesas,pfc-r8a7790",
471 .data = &r8a7790_pinmux_info,
474 #ifdef CONFIG_PINCTRL_PFC_R8A7791
476 .compatible = "renesas,pfc-r8a7791",
477 .data = &r8a7791_pinmux_info,
480 #ifdef CONFIG_PINCTRL_PFC_R8A7793
482 .compatible = "renesas,pfc-r8a7793",
483 .data = &r8a7793_pinmux_info,
486 #ifdef CONFIG_PINCTRL_PFC_R8A7794
488 .compatible = "renesas,pfc-r8a7794",
489 .data = &r8a7794_pinmux_info,
492 #ifdef CONFIG_PINCTRL_PFC_SH73A0
494 .compatible = "renesas,pfc-sh73a0",
495 .data = &sh73a0_pinmux_info,
500 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
503 static int sh_pfc_probe(struct platform_device *pdev)
505 const struct platform_device_id *platid = platform_get_device_id(pdev);
507 struct device_node *np = pdev->dev.of_node;
509 const struct sh_pfc_soc_info *info;
515 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
518 info = platid ? (const void *)platid->driver_data : NULL;
523 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
528 pfc->dev = &pdev->dev;
530 ret = sh_pfc_map_resources(pfc, pdev);
531 if (unlikely(ret < 0))
534 spin_lock_init(&pfc->lock);
536 if (info->ops && info->ops->init) {
537 ret = info->ops->init(pfc);
542 pinctrl_provide_dummies();
544 ret = sh_pfc_init_ranges(pfc);
549 * Initialize pinctrl bindings first
551 ret = sh_pfc_register_pinctrl(pfc);
552 if (unlikely(ret != 0))
555 #ifdef CONFIG_GPIO_SH_PFC
559 ret = sh_pfc_register_gpiochip(pfc);
560 if (unlikely(ret != 0)) {
562 * If the GPIO chip fails to come up we still leave the
563 * PFC state as it is, given that there are already
564 * extant users of it that have succeeded by this point.
566 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
570 platform_set_drvdata(pdev, pfc);
572 dev_info(pfc->dev, "%s support registered\n", info->name);
577 static int sh_pfc_remove(struct platform_device *pdev)
579 struct sh_pfc *pfc = platform_get_drvdata(pdev);
581 #ifdef CONFIG_GPIO_SH_PFC
582 sh_pfc_unregister_gpiochip(pfc);
584 sh_pfc_unregister_pinctrl(pfc);
589 static const struct platform_device_id sh_pfc_id_table[] = {
590 #ifdef CONFIG_PINCTRL_PFC_R8A7778
591 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
593 #ifdef CONFIG_PINCTRL_PFC_R8A7779
594 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
596 #ifdef CONFIG_PINCTRL_PFC_SH7203
597 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
599 #ifdef CONFIG_PINCTRL_PFC_SH7264
600 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
602 #ifdef CONFIG_PINCTRL_PFC_SH7269
603 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
605 #ifdef CONFIG_PINCTRL_PFC_SH7720
606 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
608 #ifdef CONFIG_PINCTRL_PFC_SH7722
609 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
611 #ifdef CONFIG_PINCTRL_PFC_SH7723
612 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
614 #ifdef CONFIG_PINCTRL_PFC_SH7724
615 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
617 #ifdef CONFIG_PINCTRL_PFC_SH7734
618 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
620 #ifdef CONFIG_PINCTRL_PFC_SH7757
621 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
623 #ifdef CONFIG_PINCTRL_PFC_SH7785
624 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
626 #ifdef CONFIG_PINCTRL_PFC_SH7786
627 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
629 #ifdef CONFIG_PINCTRL_PFC_SHX3
630 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
635 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
637 static struct platform_driver sh_pfc_driver = {
638 .probe = sh_pfc_probe,
639 .remove = sh_pfc_remove,
640 .id_table = sh_pfc_id_table,
643 .of_match_table = of_match_ptr(sh_pfc_of_table),
647 static int __init sh_pfc_init(void)
649 return platform_driver_register(&sh_pfc_driver);
651 postcore_initcall(sh_pfc_init);
653 static void __exit sh_pfc_exit(void)
655 platform_driver_unregister(&sh_pfc_driver);
657 module_exit(sh_pfc_exit);
659 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
660 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
661 MODULE_LICENSE("GPL v2");