2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
36 struct exynos_irq_chip {
44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
46 return container_of(chip, struct exynos_irq_chip, chip);
49 static struct samsung_pin_bank_type bank_type_off = {
50 .fld_width = { 4, 1, 2, 2, 2, 2, },
51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
54 static struct samsung_pin_bank_type bank_type_alive = {
55 .fld_width = { 4, 1, 2, 2, },
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
59 /* list of external wakeup controllers supported */
60 static const struct of_device_id exynos_wkup_irq_ids[] = {
61 { .compatible = "samsung,exynos4210-wakeup-eint", },
65 static void exynos_irq_mask(struct irq_data *irqd)
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
75 spin_lock_irqsave(&bank->slock, flags);
77 mask = readl(d->virt_base + reg_mask);
78 mask |= 1 << irqd->hwirq;
79 writel(mask, d->virt_base + reg_mask);
81 spin_unlock_irqrestore(&bank->slock, flags);
84 static void exynos_irq_ack(struct irq_data *irqd)
86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
95 static void exynos_irq_unmask(struct irq_data *irqd)
97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
106 * Ack level interrupts right before unmask
108 * If we don't do this we'll get a double-interrupt. Level triggered
109 * interrupts must not fire an interrupt if the level is not
110 * _currently_ active, even if it was active while the interrupt was
113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
114 exynos_irq_ack(irqd);
116 spin_lock_irqsave(&bank->slock, flags);
118 mask = readl(d->virt_base + reg_mask);
119 mask &= ~(1 << irqd->hwirq);
120 writel(mask, d->virt_base + reg_mask);
122 spin_unlock_irqrestore(&bank->slock, flags);
125 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
130 struct samsung_pinctrl_drv_data *d = bank->drvdata;
131 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
132 unsigned int con, trig_type;
133 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
136 case IRQ_TYPE_EDGE_RISING:
137 trig_type = EXYNOS_EINT_EDGE_RISING;
139 case IRQ_TYPE_EDGE_FALLING:
140 trig_type = EXYNOS_EINT_EDGE_FALLING;
142 case IRQ_TYPE_EDGE_BOTH:
143 trig_type = EXYNOS_EINT_EDGE_BOTH;
145 case IRQ_TYPE_LEVEL_HIGH:
146 trig_type = EXYNOS_EINT_LEVEL_HIGH;
148 case IRQ_TYPE_LEVEL_LOW:
149 trig_type = EXYNOS_EINT_LEVEL_LOW;
152 pr_err("unsupported external interrupt type\n");
156 if (type & IRQ_TYPE_EDGE_BOTH)
157 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
159 __irq_set_handler_locked(irqd->irq, handle_level_irq);
161 con = readl(d->virt_base + reg_con);
162 con &= ~(EXYNOS_EINT_CON_MASK << shift);
163 con |= trig_type << shift;
164 writel(con, d->virt_base + reg_con);
169 static int exynos_irq_request_resources(struct irq_data *irqd)
171 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
172 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
173 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
174 struct samsung_pin_bank_type *bank_type = bank->type;
175 struct samsung_pinctrl_drv_data *d = bank->drvdata;
176 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
177 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
183 ret = gpio_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
185 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n",
186 bank->name, irqd->hwirq);
190 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
191 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
192 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
194 spin_lock_irqsave(&bank->slock, flags);
196 con = readl(d->virt_base + reg_con);
197 con &= ~(mask << shift);
198 con |= EXYNOS_EINT_FUNC << shift;
199 writel(con, d->virt_base + reg_con);
201 spin_unlock_irqrestore(&bank->slock, flags);
203 exynos_irq_unmask(irqd);
208 static void exynos_irq_release_resources(struct irq_data *irqd)
210 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
211 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
212 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
213 struct samsung_pin_bank_type *bank_type = bank->type;
214 struct samsung_pinctrl_drv_data *d = bank->drvdata;
215 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
216 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
221 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
222 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
223 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
225 exynos_irq_mask(irqd);
227 spin_lock_irqsave(&bank->slock, flags);
229 con = readl(d->virt_base + reg_con);
230 con &= ~(mask << shift);
231 con |= FUNC_INPUT << shift;
232 writel(con, d->virt_base + reg_con);
234 spin_unlock_irqrestore(&bank->slock, flags);
236 gpio_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
240 * irq_chip for gpio interrupts.
242 static struct exynos_irq_chip exynos_gpio_irq_chip = {
244 .name = "exynos_gpio_irq_chip",
245 .irq_unmask = exynos_irq_unmask,
246 .irq_mask = exynos_irq_mask,
247 .irq_ack = exynos_irq_ack,
248 .irq_set_type = exynos_irq_set_type,
249 .irq_request_resources = exynos_irq_request_resources,
250 .irq_release_resources = exynos_irq_release_resources,
252 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
253 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
254 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
257 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
260 struct samsung_pin_bank *b = h->host_data;
262 irq_set_chip_data(virq, b);
263 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
265 set_irq_flags(virq, IRQF_VALID);
270 * irq domain callbacks for external gpio interrupt controller.
272 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
273 .map = exynos_gpio_irq_map,
274 .xlate = irq_domain_xlate_twocell,
277 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
279 struct samsung_pinctrl_drv_data *d = data;
280 struct samsung_pin_ctrl *ctrl = d->ctrl;
281 struct samsung_pin_bank *bank = ctrl->pin_banks;
282 unsigned int svc, group, pin, virq;
284 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
285 group = EXYNOS_SVC_GROUP(svc);
286 pin = svc & EXYNOS_SVC_NUM_MASK;
292 virq = irq_linear_revmap(bank->irq_domain, pin);
295 generic_handle_irq(virq);
299 struct exynos_eint_gpio_save {
306 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
307 * @d: driver data of samsung pinctrl driver.
309 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
311 struct samsung_pin_bank *bank;
312 struct device *dev = d->dev;
317 dev_err(dev, "irq number not available\n");
321 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
322 0, dev_name(dev), d);
324 dev_err(dev, "irq request failed\n");
328 bank = d->ctrl->pin_banks;
329 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
330 if (bank->eint_type != EINT_TYPE_GPIO)
332 bank->irq_domain = irq_domain_add_linear(bank->of_node,
333 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
334 if (!bank->irq_domain) {
335 dev_err(dev, "gpio irq domain add failed\n");
340 bank->soc_priv = devm_kzalloc(d->dev,
341 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
342 if (!bank->soc_priv) {
343 irq_domain_remove(bank->irq_domain);
352 for (--i, --bank; i >= 0; --i, --bank) {
353 if (bank->eint_type != EINT_TYPE_GPIO)
355 irq_domain_remove(bank->irq_domain);
361 static u32 exynos_eint_wake_mask = 0xffffffff;
363 u32 exynos_get_eint_wake_mask(void)
365 return exynos_eint_wake_mask;
368 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
370 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
371 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
373 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
376 exynos_eint_wake_mask |= bit;
378 exynos_eint_wake_mask &= ~bit;
384 * irq_chip for wakeup interrupts
386 static struct exynos_irq_chip exynos_wkup_irq_chip = {
388 .name = "exynos_wkup_irq_chip",
389 .irq_unmask = exynos_irq_unmask,
390 .irq_mask = exynos_irq_mask,
391 .irq_ack = exynos_irq_ack,
392 .irq_set_type = exynos_irq_set_type,
393 .irq_set_wake = exynos_wkup_irq_set_wake,
394 .irq_request_resources = exynos_irq_request_resources,
395 .irq_release_resources = exynos_irq_release_resources,
397 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
398 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
399 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
402 /* interrupt handler for wakeup interrupts 0..15 */
403 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
405 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
406 struct samsung_pin_bank *bank = eintd->bank;
407 struct irq_chip *chip = irq_get_chip(irq);
410 chained_irq_enter(chip, desc);
411 chip->irq_mask(&desc->irq_data);
414 chip->irq_ack(&desc->irq_data);
416 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
417 generic_handle_irq(eint_irq);
418 chip->irq_unmask(&desc->irq_data);
419 chained_irq_exit(chip, desc);
422 static inline void exynos_irq_demux_eint(unsigned long pend,
423 struct irq_domain *domain)
429 generic_handle_irq(irq_find_mapping(domain, irq));
434 /* interrupt handler for wakeup interrupt 16 */
435 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
437 struct irq_chip *chip = irq_get_chip(irq);
438 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
439 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
444 chained_irq_enter(chip, desc);
446 for (i = 0; i < eintd->nr_banks; ++i) {
447 struct samsung_pin_bank *b = eintd->banks[i];
448 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
450 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
452 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
455 chained_irq_exit(chip, desc);
458 static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
461 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
463 irq_set_chip_data(virq, h->host_data);
464 set_irq_flags(virq, IRQF_VALID);
469 * irq domain callbacks for external wakeup interrupt controller.
471 static const struct irq_domain_ops exynos_wkup_irqd_ops = {
472 .map = exynos_wkup_irq_map,
473 .xlate = irq_domain_xlate_twocell,
477 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
478 * @d: driver data of samsung pinctrl driver.
480 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
482 struct device *dev = d->dev;
483 struct device_node *wkup_np = NULL;
484 struct device_node *np;
485 struct samsung_pin_bank *bank;
486 struct exynos_weint_data *weint_data;
487 struct exynos_muxed_weint_data *muxed_data;
488 unsigned int muxed_banks = 0;
492 for_each_child_of_node(dev->of_node, np) {
493 if (of_match_node(exynos_wkup_irq_ids, np)) {
501 bank = d->ctrl->pin_banks;
502 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
503 if (bank->eint_type != EINT_TYPE_WKUP)
506 bank->irq_domain = irq_domain_add_linear(bank->of_node,
507 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
508 if (!bank->irq_domain) {
509 dev_err(dev, "wkup irq domain add failed\n");
513 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
514 bank->eint_type = EINT_TYPE_WKUP_MUX;
519 weint_data = devm_kzalloc(dev, bank->nr_pins
520 * sizeof(*weint_data), GFP_KERNEL);
522 dev_err(dev, "could not allocate memory for weint_data\n");
526 for (idx = 0; idx < bank->nr_pins; ++idx) {
527 irq = irq_of_parse_and_map(bank->of_node, idx);
529 dev_err(dev, "irq number for eint-%s-%d not found\n",
533 weint_data[idx].irq = idx;
534 weint_data[idx].bank = bank;
535 irq_set_handler_data(irq, &weint_data[idx]);
536 irq_set_chained_handler(irq, exynos_irq_eint0_15);
543 irq = irq_of_parse_and_map(wkup_np, 0);
545 dev_err(dev, "irq number for muxed EINTs not found\n");
549 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
550 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
552 dev_err(dev, "could not allocate memory for muxed_data\n");
556 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
557 irq_set_handler_data(irq, muxed_data);
559 bank = d->ctrl->pin_banks;
561 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
562 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
565 muxed_data->banks[idx++] = bank;
567 muxed_data->nr_banks = muxed_banks;
572 static void exynos_pinctrl_suspend_bank(
573 struct samsung_pinctrl_drv_data *drvdata,
574 struct samsung_pin_bank *bank)
576 struct exynos_eint_gpio_save *save = bank->soc_priv;
577 void __iomem *regs = drvdata->virt_base;
579 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
580 + bank->eint_offset);
581 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
582 + 2 * bank->eint_offset);
583 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
584 + 2 * bank->eint_offset + 4);
586 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
587 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
588 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
591 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
593 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
594 struct samsung_pin_bank *bank = ctrl->pin_banks;
597 for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
598 if (bank->eint_type == EINT_TYPE_GPIO)
599 exynos_pinctrl_suspend_bank(drvdata, bank);
602 static void exynos_pinctrl_resume_bank(
603 struct samsung_pinctrl_drv_data *drvdata,
604 struct samsung_pin_bank *bank)
606 struct exynos_eint_gpio_save *save = bank->soc_priv;
607 void __iomem *regs = drvdata->virt_base;
609 pr_debug("%s: con %#010x => %#010x\n", bank->name,
610 readl(regs + EXYNOS_GPIO_ECON_OFFSET
611 + bank->eint_offset), save->eint_con);
612 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
613 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
614 + 2 * bank->eint_offset), save->eint_fltcon0);
615 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
616 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
617 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
619 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
620 + bank->eint_offset);
621 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
622 + 2 * bank->eint_offset);
623 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
624 + 2 * bank->eint_offset + 4);
627 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
629 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
630 struct samsung_pin_bank *bank = ctrl->pin_banks;
633 for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
634 if (bank->eint_type == EINT_TYPE_GPIO)
635 exynos_pinctrl_resume_bank(drvdata, bank);
638 /* pin banks of s5pv210 pin-controller */
639 static struct samsung_pin_bank s5pv210_pin_bank[] = {
640 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
641 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
642 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
643 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
644 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
645 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
646 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
647 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
648 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
649 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
650 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
651 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
652 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
653 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
654 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
655 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
656 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
657 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
658 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
659 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
660 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
661 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
662 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
663 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
664 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
665 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
666 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
667 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
668 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
669 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
670 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
671 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
672 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
673 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
676 struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
678 /* pin-controller instance 0 data */
679 .pin_banks = s5pv210_pin_bank,
680 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
681 .eint_gpio_init = exynos_eint_gpio_init,
682 .eint_wkup_init = exynos_eint_wkup_init,
683 .suspend = exynos_pinctrl_suspend,
684 .resume = exynos_pinctrl_resume,
685 .label = "s5pv210-gpio-ctrl0",
689 /* pin banks of exynos3250 pin-controller 0 */
690 static struct samsung_pin_bank exynos3250_pin_banks0[] = {
691 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
692 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
693 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
694 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
695 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
696 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
697 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
700 /* pin banks of exynos3250 pin-controller 1 */
701 static struct samsung_pin_bank exynos3250_pin_banks1[] = {
702 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
703 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
704 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
705 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
706 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
707 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
708 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
709 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
710 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
711 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
712 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
713 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
714 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
715 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
716 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
717 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
721 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
722 * two gpio/pin-mux/pinconfig controllers.
724 struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
726 /* pin-controller instance 0 data */
727 .pin_banks = exynos3250_pin_banks0,
728 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
729 .eint_gpio_init = exynos_eint_gpio_init,
730 .suspend = exynos_pinctrl_suspend,
731 .resume = exynos_pinctrl_resume,
732 .label = "exynos3250-gpio-ctrl0",
734 /* pin-controller instance 1 data */
735 .pin_banks = exynos3250_pin_banks1,
736 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
737 .eint_gpio_init = exynos_eint_gpio_init,
738 .eint_wkup_init = exynos_eint_wkup_init,
739 .suspend = exynos_pinctrl_suspend,
740 .resume = exynos_pinctrl_resume,
741 .label = "exynos3250-gpio-ctrl1",
745 /* pin banks of exynos4210 pin-controller 0 */
746 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
747 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
748 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
749 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
750 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
751 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
752 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
753 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
754 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
755 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
756 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
757 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
758 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
759 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
760 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
761 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
762 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
765 /* pin banks of exynos4210 pin-controller 1 */
766 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
767 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
768 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
769 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
770 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
771 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
772 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
773 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
774 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
775 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
776 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
777 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
778 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
779 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
780 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
781 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
782 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
783 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
784 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
785 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
786 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
789 /* pin banks of exynos4210 pin-controller 2 */
790 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
791 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
795 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
796 * three gpio/pin-mux/pinconfig controllers.
798 struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
800 /* pin-controller instance 0 data */
801 .pin_banks = exynos4210_pin_banks0,
802 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
803 .eint_gpio_init = exynos_eint_gpio_init,
804 .suspend = exynos_pinctrl_suspend,
805 .resume = exynos_pinctrl_resume,
806 .label = "exynos4210-gpio-ctrl0",
808 /* pin-controller instance 1 data */
809 .pin_banks = exynos4210_pin_banks1,
810 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
811 .eint_gpio_init = exynos_eint_gpio_init,
812 .eint_wkup_init = exynos_eint_wkup_init,
813 .suspend = exynos_pinctrl_suspend,
814 .resume = exynos_pinctrl_resume,
815 .label = "exynos4210-gpio-ctrl1",
817 /* pin-controller instance 2 data */
818 .pin_banks = exynos4210_pin_banks2,
819 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
820 .label = "exynos4210-gpio-ctrl2",
824 /* pin banks of exynos4x12 pin-controller 0 */
825 static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
826 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
827 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
828 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
829 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
830 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
831 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
832 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
833 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
834 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
835 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
836 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
837 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
838 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
841 /* pin banks of exynos4x12 pin-controller 1 */
842 static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
843 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
844 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
845 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
846 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
847 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
848 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
849 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
850 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
851 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
852 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
853 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
854 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
855 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
856 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
857 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
858 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
859 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
860 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
861 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
862 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
863 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
864 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
865 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
868 /* pin banks of exynos4x12 pin-controller 2 */
869 static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
870 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
873 /* pin banks of exynos4x12 pin-controller 3 */
874 static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
875 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
876 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
877 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
878 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
879 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
883 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
884 * four gpio/pin-mux/pinconfig controllers.
886 struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
888 /* pin-controller instance 0 data */
889 .pin_banks = exynos4x12_pin_banks0,
890 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
891 .eint_gpio_init = exynos_eint_gpio_init,
892 .suspend = exynos_pinctrl_suspend,
893 .resume = exynos_pinctrl_resume,
894 .label = "exynos4x12-gpio-ctrl0",
896 /* pin-controller instance 1 data */
897 .pin_banks = exynos4x12_pin_banks1,
898 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
899 .eint_gpio_init = exynos_eint_gpio_init,
900 .eint_wkup_init = exynos_eint_wkup_init,
901 .suspend = exynos_pinctrl_suspend,
902 .resume = exynos_pinctrl_resume,
903 .label = "exynos4x12-gpio-ctrl1",
905 /* pin-controller instance 2 data */
906 .pin_banks = exynos4x12_pin_banks2,
907 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
908 .eint_gpio_init = exynos_eint_gpio_init,
909 .suspend = exynos_pinctrl_suspend,
910 .resume = exynos_pinctrl_resume,
911 .label = "exynos4x12-gpio-ctrl2",
913 /* pin-controller instance 3 data */
914 .pin_banks = exynos4x12_pin_banks3,
915 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
916 .eint_gpio_init = exynos_eint_gpio_init,
917 .suspend = exynos_pinctrl_suspend,
918 .resume = exynos_pinctrl_resume,
919 .label = "exynos4x12-gpio-ctrl3",
923 /* pin banks of exynos5250 pin-controller 0 */
924 static struct samsung_pin_bank exynos5250_pin_banks0[] = {
925 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
926 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
927 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
928 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
929 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
930 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
931 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
932 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
933 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
934 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
935 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
936 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
937 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
938 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
939 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
940 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
941 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
942 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
943 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
944 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
945 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
946 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
947 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
948 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
949 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
952 /* pin banks of exynos5250 pin-controller 1 */
953 static struct samsung_pin_bank exynos5250_pin_banks1[] = {
954 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
955 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
956 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
957 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
958 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
959 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
960 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
961 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
962 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
965 /* pin banks of exynos5250 pin-controller 2 */
966 static struct samsung_pin_bank exynos5250_pin_banks2[] = {
967 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
968 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
969 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
970 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
971 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
974 /* pin banks of exynos5250 pin-controller 3 */
975 static struct samsung_pin_bank exynos5250_pin_banks3[] = {
976 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
980 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
981 * four gpio/pin-mux/pinconfig controllers.
983 struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
985 /* pin-controller instance 0 data */
986 .pin_banks = exynos5250_pin_banks0,
987 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
988 .eint_gpio_init = exynos_eint_gpio_init,
989 .eint_wkup_init = exynos_eint_wkup_init,
990 .suspend = exynos_pinctrl_suspend,
991 .resume = exynos_pinctrl_resume,
992 .label = "exynos5250-gpio-ctrl0",
994 /* pin-controller instance 1 data */
995 .pin_banks = exynos5250_pin_banks1,
996 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
997 .eint_gpio_init = exynos_eint_gpio_init,
998 .suspend = exynos_pinctrl_suspend,
999 .resume = exynos_pinctrl_resume,
1000 .label = "exynos5250-gpio-ctrl1",
1002 /* pin-controller instance 2 data */
1003 .pin_banks = exynos5250_pin_banks2,
1004 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
1005 .eint_gpio_init = exynos_eint_gpio_init,
1006 .suspend = exynos_pinctrl_suspend,
1007 .resume = exynos_pinctrl_resume,
1008 .label = "exynos5250-gpio-ctrl2",
1010 /* pin-controller instance 3 data */
1011 .pin_banks = exynos5250_pin_banks3,
1012 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
1013 .eint_gpio_init = exynos_eint_gpio_init,
1014 .suspend = exynos_pinctrl_suspend,
1015 .resume = exynos_pinctrl_resume,
1016 .label = "exynos5250-gpio-ctrl3",
1020 /* pin banks of exynos5260 pin-controller 0 */
1021 static struct samsung_pin_bank exynos5260_pin_banks0[] = {
1022 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1023 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1024 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1025 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1026 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1027 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1028 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1029 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1030 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1031 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1032 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1033 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1034 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1035 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1036 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1037 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1038 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1039 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1040 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1041 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1042 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1045 /* pin banks of exynos5260 pin-controller 1 */
1046 static struct samsung_pin_bank exynos5260_pin_banks1[] = {
1047 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1048 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1049 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1050 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1051 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1054 /* pin banks of exynos5260 pin-controller 2 */
1055 static struct samsung_pin_bank exynos5260_pin_banks2[] = {
1056 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1057 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1061 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1062 * three gpio/pin-mux/pinconfig controllers.
1064 struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1066 /* pin-controller instance 0 data */
1067 .pin_banks = exynos5260_pin_banks0,
1068 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1069 .eint_gpio_init = exynos_eint_gpio_init,
1070 .eint_wkup_init = exynos_eint_wkup_init,
1071 .label = "exynos5260-gpio-ctrl0",
1073 /* pin-controller instance 1 data */
1074 .pin_banks = exynos5260_pin_banks1,
1075 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1076 .eint_gpio_init = exynos_eint_gpio_init,
1077 .label = "exynos5260-gpio-ctrl1",
1079 /* pin-controller instance 2 data */
1080 .pin_banks = exynos5260_pin_banks2,
1081 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1082 .eint_gpio_init = exynos_eint_gpio_init,
1083 .label = "exynos5260-gpio-ctrl2",
1087 /* pin banks of exynos5420 pin-controller 0 */
1088 static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1089 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1090 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1091 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1092 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1093 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1096 /* pin banks of exynos5420 pin-controller 1 */
1097 static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1098 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1099 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1100 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1101 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1102 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1103 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1104 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1105 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1106 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1107 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1108 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1109 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1110 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1113 /* pin banks of exynos5420 pin-controller 2 */
1114 static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1115 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1116 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1117 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1118 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1119 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1120 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1121 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1122 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1125 /* pin banks of exynos5420 pin-controller 3 */
1126 static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1127 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1128 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1129 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1130 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1131 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1132 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1133 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1134 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1135 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1138 /* pin banks of exynos5420 pin-controller 4 */
1139 static struct samsung_pin_bank exynos5420_pin_banks4[] = {
1140 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1144 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1145 * four gpio/pin-mux/pinconfig controllers.
1147 struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1149 /* pin-controller instance 0 data */
1150 .pin_banks = exynos5420_pin_banks0,
1151 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1152 .eint_gpio_init = exynos_eint_gpio_init,
1153 .eint_wkup_init = exynos_eint_wkup_init,
1154 .label = "exynos5420-gpio-ctrl0",
1156 /* pin-controller instance 1 data */
1157 .pin_banks = exynos5420_pin_banks1,
1158 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1159 .eint_gpio_init = exynos_eint_gpio_init,
1160 .label = "exynos5420-gpio-ctrl1",
1162 /* pin-controller instance 2 data */
1163 .pin_banks = exynos5420_pin_banks2,
1164 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1165 .eint_gpio_init = exynos_eint_gpio_init,
1166 .label = "exynos5420-gpio-ctrl2",
1168 /* pin-controller instance 3 data */
1169 .pin_banks = exynos5420_pin_banks3,
1170 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1171 .eint_gpio_init = exynos_eint_gpio_init,
1172 .label = "exynos5420-gpio-ctrl3",
1174 /* pin-controller instance 4 data */
1175 .pin_banks = exynos5420_pin_banks4,
1176 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1177 .eint_gpio_init = exynos_eint_gpio_init,
1178 .label = "exynos5420-gpio-ctrl4",