2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
28 #include "../pinctrl-utils.h"
30 #define PMIC_GPIO_ADDRESS_RANGE 0x100
32 /* type and subtype registers base address offsets */
33 #define PMIC_GPIO_REG_TYPE 0x4
34 #define PMIC_GPIO_REG_SUBTYPE 0x5
36 /* GPIO peripheral type and subtype out_values */
37 #define PMIC_GPIO_TYPE 0x10
38 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
39 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
40 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
41 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_MPP_REG_RT_STS 0x10
44 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
46 /* control register base address offsets */
47 #define PMIC_GPIO_REG_MODE_CTL 0x40
48 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
49 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
50 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
51 #define PMIC_GPIO_REG_EN_CTL 0x46
53 /* PMIC_GPIO_REG_MODE_CTL */
54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
58 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
60 /* PMIC_GPIO_REG_DIG_VIN_CTL */
61 #define PMIC_GPIO_REG_VIN_SHIFT 0
62 #define PMIC_GPIO_REG_VIN_MASK 0x7
64 /* PMIC_GPIO_REG_DIG_PULL_CTL */
65 #define PMIC_GPIO_REG_PULL_SHIFT 0
66 #define PMIC_GPIO_REG_PULL_MASK 0x7
68 #define PMIC_GPIO_PULL_DOWN 4
69 #define PMIC_GPIO_PULL_DISABLE 5
71 /* PMIC_GPIO_REG_DIG_OUT_CTL */
72 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
73 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
74 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
75 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
78 * Output type - indicates pin should be configured as push-pull,
79 * open drain or open source.
81 #define PMIC_GPIO_OUT_BUF_CMOS 0
82 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
85 /* PMIC_GPIO_REG_EN_CTL */
86 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
88 #define PMIC_GPIO_PHYSICAL_OFFSET 1
90 /* Qualcomm specific pin configurations */
91 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
92 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
95 * struct pmic_gpio_pad - keep current GPIO settings
96 * @base: Address base in SPMI device.
97 * @irq: IRQ number which this GPIO generate.
98 * @is_enabled: Set to false when GPIO should be put in high Z state.
99 * @out_value: Cached pin output value
100 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
101 * open-drain or open-source mode.
102 * @output_enabled: Set to true if GPIO output logic is enabled.
103 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
104 * @num_sources: Number of power-sources supported by this GPIO.
105 * @power_source: Current power-source used.
106 * @buffer_type: Push-pull, open-drain or open-source.
107 * @pullup: Constant current which flow trough GPIO output buffer.
108 * @strength: No, Low, Medium, High
109 * @function: See pmic_gpio_functions[]
111 struct pmic_gpio_pad {
119 unsigned int num_sources;
120 unsigned int power_source;
121 unsigned int buffer_type;
123 unsigned int strength;
124 unsigned int function;
127 struct pmic_gpio_state {
130 struct pinctrl_dev *ctrl;
131 struct gpio_chip chip;
134 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
135 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
136 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
139 #ifdef CONFIG_DEBUG_FS
140 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
141 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
142 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
146 static const char *const pmic_gpio_groups[] = {
147 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
148 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
149 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
150 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
151 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
154 static const char *const pmic_gpio_functions[] = {
155 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
156 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
157 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
158 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
161 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
163 return container_of(chip, struct pmic_gpio_state, chip);
166 static int pmic_gpio_read(struct pmic_gpio_state *state,
167 struct pmic_gpio_pad *pad, unsigned int addr)
172 ret = regmap_read(state->map, pad->base + addr, &val);
174 dev_err(state->dev, "read 0x%x failed\n", addr);
181 static int pmic_gpio_write(struct pmic_gpio_state *state,
182 struct pmic_gpio_pad *pad, unsigned int addr,
187 ret = regmap_write(state->map, pad->base + addr, val);
189 dev_err(state->dev, "write 0x%x failed\n", addr);
194 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
196 /* Every PIN is a group */
197 return pctldev->desc->npins;
200 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
203 return pctldev->desc->pins[pin].name;
206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
207 const unsigned **pins, unsigned *num_pins)
209 *pins = &pctldev->desc->pins[pin].number;
214 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
215 .get_groups_count = pmic_gpio_get_groups_count,
216 .get_group_name = pmic_gpio_get_group_name,
217 .get_group_pins = pmic_gpio_get_group_pins,
218 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
219 .dt_free_map = pinctrl_utils_dt_free_map,
222 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
224 return ARRAY_SIZE(pmic_gpio_functions);
227 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
230 return pmic_gpio_functions[function];
233 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
235 const char *const **groups,
236 unsigned *const num_qgroups)
238 *groups = pmic_gpio_groups;
239 *num_qgroups = pctldev->desc->npins;
243 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
246 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
247 struct pmic_gpio_pad *pad;
251 pad = pctldev->desc->pins[pin].drv_data;
253 pad->function = function;
256 if (pad->output_enabled) {
257 if (pad->input_enabled)
263 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
264 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
266 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
270 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
272 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
275 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
276 .get_functions_count = pmic_gpio_get_functions_count,
277 .get_function_name = pmic_gpio_get_function_name,
278 .get_function_groups = pmic_gpio_get_function_groups,
279 .set_mux = pmic_gpio_set_mux,
282 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
283 unsigned int pin, unsigned long *config)
285 unsigned param = pinconf_to_config_param(*config);
286 struct pmic_gpio_pad *pad;
289 pad = pctldev->desc->pins[pin].drv_data;
292 case PIN_CONFIG_DRIVE_PUSH_PULL:
293 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
295 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
296 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
298 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
299 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
301 case PIN_CONFIG_BIAS_PULL_DOWN:
302 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
304 case PIN_CONFIG_BIAS_DISABLE:
305 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
307 case PIN_CONFIG_BIAS_PULL_UP:
308 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
310 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
311 arg = !pad->is_enabled;
313 case PIN_CONFIG_POWER_SOURCE:
314 arg = pad->power_source;
316 case PIN_CONFIG_INPUT_ENABLE:
317 arg = pad->input_enabled;
319 case PIN_CONFIG_OUTPUT:
320 arg = pad->out_value;
322 case PMIC_GPIO_CONF_PULL_UP:
325 case PMIC_GPIO_CONF_STRENGTH:
332 *config = pinconf_to_config_packed(param, arg);
336 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
337 unsigned long *configs, unsigned nconfs)
339 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
340 struct pmic_gpio_pad *pad;
345 pad = pctldev->desc->pins[pin].drv_data;
347 for (i = 0; i < nconfs; i++) {
348 param = pinconf_to_config_param(configs[i]);
349 arg = pinconf_to_config_argument(configs[i]);
352 case PIN_CONFIG_DRIVE_PUSH_PULL:
353 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
355 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
356 if (!pad->have_buffer)
358 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
360 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
361 if (!pad->have_buffer)
363 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
365 case PIN_CONFIG_BIAS_DISABLE:
366 pad->pullup = PMIC_GPIO_PULL_DISABLE;
368 case PIN_CONFIG_BIAS_PULL_UP:
369 pad->pullup = PMIC_GPIO_PULL_UP_30;
371 case PIN_CONFIG_BIAS_PULL_DOWN:
373 pad->pullup = PMIC_GPIO_PULL_DOWN;
375 pad->pullup = PMIC_GPIO_PULL_DISABLE;
377 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
378 pad->is_enabled = false;
380 case PIN_CONFIG_POWER_SOURCE:
381 if (arg > pad->num_sources)
383 pad->power_source = arg;
385 case PIN_CONFIG_INPUT_ENABLE:
386 pad->input_enabled = arg ? true : false;
388 case PIN_CONFIG_OUTPUT:
389 pad->output_enabled = true;
390 pad->out_value = arg;
392 case PMIC_GPIO_CONF_PULL_UP:
393 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
397 case PMIC_GPIO_CONF_STRENGTH:
398 if (arg > PMIC_GPIO_STRENGTH_LOW)
407 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
409 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
413 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
415 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
419 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
420 val = pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
422 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
427 if (pad->output_enabled) {
428 if (pad->input_enabled)
434 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
435 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
436 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
438 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
441 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
442 struct seq_file *s, unsigned pin)
444 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
445 struct pmic_gpio_pad *pad;
448 static const char *const biases[] = {
449 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
450 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
452 static const char *const buffer_types[] = {
453 "push-pull", "open-drain", "open-source"
455 static const char *const strengths[] = {
456 "no", "high", "medium", "low"
459 pad = pctldev->desc->pins[pin].drv_data;
461 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
463 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
465 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
469 if (!pad->input_enabled) {
470 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
472 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
473 pad->out_value = ret;
477 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
478 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
479 seq_printf(s, " vin-%d", pad->power_source);
480 seq_printf(s, " %-27s", biases[pad->pullup]);
481 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
482 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
483 seq_printf(s, " %-7s", strengths[pad->strength]);
487 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
489 .pin_config_group_get = pmic_gpio_config_get,
490 .pin_config_group_set = pmic_gpio_config_set,
491 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
494 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
496 struct pmic_gpio_state *state = to_gpio_state(chip);
497 unsigned long config;
499 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
501 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
504 static int pmic_gpio_direction_output(struct gpio_chip *chip,
505 unsigned pin, int val)
507 struct pmic_gpio_state *state = to_gpio_state(chip);
508 unsigned long config;
510 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
512 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
515 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
517 struct pmic_gpio_state *state = to_gpio_state(chip);
518 struct pmic_gpio_pad *pad;
521 pad = state->ctrl->desc->pins[pin].drv_data;
523 if (!pad->is_enabled)
526 if (pad->input_enabled) {
527 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
531 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
534 return pad->out_value;
537 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
539 struct pmic_gpio_state *state = to_gpio_state(chip);
540 unsigned long config;
542 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
544 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
547 static int pmic_gpio_request(struct gpio_chip *chip, unsigned base)
549 return pinctrl_request_gpio(chip->base + base);
552 static void pmic_gpio_free(struct gpio_chip *chip, unsigned base)
554 pinctrl_free_gpio(chip->base + base);
557 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
558 const struct of_phandle_args *gpio_desc,
561 if (chip->of_gpio_n_cells < 2)
565 *flags = gpio_desc->args[1];
567 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
570 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
572 struct pmic_gpio_state *state = to_gpio_state(chip);
573 struct pmic_gpio_pad *pad;
575 pad = state->ctrl->desc->pins[pin].drv_data;
580 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
582 struct pmic_gpio_state *state = to_gpio_state(chip);
585 for (i = 0; i < chip->ngpio; i++) {
586 pmic_gpio_config_dbg_show(state->ctrl, s, i);
591 static const struct gpio_chip pmic_gpio_gpio_template = {
592 .direction_input = pmic_gpio_direction_input,
593 .direction_output = pmic_gpio_direction_output,
594 .get = pmic_gpio_get,
595 .set = pmic_gpio_set,
596 .request = pmic_gpio_request,
597 .free = pmic_gpio_free,
598 .of_xlate = pmic_gpio_of_xlate,
599 .to_irq = pmic_gpio_to_irq,
600 .dbg_show = pmic_gpio_dbg_show,
603 static int pmic_gpio_populate(struct pmic_gpio_state *state,
604 struct pmic_gpio_pad *pad)
606 int type, subtype, val, dir;
608 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
612 if (type != PMIC_GPIO_TYPE) {
613 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
618 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
623 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
624 pad->have_buffer = true;
625 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
626 pad->num_sources = 4;
628 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
629 pad->have_buffer = true;
630 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
631 pad->num_sources = 8;
634 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
638 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
642 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
644 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
645 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
648 pad->input_enabled = true;
649 pad->output_enabled = false;
652 pad->input_enabled = false;
653 pad->output_enabled = true;
656 pad->input_enabled = true;
657 pad->output_enabled = true;
660 dev_err(state->dev, "unknown GPIO direction\n");
664 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
665 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
667 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
671 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
672 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
674 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
678 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
679 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
681 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
685 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
686 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
688 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
689 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
691 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
692 pad->is_enabled = true;
696 static int pmic_gpio_probe(struct platform_device *pdev)
698 struct device *dev = &pdev->dev;
699 struct pinctrl_pin_desc *pindesc;
700 struct pinctrl_desc *pctrldesc;
701 struct pmic_gpio_pad *pad, *pads;
702 struct pmic_gpio_state *state;
706 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
708 dev_err(dev, "missing base address and/or range");
712 npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
717 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
719 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
723 platform_set_drvdata(pdev, state);
725 state->dev = &pdev->dev;
726 state->map = dev_get_regmap(dev->parent, NULL);
728 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
732 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
736 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
740 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
741 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
742 pctrldesc->confops = &pmic_gpio_pinconf_ops;
743 pctrldesc->owner = THIS_MODULE;
744 pctrldesc->name = dev_name(dev);
745 pctrldesc->pins = pindesc;
746 pctrldesc->npins = npins;
747 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
748 pctrldesc->custom_params = pmic_gpio_bindings;
749 #ifdef CONFIG_DEBUG_FS
750 pctrldesc->custom_conf_items = pmic_conf_items;
753 for (i = 0; i < npins; i++, pindesc++) {
755 pindesc->drv_data = pad;
757 pindesc->name = pmic_gpio_groups[i];
759 pad->irq = platform_get_irq(pdev, i);
763 pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
765 ret = pmic_gpio_populate(state, pad);
770 state->chip = pmic_gpio_gpio_template;
771 state->chip.dev = dev;
772 state->chip.base = -1;
773 state->chip.ngpio = npins;
774 state->chip.label = dev_name(dev);
775 state->chip.of_gpio_n_cells = 2;
776 state->chip.can_sleep = false;
778 state->ctrl = pinctrl_register(pctrldesc, dev, state);
782 ret = gpiochip_add(&state->chip);
784 dev_err(state->dev, "can't add gpio chip\n");
788 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
790 dev_err(dev, "failed to add pin range\n");
797 gpiochip_remove(&state->chip);
799 pinctrl_unregister(state->ctrl);
803 static int pmic_gpio_remove(struct platform_device *pdev)
805 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
807 gpiochip_remove(&state->chip);
808 pinctrl_unregister(state->ctrl);
812 static const struct of_device_id pmic_gpio_of_match[] = {
813 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
814 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
815 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
819 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
821 static struct platform_driver pmic_gpio_driver = {
823 .name = "qcom-spmi-gpio",
824 .of_match_table = pmic_gpio_of_match,
826 .probe = pmic_gpio_probe,
827 .remove = pmic_gpio_remove,
830 module_platform_driver(pmic_gpio_driver);
832 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
833 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
834 MODULE_ALIAS("platform:qcom-spmi-gpio");
835 MODULE_LICENSE("GPL v2");