2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
72 * Encode variants of iomux registers into a type variable
74 #define IOMUX_GPIO_ONLY BIT(0)
75 #define IOMUX_WIDTH_4BIT BIT(1)
76 #define IOMUX_SOURCE_PMU BIT(2)
77 #define IOMUX_UNROUTED BIT(3)
80 * @type: iomux variant using IOMUX_* constants
81 * @offset: if initialized to -1 it will be autocalculated, by specifying
82 * an initial offset value the relevant source offset can be reset
83 * to a new value for autocalculating the following iomux registers.
85 struct rockchip_iomux {
91 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
93 enum rockchip_pin_drv_type {
94 DRV_TYPE_IO_DEFAULT = 0,
95 DRV_TYPE_IO_1V8_OR_3V0,
97 DRV_TYPE_IO_1V8_3V0_AUTO,
99 DRV_TYPE_IO_WIDE_LEVEL,
100 DRV_TYPE_IO_NARROW_LEVEL,
105 * enum type of pin extra drive alignment.
107 enum rockchip_pin_extra_drv_type {
108 DRV_TYPE_EXTRA_DEFAULT = 0,
109 DRV_TYPE_EXTRA_SAME_OFFSET,
110 DRV_TYPE_EXTRA_SAME_BITS
114 * @drv_type: drive strength variant using rockchip_pin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
121 struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
127 * @reg_base: register base of the gpio bank
128 * @reg_pull: optional separate register for additional pull settings
129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
136 * @iomux: array describing the 4 iomux sources of the bank
137 * @drv: array describing the 4 drive strength sources of the bank
138 * @valid: are all necessary informations present
139 * @of_node: dt node of this bank
140 * @drvdata: common pinctrl basedata
141 * @domain: irqdomain of the gpio bank
142 * @gpio_chip: gpiolib chip
143 * @grange: gpio range
144 * @slock: spinlock for the gpio bank
146 struct rockchip_pin_bank {
147 void __iomem *reg_base;
148 struct regmap *regmap_pull;
156 struct rockchip_iomux iomux[4];
157 struct rockchip_drv drv[4];
159 struct device_node *of_node;
160 struct rockchip_pinctrl *drvdata;
161 struct irq_domain *domain;
162 struct gpio_chip gpio_chip;
163 struct pinctrl_gpio_range grange;
165 u32 toggle_edge_mode;
168 #define PIN_BANK(id, pins, label) \
181 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
187 { .type = iom0, .offset = -1 }, \
188 { .type = iom1, .offset = -1 }, \
189 { .type = iom2, .offset = -1 }, \
190 { .type = iom3, .offset = -1 }, \
194 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
206 { .drv_type = type0, .offset = -1 }, \
207 { .drv_type = type1, .offset = -1 }, \
208 { .drv_type = type2, .offset = -1 }, \
209 { .drv_type = type3, .offset = -1 }, \
213 #define PIN_BANK_IOMUX_DRV_FLAGS(id, pins, label, iom0, iom1, iom2, \
214 iom3, drv0, drv1, drv2, drv3) \
220 { .type = iom0, .offset = -1 }, \
221 { .type = iom1, .offset = -1 }, \
222 { .type = iom2, .offset = -1 }, \
223 { .type = iom3, .offset = -1 }, \
226 { .drv_type = drv0, .offset = -1 }, \
227 { .drv_type = drv1, .offset = -1 }, \
228 { .drv_type = drv2, .offset = -1 }, \
229 { .drv_type = drv3, .offset = -1 }, \
233 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \
234 iom1, iom2, iom3, offset0, \
235 offset1, offset2, offset3, \
236 drv0, drv1, drv2, drv3) \
242 { .type = iom0, .offset = offset0 }, \
243 { .type = iom1, .offset = offset1 }, \
244 { .type = iom2, .offset = offset2 }, \
245 { .type = iom3, .offset = offset3 }, \
248 { .drv_type = drv0, .offset = -1 }, \
249 { .drv_type = drv1, .offset = -1 }, \
250 { .drv_type = drv2, .offset = -1 }, \
251 { .drv_type = drv3, .offset = -1 }, \
255 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(id, pins, label, iom0, \
256 iom1, iom2, iom3, drv0, \
257 drv1, drv2, drv3, offset0,\
258 offset1, offset2, offset3)\
264 { .type = iom0, .offset = -1 }, \
265 { .type = iom1, .offset = -1 }, \
266 { .type = iom2, .offset = -1 }, \
267 { .type = iom3, .offset = -1 }, \
270 { .drv_type = drv0, .offset = offset0 }, \
271 { .drv_type = drv1, .offset = offset1 }, \
272 { .drv_type = drv2, .offset = offset2 }, \
273 { .drv_type = drv3, .offset = offset3 }, \
279 struct rockchip_pin_ctrl {
280 struct rockchip_pin_bank *pin_banks;
284 enum rockchip_pinctrl_type type;
290 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
291 int pin_num, struct regmap **regmap,
293 enum rockchip_pin_drv_type (*drv_calc_reg)(
294 struct rockchip_pin_bank *bank,
295 int pin_num, struct regmap **regmap,
297 enum rockchip_pin_extra_drv_type (*drv_calc_extra_reg)(
298 struct rockchip_pin_bank *bank,
299 int pin_num, struct regmap **regmap,
303 struct rockchip_pin_config {
305 unsigned long *configs;
306 unsigned int nconfigs;
310 * struct rockchip_pin_group: represent group of pins of a pinmux function.
311 * @name: name of the pin group, used to lookup the group.
312 * @pins: the pins included in this group.
313 * @npins: number of pins included in this group.
314 * @func: the mux function number to be programmed when selected.
315 * @configs: the config values to be set for each pin
316 * @nconfigs: number of configs for each pin
318 struct rockchip_pin_group {
322 struct rockchip_pin_config *data;
326 * struct rockchip_pmx_func: represent a pin function.
327 * @name: name of the pin function, used to lookup the function.
328 * @groups: one or more names of pin groups that provide this function.
329 * @num_groups: number of groups included in @groups.
331 struct rockchip_pmx_func {
337 struct rockchip_pinctrl {
338 struct regmap *regmap_base;
340 struct regmap *regmap_pull;
341 struct regmap *regmap_pmu;
343 struct rockchip_pin_ctrl *ctrl;
344 struct pinctrl_desc pctl;
345 struct pinctrl_dev *pctl_dev;
346 struct rockchip_pin_group *groups;
347 unsigned int ngroups;
348 struct rockchip_pmx_func *functions;
349 unsigned int nfunctions;
352 static struct regmap_config rockchip_regmap_config = {
358 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
360 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
363 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
364 const struct rockchip_pinctrl *info,
369 for (i = 0; i < info->ngroups; i++) {
370 if (!strcmp(info->groups[i].name, name))
371 return &info->groups[i];
378 * given a pin number that is local to a pin controller, find out the pin bank
379 * and the register base of the pin bank.
381 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
384 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
386 while (pin >= (b->pin_base + b->nr_pins))
392 static struct rockchip_pin_bank *bank_num_to_bank(
393 struct rockchip_pinctrl *info,
396 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
399 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
400 if (b->bank_num == num)
404 return ERR_PTR(-EINVAL);
408 * Pinctrl_ops handling
411 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
413 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
415 return info->ngroups;
418 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
421 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
423 return info->groups[selector].name;
426 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
427 unsigned selector, const unsigned **pins,
430 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
432 if (selector >= info->ngroups)
435 *pins = info->groups[selector].pins;
436 *npins = info->groups[selector].npins;
441 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
442 struct device_node *np,
443 struct pinctrl_map **map, unsigned *num_maps)
445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
446 const struct rockchip_pin_group *grp;
447 struct pinctrl_map *new_map;
448 struct device_node *parent;
453 * first find the group of this node and check if we need to create
454 * config maps for pins
456 grp = pinctrl_name_to_group(info, np->name);
458 dev_err(info->dev, "unable to find group for node %s\n",
463 map_num += grp->npins;
464 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
473 parent = of_get_parent(np);
475 devm_kfree(pctldev->dev, new_map);
478 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
479 new_map[0].data.mux.function = parent->name;
480 new_map[0].data.mux.group = np->name;
483 /* create config map */
485 for (i = 0; i < grp->npins; i++) {
486 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
487 new_map[i].data.configs.group_or_pin =
488 pin_get_name(pctldev, grp->pins[i]);
489 new_map[i].data.configs.configs = grp->data[i].configs;
490 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
493 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
494 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
499 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
500 struct pinctrl_map *map, unsigned num_maps)
504 static const struct pinctrl_ops rockchip_pctrl_ops = {
505 .get_groups_count = rockchip_get_groups_count,
506 .get_group_name = rockchip_get_group_name,
507 .get_group_pins = rockchip_get_group_pins,
508 .dt_node_to_map = rockchip_dt_node_to_map,
509 .dt_free_map = rockchip_dt_free_map,
516 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
518 struct rockchip_pinctrl *info = bank->drvdata;
519 int iomux_num = (pin / 8);
520 struct regmap *regmap;
528 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
529 dev_err(info->dev, "pin %d is unrouted\n", pin);
533 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
536 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
537 ? info->regmap_pmu : info->regmap_base;
539 /* get basic quadrupel of mux registers and the correct reg inside */
540 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
541 reg = bank->iomux[iomux_num].offset;
542 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
550 ret = regmap_read(regmap, reg, &val);
554 return ((val >> bit) & mask);
558 * Set a new mux function for a pin.
560 * The register is divided into the upper and lower 16 bit. When changing
561 * a value, the previous register value is not read and changed. Instead
562 * it seems the changed bits are marked in the upper 16 bit, while the
563 * changed value gets set in the same offset in the lower 16 bit.
564 * All pin settings seem to be 2 bit wide in both the upper and lower
566 * @bank: pin bank to change
567 * @pin: pin to change
568 * @mux: new mux function to set
570 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
572 struct rockchip_pinctrl *info = bank->drvdata;
573 int iomux_num = (pin / 8);
574 struct regmap *regmap;
583 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
584 dev_err(info->dev, "pin %d is unrouted\n", pin);
588 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
589 if (mux != RK_FUNC_GPIO) {
591 "pin %d only supports a gpio mux\n", pin);
598 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
599 bank->bank_num, pin, mux);
601 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
602 ? info->regmap_pmu : info->regmap_base;
604 /* get basic quadrupel of mux registers and the correct reg inside */
605 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
606 reg = bank->iomux[iomux_num].offset;
607 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
615 spin_lock_irqsave(&bank->slock, flags);
617 data = (mask << (bit + 16));
618 rmask = data | (data >> 16);
619 data |= (mux & mask) << bit;
620 ret = regmap_update_bits(regmap, reg, rmask, data);
622 spin_unlock_irqrestore(&bank->slock, flags);
627 #define RK2928_PULL_OFFSET 0x118
628 #define RK2928_PULL_PINS_PER_REG 16
629 #define RK2928_PULL_BANK_STRIDE 8
631 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
632 int pin_num, struct regmap **regmap,
635 struct rockchip_pinctrl *info = bank->drvdata;
637 *regmap = info->regmap_base;
638 *reg = RK2928_PULL_OFFSET;
639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
640 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
642 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
645 #define RK3188_PULL_OFFSET 0x164
646 #define RK3188_PULL_BITS_PER_PIN 2
647 #define RK3188_PULL_PINS_PER_REG 8
648 #define RK3188_PULL_BANK_STRIDE 16
649 #define RK3188_PULL_PMU_OFFSET 0x64
651 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
652 int pin_num, struct regmap **regmap,
655 struct rockchip_pinctrl *info = bank->drvdata;
657 /* The first 12 pins of the first bank are located elsewhere */
658 if (bank->bank_num == 0 && pin_num < 12) {
659 *regmap = info->regmap_pmu ? info->regmap_pmu
661 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
662 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
663 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
664 *bit *= RK3188_PULL_BITS_PER_PIN;
666 *regmap = info->regmap_pull ? info->regmap_pull
668 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
670 /* correct the offset, as it is the 2nd pull register */
672 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
673 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
676 * The bits in these registers have an inverse ordering
677 * with the lowest pin being in bits 15:14 and the highest
680 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
681 *bit *= RK3188_PULL_BITS_PER_PIN;
685 #define RK3288_PULL_OFFSET 0x140
686 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
687 int pin_num, struct regmap **regmap,
690 struct rockchip_pinctrl *info = bank->drvdata;
692 /* The first 24 pins of the first bank are located in PMU */
693 if (bank->bank_num == 0) {
694 *regmap = info->regmap_pmu;
695 *reg = RK3188_PULL_PMU_OFFSET;
697 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
698 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
699 *bit *= RK3188_PULL_BITS_PER_PIN;
701 *regmap = info->regmap_base;
702 *reg = RK3288_PULL_OFFSET;
704 /* correct the offset, as we're starting with the 2nd bank */
706 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
707 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
709 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
710 *bit *= RK3188_PULL_BITS_PER_PIN;
714 #define RK3288_DRV_PMU_OFFSET 0x70
715 #define RK3288_DRV_GRF_OFFSET 0x1c0
716 #define RK3288_DRV_BITS_PER_PIN 2
717 #define RK3288_DRV_PINS_PER_REG 8
718 #define RK3288_DRV_BANK_STRIDE 16
720 static enum rockchip_pin_drv_type rk3288_calc_drv_reg_and_bit(
721 struct rockchip_pin_bank *bank,
722 int pin_num, struct regmap **regmap,
725 struct rockchip_pinctrl *info = bank->drvdata;
727 /* The first 24 pins of the first bank are located in PMU */
728 if (bank->bank_num == 0) {
729 *regmap = info->regmap_pmu;
730 *reg = RK3288_DRV_PMU_OFFSET;
732 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
733 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
734 *bit *= RK3288_DRV_BITS_PER_PIN;
736 *regmap = info->regmap_base;
737 *reg = RK3288_DRV_GRF_OFFSET;
739 /* correct the offset, as we're starting with the 2nd bank */
741 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
742 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
744 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
745 *bit *= RK3288_DRV_BITS_PER_PIN;
748 return DRV_TYPE_IO_DEFAULT;
751 #define RK3228_PULL_OFFSET 0x100
753 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
754 int pin_num, struct regmap **regmap,
757 struct rockchip_pinctrl *info = bank->drvdata;
759 *regmap = info->regmap_base;
760 *reg = RK3228_PULL_OFFSET;
761 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
762 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
764 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
765 *bit *= RK3188_PULL_BITS_PER_PIN;
768 #define RK3228_DRV_GRF_OFFSET 0x200
770 static enum rockchip_pin_drv_type rk3228_calc_drv_reg_and_bit(
771 struct rockchip_pin_bank *bank,
772 int pin_num, struct regmap **regmap,
775 struct rockchip_pinctrl *info = bank->drvdata;
777 *regmap = info->regmap_base;
778 *reg = RK3228_DRV_GRF_OFFSET;
779 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
780 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
782 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
783 *bit *= RK3288_DRV_BITS_PER_PIN;
785 return DRV_TYPE_IO_DEFAULT;
788 #define RK3366_PULL_GRF_OFFSET 0x110
789 #define RK3366_PULL_PMU_OFFSET 0x10
791 static void rk3366_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
792 int pin_num, struct regmap **regmap,
795 struct rockchip_pinctrl *info = bank->drvdata;
797 /* The bank0:32 and bank1:16 pins are located in PMU */
798 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
799 *regmap = info->regmap_pmu;
800 *reg = RK3366_PULL_PMU_OFFSET + bank->bank_num * 0x30;
802 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
803 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
804 *bit *= RK3188_PULL_BITS_PER_PIN;
806 *regmap = info->regmap_base;
807 *reg = RK3366_PULL_GRF_OFFSET;
809 /* correct the offset, as we're starting with the 2nd bank */
811 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
812 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
814 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
815 *bit *= RK3188_PULL_BITS_PER_PIN;
819 #define RK3366_DRV_PMU_OFFSET 0x20
820 #define RK3366_DRV_GRF_OFFSET 0x210
822 #define RK3366_DRV_GPIO2B3_OFFSET 0x378
823 #define RK3366_DRV_GPIO2B3_BITS 4
825 #define RK3366_DRV_GPIO3A4_OFFSET 0x37c
826 #define RK3366_DRV_GPIO3A4_BITS 4
828 static enum rockchip_pin_drv_type rk3366_calc_drv_reg_and_bit(
829 struct rockchip_pin_bank *bank,
830 int pin_num, struct regmap **regmap,
833 struct rockchip_pinctrl *info = bank->drvdata;
835 /* The bank0:32 and bank1:16 pins are located in PMU */
836 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
837 *regmap = info->regmap_pmu;
838 *reg = RK3366_DRV_PMU_OFFSET + bank->bank_num * 0x30;
840 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
841 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
842 *bit *= RK3288_DRV_BITS_PER_PIN;
844 return DRV_TYPE_IO_DEFAULT;
845 } else if ((bank->bank_num == 2) && (pin_num == 11)) {
846 /* GPIO2B3 is a special case in bank2 */
847 *regmap = info->regmap_base;
848 *reg = RK3366_DRV_GPIO2B3_OFFSET;
849 *bit = RK3366_DRV_GPIO2B3_BITS;
851 return DRV_TYPE_IO_WIDE_LEVEL;
852 } else if ((bank->bank_num == 3) && (pin_num == 4)) {
853 /* GPIO3A4 is a special case in bank3 */
854 *regmap = info->regmap_base;
855 *reg = RK3366_DRV_GPIO3A4_OFFSET;
856 *bit = RK3366_DRV_GPIO3A4_BITS;
858 return DRV_TYPE_IO_WIDE_LEVEL;
861 *regmap = info->regmap_base;
862 *reg = RK3366_DRV_GRF_OFFSET;
864 /* correct the offset, as we're starting with the 2nd bank */
866 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
867 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
869 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
870 *bit *= RK3288_DRV_BITS_PER_PIN;
872 /* special cases need special handle */
873 if ((bank->bank_num == 2) && (pin_num == 14))
874 return DRV_TYPE_IO_WIDE_LEVEL;
875 else if ((bank->bank_num == 2) && (pin_num == 16))
876 return DRV_TYPE_IO_NARROW_LEVEL;
877 else if ((bank->bank_num == 2) && (pin_num >= 24) && (pin_num <= 26))
878 return DRV_TYPE_IO_WIDE_LEVEL;
880 return DRV_TYPE_IO_DEFAULT;
883 #define RK3366_DRV_GPIO2A_EN_OFFSET 0x360
884 #define RK3366_DRV_GPIO2A_EP_OFFSET 0x364
886 #define RK3366_DRV_GPIO2C_EN_OFFSET 0x368
887 #define RK3366_DRV_GPIO2C_EP_OFFSET 0x36C
889 #define RK3366_DRV_GPIO2D_EN_OFFSET 0x370
890 #define RK3366_DRV_GPIO2D_EP_OFFSET 0x374
892 #define RK3366_DRV_GPIO2B3_E_OFFSET 0x378
893 #define RK3366_DRV_GPIO2B3_EN_BIT 0
894 #define RK3366_DRV_GPIO2B3_EP_BIT 2
896 #define RK3366_DRV_GPIO3A4_E_OFFSET 0x37c
897 #define RK3366_DRV_GPIO3A4_EN_BIT 0
898 #define RK3366_DRV_GPIO3A4_EP_BIT 2
900 #define RK3366_DRV_GPIO2B6_E_OFFSET 0x404
901 #define RK3366_DRV_GPIO2B6_EN_BIT 12
902 #define RK3366_DRV_GPIO2B6_EP_BIT 14
904 static enum rockchip_pin_extra_drv_type rk3366_calc_drv_extra_reg_and_bit(
905 struct rockchip_pin_bank *bank,
907 struct regmap **regmap,
910 struct rockchip_pinctrl *info = bank->drvdata;
912 *regmap = info->regmap_base;
913 if (bank->bank_num == 2) {
914 switch (pin_num / 8) {
916 *reg = RK3366_DRV_GPIO2A_EN_OFFSET;
919 /* special cases need special handle */
921 *reg = RK3366_DRV_GPIO2B3_E_OFFSET;
922 *bit = RK3366_DRV_GPIO2B3_EN_BIT;
923 } else if (pin_num == 14) {
924 *reg = RK3366_DRV_GPIO2B6_E_OFFSET;
925 *bit = RK3366_DRV_GPIO2B6_EN_BIT;
930 return DRV_TYPE_EXTRA_SAME_OFFSET;
932 *reg = RK3366_DRV_GPIO2C_EN_OFFSET;
935 *reg = RK3366_DRV_GPIO2D_EN_OFFSET;
941 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
942 *bit *= RK3288_DRV_BITS_PER_PIN;
944 return DRV_TYPE_EXTRA_SAME_BITS;
947 /* GPIO3A4 is a special case */
948 if ((pin_num != 4) && (bank->bank_num != 3))
951 *reg = RK3366_DRV_GPIO3A4_E_OFFSET;
952 *bit = RK3366_DRV_GPIO3A4_EN_BIT;
954 return DRV_TYPE_EXTRA_SAME_OFFSET;
957 #define RK3368_PULL_GRF_OFFSET 0x100
958 #define RK3368_PULL_PMU_OFFSET 0x10
960 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
961 int pin_num, struct regmap **regmap,
964 struct rockchip_pinctrl *info = bank->drvdata;
966 /* The first 32 pins of the first bank are located in PMU */
967 if (bank->bank_num == 0) {
968 *regmap = info->regmap_pmu;
969 *reg = RK3368_PULL_PMU_OFFSET;
971 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
972 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
973 *bit *= RK3188_PULL_BITS_PER_PIN;
975 *regmap = info->regmap_base;
976 *reg = RK3368_PULL_GRF_OFFSET;
978 /* correct the offset, as we're starting with the 2nd bank */
980 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
981 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
983 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
984 *bit *= RK3188_PULL_BITS_PER_PIN;
988 #define RK3368_DRV_PMU_OFFSET 0x20
989 #define RK3368_DRV_GRF_OFFSET 0x200
991 static enum rockchip_pin_drv_type rk3368_calc_drv_reg_and_bit(
992 struct rockchip_pin_bank *bank,
993 int pin_num, struct regmap **regmap,
996 struct rockchip_pinctrl *info = bank->drvdata;
998 /* The first 32 pins of the first bank are located in PMU */
999 if (bank->bank_num == 0) {
1000 *regmap = info->regmap_pmu;
1001 *reg = RK3368_DRV_PMU_OFFSET;
1003 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1004 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1005 *bit *= RK3288_DRV_BITS_PER_PIN;
1007 *regmap = info->regmap_base;
1008 *reg = RK3368_DRV_GRF_OFFSET;
1010 /* correct the offset, as we're starting with the 2nd bank */
1012 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1013 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1015 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1016 *bit *= RK3288_DRV_BITS_PER_PIN;
1019 return DRV_TYPE_IO_DEFAULT;
1022 #define RK3399_PULL_GRF_OFFSET 0xe040
1023 #define RK3399_PULL_PMU_OFFSET 0x40
1024 #define RK3399_DRV_3BITS_PER_PIN 3
1026 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1027 int pin_num, struct regmap **regmap,
1030 struct rockchip_pinctrl *info = bank->drvdata;
1032 /* The bank0:16 and bank1:32 pins are located in PMU */
1033 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1034 *regmap = info->regmap_pmu;
1035 *reg = RK3399_PULL_PMU_OFFSET;
1037 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1039 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1040 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1041 *bit *= RK3188_PULL_BITS_PER_PIN;
1043 *regmap = info->regmap_base;
1044 *reg = RK3399_PULL_GRF_OFFSET;
1046 /* correct the offset, as we're starting with the 3rd bank */
1048 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1049 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1051 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1052 *bit *= RK3188_PULL_BITS_PER_PIN;
1056 static enum rockchip_pin_drv_type rk3399_calc_drv_reg_and_bit(
1057 struct rockchip_pin_bank *bank,
1058 int pin_num, struct regmap **regmap,
1061 struct rockchip_pinctrl *info = bank->drvdata;
1062 int drv_num = (pin_num / 8);
1064 /* The bank0:16 and bank1:32 pins are located in PMU */
1065 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1066 *regmap = info->regmap_pmu;
1068 *regmap = info->regmap_base;
1070 *reg = bank->drv[drv_num].offset;
1071 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1072 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1073 *bit = (pin_num % 8) * 3;
1075 *bit = (pin_num % 8) * 2;
1077 return DRV_TYPE_IO_DEFAULT;
1080 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1081 { 2, 4, 8, 12, -1, -1, -1, -1 },
1082 { 3, 6, 9, 12, -1, -1, -1, -1 },
1083 { 5, 10, 15, 20, -1, -1, -1, -1 },
1084 { 4, 6, 8, 10, 12, 14, 16, 18 },
1085 { 4, 7, 10, 13, 16, 19, 22, 26 },
1086 { 0, 6, 12, 18, -1, -1, -1, -1 },
1087 { 4, 8, 12, 16, -1, -1, -1, -1 }
1090 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1093 struct rockchip_pinctrl *info = bank->drvdata;
1094 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1095 struct regmap *regmap, *extra_regmap;
1096 int reg, ret, extra_reg;
1097 u32 data, temp, rmask_bits;
1101 drv_type = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1103 drv_type = bank->drv[pin_num / 8].drv_type;
1106 case DRV_TYPE_IO_1V8_3V0_AUTO:
1107 case DRV_TYPE_IO_3V3_ONLY:
1108 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1111 /* regular case, nothing to do */
1115 * drive-strength offset is special, as it is
1116 * spread over 2 registers
1118 ret = regmap_read(regmap, reg, &data);
1122 ret = regmap_read(regmap, reg + 0x4, &temp);
1127 * the bit data[15] contains bit 0 of the value
1128 * while temp[1:0] contains bits 2 and 1
1135 return rockchip_perpin_drv_list[drv_type][data];
1137 /* setting fully enclosed in the second register */
1142 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1148 case DRV_TYPE_IO_WIDE_LEVEL:
1149 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1150 /* enable the write to the equivalent lower bits */
1151 ret = regmap_read(regmap, reg, &data);
1155 data &= (1 << rmask_bits) - 1;
1158 * assume the drive strength of N channel and
1159 * P channel are the same.
1161 if (ctrl->drv_calc_extra_reg)
1162 ctrl->drv_calc_extra_reg(bank, pin_num,
1168 * It is enough to read one channel drive strength,
1169 * this is N channel.
1171 ret = regmap_read(extra_regmap, extra_reg, &temp);
1176 temp &= (1 << rmask_bits) - 1;
1178 return (rockchip_perpin_drv_list[drv_type][data]) + (temp * 2);
1179 case DRV_TYPE_IO_DEFAULT:
1180 case DRV_TYPE_IO_1V8_OR_3V0:
1181 case DRV_TYPE_IO_1V8_ONLY:
1182 case DRV_TYPE_IO_NARROW_LEVEL:
1183 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1186 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1191 ret = regmap_read(regmap, reg, &data);
1196 data &= (1 << rmask_bits) - 1;
1198 return rockchip_perpin_drv_list[drv_type][data];
1201 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1202 int pin_num, int strength)
1204 struct rockchip_pinctrl *info = bank->drvdata;
1205 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1206 struct regmap *regmap, *extra_regmap;
1207 unsigned long flags;
1209 u32 data, temp, rmask, rmask_bits;
1211 int drv_type, extra_drv_type = 0;
1212 int extra_value, extra_reg;
1214 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1215 bank->bank_num, pin_num, strength);
1217 drv_type = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1219 drv_type = bank->drv[pin_num / 8].drv_type;
1223 if (drv_type == DRV_TYPE_IO_WIDE_LEVEL) {
1224 if ((strength % 2 == 0) && (strength <= 24))
1225 ret = ((strength > 18) ? 18 : strength) / 6;
1227 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]);
1229 if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1230 ret = rockchip_perpin_drv_list[drv_type][i];
1232 } else if (rockchip_perpin_drv_list[drv_type][i] ==
1241 dev_err(info->dev, "unsupported driver strength %d\n",
1246 spin_lock_irqsave(&bank->slock, flags);
1249 case DRV_TYPE_IO_1V8_3V0_AUTO:
1250 case DRV_TYPE_IO_3V3_ONLY:
1251 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1254 /* regular case, nothing to do */
1258 * drive-strength offset is special, as it is spread
1259 * over 2 registers, the bit data[15] contains bit 0
1260 * of the value while temp[1:0] contains bits 2 and 1
1262 data = (ret & 0x1) << 15;
1263 temp = (ret >> 0x1) & 0x3;
1265 rmask = BIT(15) | BIT(31);
1267 ret = regmap_update_bits(regmap, reg, rmask, data);
1269 spin_unlock_irqrestore(&bank->slock, flags);
1273 rmask = 0x3 | (0x3 << 16);
1274 temp |= (0x3 << 16);
1276 ret = regmap_update_bits(regmap, reg, rmask, temp);
1278 spin_unlock_irqrestore(&bank->slock, flags);
1281 /* setting fully enclosed in the second register */
1286 spin_unlock_irqrestore(&bank->slock, flags);
1287 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1292 case DRV_TYPE_IO_WIDE_LEVEL:
1293 extra_value = ((strength -
1294 rockchip_perpin_drv_list[drv_type][ret])) >> 1;
1295 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1298 * assume the drive strength of N channel and
1299 * P channel are the same.
1301 if (ctrl->drv_calc_extra_reg)
1302 extra_drv_type = ctrl->drv_calc_extra_reg(bank, pin_num,
1307 /* enable the write to the equivalent lower bits */
1308 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1309 rmask = data | (data >> 16);
1310 data |= (extra_value << extra_bit);
1312 /* write drive strength of N channel */
1313 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data))
1316 if (extra_drv_type == DRV_TYPE_EXTRA_SAME_OFFSET)
1318 else if (extra_drv_type == DRV_TYPE_EXTRA_SAME_BITS)
1323 /* enable the write to the equivalent lower bits */
1324 data = ((1 << rmask_bits) - 1) << (extra_bit + 16);
1325 rmask = data | (data >> 16);
1326 data |= (extra_value << extra_bit);
1328 /* write drive strength of P channel */
1329 if (regmap_update_bits(extra_regmap, extra_reg, rmask, data))
1333 case DRV_TYPE_IO_DEFAULT:
1334 case DRV_TYPE_IO_1V8_OR_3V0:
1335 case DRV_TYPE_IO_1V8_ONLY:
1336 case DRV_TYPE_IO_NARROW_LEVEL:
1337 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1340 spin_unlock_irqrestore(&bank->slock, flags);
1341 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1346 /* enable the write to the equivalent lower bits */
1347 data = ((1 << rmask_bits) - 1) << (bit + 16);
1348 rmask = data | (data >> 16);
1349 data |= (ret << bit);
1351 ret = regmap_update_bits(regmap, reg, rmask, data);
1352 spin_unlock_irqrestore(&bank->slock, flags);
1357 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1359 struct rockchip_pinctrl *info = bank->drvdata;
1360 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1361 struct regmap *regmap;
1366 /* rk3066b does support any pulls */
1367 if (ctrl->type == RK3066B)
1368 return PIN_CONFIG_BIAS_DISABLE;
1370 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1372 ret = regmap_read(regmap, reg, &data);
1376 switch (ctrl->type) {
1378 return !(data & BIT(bit))
1379 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1380 : PIN_CONFIG_BIAS_DISABLE;
1387 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1391 return PIN_CONFIG_BIAS_DISABLE;
1393 return PIN_CONFIG_BIAS_PULL_UP;
1395 return PIN_CONFIG_BIAS_PULL_DOWN;
1397 return PIN_CONFIG_BIAS_BUS_HOLD;
1400 dev_err(info->dev, "unknown pull setting\n");
1403 dev_err(info->dev, "unsupported pinctrl type\n");
1408 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1409 int pin_num, int pull)
1411 struct rockchip_pinctrl *info = bank->drvdata;
1412 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1413 struct regmap *regmap;
1415 unsigned long flags;
1419 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1420 bank->bank_num, pin_num, pull);
1422 /* rk3066b does support any pulls */
1423 if (ctrl->type == RK3066B)
1424 return pull ? -EINVAL : 0;
1426 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1428 switch (ctrl->type) {
1430 spin_lock_irqsave(&bank->slock, flags);
1432 data = BIT(bit + 16);
1433 if (pull == PIN_CONFIG_BIAS_DISABLE)
1435 ret = regmap_write(regmap, reg, data);
1437 spin_unlock_irqrestore(&bank->slock, flags);
1444 spin_lock_irqsave(&bank->slock, flags);
1446 /* enable the write to the equivalent lower bits */
1447 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1448 rmask = data | (data >> 16);
1451 case PIN_CONFIG_BIAS_DISABLE:
1453 case PIN_CONFIG_BIAS_PULL_UP:
1456 case PIN_CONFIG_BIAS_PULL_DOWN:
1459 case PIN_CONFIG_BIAS_BUS_HOLD:
1463 spin_unlock_irqrestore(&bank->slock, flags);
1464 dev_err(info->dev, "unsupported pull setting %d\n",
1469 ret = regmap_update_bits(regmap, reg, rmask, data);
1471 spin_unlock_irqrestore(&bank->slock, flags);
1474 dev_err(info->dev, "unsupported pinctrl type\n");
1482 * Pinmux_ops handling
1485 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1487 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1489 return info->nfunctions;
1492 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1495 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1497 return info->functions[selector].name;
1500 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1501 unsigned selector, const char * const **groups,
1502 unsigned * const num_groups)
1504 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1506 *groups = info->functions[selector].groups;
1507 *num_groups = info->functions[selector].ngroups;
1512 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1515 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1516 const unsigned int *pins = info->groups[group].pins;
1517 const struct rockchip_pin_config *data = info->groups[group].data;
1518 struct rockchip_pin_bank *bank;
1521 dev_dbg(info->dev, "enable function %s group %s\n",
1522 info->functions[selector].name, info->groups[group].name);
1525 * for each pin in the pin group selected, program the correspoding pin
1526 * pin function number in the config register.
1528 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1529 bank = pin_to_bank(info, pins[cnt]);
1530 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1537 /* revert the already done pin settings */
1538 for (cnt--; cnt >= 0; cnt--)
1539 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1548 * The calls to gpio_direction_output() and gpio_direction_input()
1549 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1550 * function called from the gpiolib interface).
1552 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1553 int pin, bool input)
1555 struct rockchip_pin_bank *bank;
1557 unsigned long flags;
1560 bank = gc_to_pin_bank(chip);
1562 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1566 clk_enable(bank->clk);
1567 spin_lock_irqsave(&bank->slock, flags);
1569 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1570 /* set bit to 1 for output, 0 for input */
1575 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1577 spin_unlock_irqrestore(&bank->slock, flags);
1578 clk_disable(bank->clk);
1583 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1584 struct pinctrl_gpio_range *range,
1585 unsigned offset, bool input)
1587 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1588 struct gpio_chip *chip;
1592 pin = offset - chip->base;
1593 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1594 offset, range->name, pin, input ? "input" : "output");
1596 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1600 static const struct pinmux_ops rockchip_pmx_ops = {
1601 .get_functions_count = rockchip_pmx_get_funcs_count,
1602 .get_function_name = rockchip_pmx_get_func_name,
1603 .get_function_groups = rockchip_pmx_get_groups,
1604 .set_mux = rockchip_pmx_set,
1605 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1609 * Pinconf_ops handling
1612 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1613 enum pin_config_param pull)
1615 switch (ctrl->type) {
1617 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1618 pull == PIN_CONFIG_BIAS_DISABLE);
1620 return pull ? false : true;
1626 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1632 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1633 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1635 /* set the pin config settings for a specified pin */
1636 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1637 unsigned long *configs, unsigned num_configs)
1639 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1640 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1641 enum pin_config_param param;
1646 for (i = 0; i < num_configs; i++) {
1647 param = pinconf_to_config_param(configs[i]);
1648 arg = pinconf_to_config_argument(configs[i]);
1651 case PIN_CONFIG_BIAS_DISABLE:
1652 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1657 case PIN_CONFIG_BIAS_PULL_UP:
1658 case PIN_CONFIG_BIAS_PULL_DOWN:
1659 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1660 case PIN_CONFIG_BIAS_BUS_HOLD:
1661 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1667 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1672 case PIN_CONFIG_OUTPUT:
1673 rockchip_gpio_set(&bank->gpio_chip,
1674 pin - bank->pin_base, arg);
1675 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1676 pin - bank->pin_base, false);
1680 case PIN_CONFIG_DRIVE_STRENGTH:
1681 /* rk3288 is the first with per-pin drive-strength */
1682 if (!info->ctrl->drv_calc_reg)
1685 rc = rockchip_set_drive_perpin(bank,
1686 pin - bank->pin_base, arg);
1694 } /* for each config */
1699 /* get the pin config settings for a specified pin */
1700 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1701 unsigned long *config)
1703 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1704 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1705 enum pin_config_param param = pinconf_to_config_param(*config);
1710 case PIN_CONFIG_BIAS_DISABLE:
1711 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1716 case PIN_CONFIG_BIAS_PULL_UP:
1717 case PIN_CONFIG_BIAS_PULL_DOWN:
1718 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1719 case PIN_CONFIG_BIAS_BUS_HOLD:
1720 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1723 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1728 case PIN_CONFIG_OUTPUT:
1729 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1730 if (rc != RK_FUNC_GPIO)
1733 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1739 case PIN_CONFIG_DRIVE_STRENGTH:
1740 /* rk3288 is the first with per-pin drive-strength */
1741 if (!info->ctrl->drv_calc_reg)
1744 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1755 *config = pinconf_to_config_packed(param, arg);
1760 static const struct pinconf_ops rockchip_pinconf_ops = {
1761 .pin_config_get = rockchip_pinconf_get,
1762 .pin_config_set = rockchip_pinconf_set,
1766 static const struct of_device_id rockchip_bank_match[] = {
1767 { .compatible = "rockchip,gpio-bank" },
1768 { .compatible = "rockchip,rk3188-gpio-bank0" },
1772 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1773 struct device_node *np)
1775 struct device_node *child;
1777 for_each_child_of_node(np, child) {
1778 if (of_match_node(rockchip_bank_match, child))
1782 info->ngroups += of_get_child_count(child);
1786 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1787 struct rockchip_pin_group *grp,
1788 struct rockchip_pinctrl *info,
1791 struct rockchip_pin_bank *bank;
1798 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1800 /* Initialise group */
1801 grp->name = np->name;
1804 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1805 * do sanity check and calculate pins number
1807 list = of_get_property(np, "rockchip,pins", &size);
1808 /* we do not check return since it's safe node passed down */
1809 size /= sizeof(*list);
1810 if (!size || size % 4) {
1811 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1815 grp->npins = size / 4;
1817 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1819 grp->data = devm_kzalloc(info->dev, grp->npins *
1820 sizeof(struct rockchip_pin_config),
1822 if (!grp->pins || !grp->data)
1825 for (i = 0, j = 0; i < size; i += 4, j++) {
1826 const __be32 *phandle;
1827 struct device_node *np_config;
1829 num = be32_to_cpu(*list++);
1830 bank = bank_num_to_bank(info, num);
1832 return PTR_ERR(bank);
1834 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1835 grp->data[j].func = be32_to_cpu(*list++);
1841 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1842 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1843 &grp->data[j].configs, &grp->data[j].nconfigs);
1851 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1852 struct rockchip_pinctrl *info,
1855 struct device_node *child;
1856 struct rockchip_pmx_func *func;
1857 struct rockchip_pin_group *grp;
1859 static u32 grp_index;
1862 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1864 func = &info->functions[index];
1866 /* Initialise function */
1867 func->name = np->name;
1868 func->ngroups = of_get_child_count(np);
1869 if (func->ngroups <= 0)
1872 func->groups = devm_kzalloc(info->dev,
1873 func->ngroups * sizeof(char *), GFP_KERNEL);
1877 for_each_child_of_node(np, child) {
1878 func->groups[i] = child->name;
1879 grp = &info->groups[grp_index++];
1880 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1890 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1891 struct rockchip_pinctrl *info)
1893 struct device *dev = &pdev->dev;
1894 struct device_node *np = dev->of_node;
1895 struct device_node *child;
1899 rockchip_pinctrl_child_count(info, np);
1901 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1902 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1904 info->functions = devm_kzalloc(dev, info->nfunctions *
1905 sizeof(struct rockchip_pmx_func),
1907 if (!info->functions) {
1908 dev_err(dev, "failed to allocate memory for function list\n");
1912 info->groups = devm_kzalloc(dev, info->ngroups *
1913 sizeof(struct rockchip_pin_group),
1915 if (!info->groups) {
1916 dev_err(dev, "failed allocate memory for ping group list\n");
1922 for_each_child_of_node(np, child) {
1923 if (of_match_node(rockchip_bank_match, child))
1926 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1928 dev_err(&pdev->dev, "failed to parse function\n");
1937 static int rockchip_pinctrl_register(struct platform_device *pdev,
1938 struct rockchip_pinctrl *info)
1940 struct pinctrl_desc *ctrldesc = &info->pctl;
1941 struct pinctrl_pin_desc *pindesc, *pdesc;
1942 struct rockchip_pin_bank *pin_bank;
1946 ctrldesc->name = "rockchip-pinctrl";
1947 ctrldesc->owner = THIS_MODULE;
1948 ctrldesc->pctlops = &rockchip_pctrl_ops;
1949 ctrldesc->pmxops = &rockchip_pmx_ops;
1950 ctrldesc->confops = &rockchip_pinconf_ops;
1952 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1953 info->ctrl->nr_pins, GFP_KERNEL);
1955 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1958 ctrldesc->pins = pindesc;
1959 ctrldesc->npins = info->ctrl->nr_pins;
1962 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1963 pin_bank = &info->ctrl->pin_banks[bank];
1964 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1966 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1967 pin_bank->name, pin);
1972 ret = rockchip_pinctrl_parse_dt(pdev, info);
1976 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1977 if (IS_ERR(info->pctl_dev)) {
1978 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1979 return PTR_ERR(info->pctl_dev);
1982 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1983 pin_bank = &info->ctrl->pin_banks[bank];
1984 pin_bank->grange.name = pin_bank->name;
1985 pin_bank->grange.id = bank;
1986 pin_bank->grange.pin_base = pin_bank->pin_base;
1987 pin_bank->grange.base = pin_bank->gpio_chip.base;
1988 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1989 pin_bank->grange.gc = &pin_bank->gpio_chip;
1990 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2000 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2002 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2003 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2004 unsigned long flags;
2007 clk_enable(bank->clk);
2008 spin_lock_irqsave(&bank->slock, flags);
2011 data &= ~BIT(offset);
2013 data |= BIT(offset);
2016 spin_unlock_irqrestore(&bank->slock, flags);
2017 clk_disable(bank->clk);
2021 * Returns the level of the pin for input direction and setting of the DR
2022 * register for output gpios.
2024 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2026 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2029 clk_enable(bank->clk);
2030 data = readl(bank->reg_base + GPIO_EXT_PORT);
2031 clk_disable(bank->clk);
2038 * gpiolib gpio_direction_input callback function. The setting of the pin
2039 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2042 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2044 return pinctrl_gpio_direction_input(gc->base + offset);
2048 * gpiolib gpio_direction_output callback function. The setting of the pin
2049 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2052 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2053 unsigned offset, int value)
2055 rockchip_gpio_set(gc, offset, value);
2056 return pinctrl_gpio_direction_output(gc->base + offset);
2060 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2061 * and a virtual IRQ, if not already present.
2063 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2065 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2071 virq = irq_create_mapping(bank->domain, offset);
2073 return (virq) ? : -ENXIO;
2076 static const struct gpio_chip rockchip_gpiolib_chip = {
2077 .request = gpiochip_generic_request,
2078 .free = gpiochip_generic_free,
2079 .set = rockchip_gpio_set,
2080 .get = rockchip_gpio_get,
2081 .direction_input = rockchip_gpio_direction_input,
2082 .direction_output = rockchip_gpio_direction_output,
2083 .to_irq = rockchip_gpio_to_irq,
2084 .owner = THIS_MODULE,
2088 * Interrupt handling
2091 static void rockchip_irq_demux(struct irq_desc *desc)
2093 struct irq_chip *chip = irq_desc_get_chip(desc);
2094 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2097 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2099 chained_irq_enter(chip, desc);
2101 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2104 unsigned int irq, virq;
2108 virq = irq_linear_revmap(bank->domain, irq);
2111 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2115 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2118 * Triggering IRQ on both rising and falling edge
2119 * needs manual intervention.
2121 if (bank->toggle_edge_mode & BIT(irq)) {
2122 u32 data, data_old, polarity;
2123 unsigned long flags;
2125 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2127 spin_lock_irqsave(&bank->slock, flags);
2129 polarity = readl_relaxed(bank->reg_base +
2131 if (data & BIT(irq))
2132 polarity &= ~BIT(irq);
2134 polarity |= BIT(irq);
2136 bank->reg_base + GPIO_INT_POLARITY);
2138 spin_unlock_irqrestore(&bank->slock, flags);
2141 data = readl_relaxed(bank->reg_base +
2143 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2146 generic_handle_irq(virq);
2149 chained_irq_exit(chip, desc);
2152 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2154 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2155 struct rockchip_pin_bank *bank = gc->private;
2156 u32 mask = BIT(d->hwirq);
2160 unsigned long flags;
2163 /* make sure the pin is configured as gpio input */
2164 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2168 clk_enable(bank->clk);
2169 spin_lock_irqsave(&bank->slock, flags);
2171 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2173 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2175 spin_unlock_irqrestore(&bank->slock, flags);
2177 if (type & IRQ_TYPE_EDGE_BOTH)
2178 irq_set_handler_locked(d, handle_edge_irq);
2180 irq_set_handler_locked(d, handle_level_irq);
2182 spin_lock_irqsave(&bank->slock, flags);
2185 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2186 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2189 case IRQ_TYPE_EDGE_BOTH:
2190 bank->toggle_edge_mode |= mask;
2194 * Determine gpio state. If 1 next interrupt should be falling
2197 data = readl(bank->reg_base + GPIO_EXT_PORT);
2203 case IRQ_TYPE_EDGE_RISING:
2204 bank->toggle_edge_mode &= ~mask;
2208 case IRQ_TYPE_EDGE_FALLING:
2209 bank->toggle_edge_mode &= ~mask;
2213 case IRQ_TYPE_LEVEL_HIGH:
2214 bank->toggle_edge_mode &= ~mask;
2218 case IRQ_TYPE_LEVEL_LOW:
2219 bank->toggle_edge_mode &= ~mask;
2225 spin_unlock_irqrestore(&bank->slock, flags);
2226 clk_disable(bank->clk);
2230 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2231 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2234 spin_unlock_irqrestore(&bank->slock, flags);
2235 clk_disable(bank->clk);
2240 static void rockchip_irq_suspend(struct irq_data *d)
2242 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2243 struct rockchip_pin_bank *bank = gc->private;
2245 clk_enable(bank->clk);
2246 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2247 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2248 clk_disable(bank->clk);
2251 static void rockchip_irq_resume(struct irq_data *d)
2253 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2254 struct rockchip_pin_bank *bank = gc->private;
2256 clk_enable(bank->clk);
2257 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2258 clk_disable(bank->clk);
2261 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2263 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2264 struct rockchip_pin_bank *bank = gc->private;
2266 clk_enable(bank->clk);
2267 irq_gc_mask_clr_bit(d);
2270 void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2272 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2273 struct rockchip_pin_bank *bank = gc->private;
2275 irq_gc_mask_set_bit(d);
2276 clk_disable(bank->clk);
2279 static int rockchip_interrupts_register(struct platform_device *pdev,
2280 struct rockchip_pinctrl *info)
2282 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2283 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2284 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2285 struct irq_chip_generic *gc;
2289 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2291 dev_warn(&pdev->dev, "bank %s is not valid\n",
2296 ret = clk_enable(bank->clk);
2298 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2303 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2304 &irq_generic_chip_ops, NULL);
2305 if (!bank->domain) {
2306 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2308 clk_disable(bank->clk);
2312 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2313 "rockchip_gpio_irq", handle_level_irq,
2314 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2316 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2318 irq_domain_remove(bank->domain);
2319 clk_disable(bank->clk);
2324 * Linux assumes that all interrupts start out disabled/masked.
2325 * Our driver only uses the concept of masked and always keeps
2326 * things enabled, so for us that's all masked and all enabled.
2328 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2329 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2331 gc = irq_get_domain_generic_chip(bank->domain, 0);
2332 gc->reg_base = bank->reg_base;
2334 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2335 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2336 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2337 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2338 gc->chip_types[0].chip.irq_unmask =
2339 rockchip_irq_gc_mask_clr_bit;
2340 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2341 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2342 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2343 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2344 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2346 irq_set_chained_handler_and_data(bank->irq,
2347 rockchip_irq_demux, bank);
2349 /* map the gpio irqs here, when the clock is still running */
2350 for (j = 0 ; j < 32 ; j++)
2351 irq_create_mapping(bank->domain, j);
2353 clk_disable(bank->clk);
2359 static int rockchip_gpiolib_register(struct platform_device *pdev,
2360 struct rockchip_pinctrl *info)
2362 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2363 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2364 struct gpio_chip *gc;
2368 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2370 dev_warn(&pdev->dev, "bank %s is not valid\n",
2375 bank->gpio_chip = rockchip_gpiolib_chip;
2377 gc = &bank->gpio_chip;
2378 gc->base = bank->pin_base;
2379 gc->ngpio = bank->nr_pins;
2380 gc->dev = &pdev->dev;
2381 gc->of_node = bank->of_node;
2382 gc->label = bank->name;
2384 ret = gpiochip_add(gc);
2386 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2392 rockchip_interrupts_register(pdev, info);
2397 for (--i, --bank; i >= 0; --i, --bank) {
2400 gpiochip_remove(&bank->gpio_chip);
2405 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2406 struct rockchip_pinctrl *info)
2408 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2409 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2412 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2415 gpiochip_remove(&bank->gpio_chip);
2421 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2422 struct rockchip_pinctrl *info)
2424 struct resource res;
2427 if (of_address_to_resource(bank->of_node, 0, &res)) {
2428 dev_err(info->dev, "cannot find IO resource for bank\n");
2432 bank->reg_base = devm_ioremap_resource(info->dev, &res);
2433 if (IS_ERR(bank->reg_base))
2434 return PTR_ERR(bank->reg_base);
2437 * special case, where parts of the pull setting-registers are
2438 * part of the PMU register space
2440 if (of_device_is_compatible(bank->of_node,
2441 "rockchip,rk3188-gpio-bank0")) {
2442 struct device_node *node;
2444 node = of_parse_phandle(bank->of_node->parent,
2447 if (of_address_to_resource(bank->of_node, 1, &res)) {
2448 dev_err(info->dev, "cannot find IO resource for bank\n");
2452 base = devm_ioremap_resource(info->dev, &res);
2454 return PTR_ERR(base);
2455 rockchip_regmap_config.max_register =
2456 resource_size(&res) - 4;
2457 rockchip_regmap_config.name =
2458 "rockchip,rk3188-gpio-bank0-pull";
2459 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2461 &rockchip_regmap_config);
2465 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2467 bank->clk = of_clk_get(bank->of_node, 0);
2468 if (IS_ERR(bank->clk))
2469 return PTR_ERR(bank->clk);
2471 return clk_prepare(bank->clk);
2474 static const struct of_device_id rockchip_pinctrl_dt_match[];
2476 /* retrieve the soc specific data */
2477 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2478 struct rockchip_pinctrl *d,
2479 struct platform_device *pdev)
2481 const struct of_device_id *match;
2482 struct device_node *node = pdev->dev.of_node;
2483 struct device_node *np;
2484 struct rockchip_pin_ctrl *ctrl;
2485 struct rockchip_pin_bank *bank;
2486 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2488 match = of_match_node(rockchip_pinctrl_dt_match, node);
2489 ctrl = (struct rockchip_pin_ctrl *)match->data;
2491 for_each_child_of_node(node, np) {
2492 if (!of_find_property(np, "gpio-controller", NULL))
2495 bank = ctrl->pin_banks;
2496 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2497 if (!strcmp(bank->name, np->name)) {
2500 if (!rockchip_get_bank_data(bank, d))
2508 grf_offs = ctrl->grf_mux_offset;
2509 pmu_offs = ctrl->pmu_mux_offset;
2510 drv_pmu_offs = ctrl->pmu_drv_offset;
2511 drv_grf_offs = ctrl->grf_drv_offset;
2512 bank = ctrl->pin_banks;
2513 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2516 spin_lock_init(&bank->slock);
2518 bank->pin_base = ctrl->nr_pins;
2519 ctrl->nr_pins += bank->nr_pins;
2521 /* calculate iomux and drv offsets */
2522 for (j = 0; j < 4; j++) {
2523 struct rockchip_iomux *iom = &bank->iomux[j];
2524 struct rockchip_drv *drv = &bank->drv[j];
2527 if (bank_pins >= bank->nr_pins)
2530 /* preset iomux offset value, set new start value */
2531 if (iom->offset >= 0) {
2532 if (iom->type & IOMUX_SOURCE_PMU)
2533 pmu_offs = iom->offset;
2535 grf_offs = iom->offset;
2536 } else { /* set current iomux offset */
2537 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2538 pmu_offs : grf_offs;
2541 /* preset drv offset value, set new start value */
2542 if (drv->offset >= 0) {
2543 if (iom->type & IOMUX_SOURCE_PMU)
2544 drv_pmu_offs = drv->offset;
2546 drv_grf_offs = drv->offset;
2547 } else { /* set current drv offset */
2548 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2549 drv_pmu_offs : drv_grf_offs;
2552 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2553 i, j, iom->offset, drv->offset);
2556 * Increase offset according to iomux width.
2557 * 4bit iomux'es are spread over two registers.
2559 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2560 if (iom->type & IOMUX_SOURCE_PMU)
2566 * Increase offset according to drv width.
2567 * 3bit drive-strenth'es are spread over two registers.
2569 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2570 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2575 if (iom->type & IOMUX_SOURCE_PMU)
2576 drv_pmu_offs += inc;
2578 drv_grf_offs += inc;
2587 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2588 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2590 static u32 rk3288_grf_gpio6c_iomux;
2592 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2594 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2595 int ret = pinctrl_force_sleep(info->pctl_dev);
2601 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2602 * the setting here, and restore it at resume.
2604 if (info->ctrl->type == RK3288) {
2605 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2606 &rk3288_grf_gpio6c_iomux);
2608 pinctrl_force_default(info->pctl_dev);
2616 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2618 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2619 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2620 rk3288_grf_gpio6c_iomux |
2621 GPIO6C6_SEL_WRITE_ENABLE);
2626 return pinctrl_force_default(info->pctl_dev);
2629 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2630 rockchip_pinctrl_resume);
2632 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2634 struct rockchip_pinctrl *info;
2635 struct device *dev = &pdev->dev;
2636 struct rockchip_pin_ctrl *ctrl;
2637 struct device_node *np = pdev->dev.of_node, *node;
2638 struct resource *res;
2642 if (!dev->of_node) {
2643 dev_err(dev, "device tree node not found\n");
2647 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2653 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2655 dev_err(dev, "driver data not available\n");
2660 node = of_parse_phandle(np, "rockchip,grf", 0);
2662 info->regmap_base = syscon_node_to_regmap(node);
2663 if (IS_ERR(info->regmap_base))
2664 return PTR_ERR(info->regmap_base);
2666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2667 base = devm_ioremap_resource(&pdev->dev, res);
2669 return PTR_ERR(base);
2671 rockchip_regmap_config.max_register = resource_size(res) - 4;
2672 rockchip_regmap_config.name = "rockchip,pinctrl";
2673 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2674 &rockchip_regmap_config);
2676 /* to check for the old dt-bindings */
2677 info->reg_size = resource_size(res);
2679 /* Honor the old binding, with pull registers as 2nd resource */
2680 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2681 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2682 base = devm_ioremap_resource(&pdev->dev, res);
2684 return PTR_ERR(base);
2686 rockchip_regmap_config.max_register =
2687 resource_size(res) - 4;
2688 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2689 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2691 &rockchip_regmap_config);
2695 /* try to find the optional reference to the pmu syscon */
2696 node = of_parse_phandle(np, "rockchip,pmu", 0);
2698 info->regmap_pmu = syscon_node_to_regmap(node);
2699 if (IS_ERR(info->regmap_pmu))
2700 return PTR_ERR(info->regmap_pmu);
2703 ret = rockchip_gpiolib_register(pdev, info);
2707 ret = rockchip_pinctrl_register(pdev, info);
2709 rockchip_gpiolib_unregister(pdev, info);
2713 platform_set_drvdata(pdev, info);
2718 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2719 PIN_BANK(0, 32, "gpio0"),
2720 PIN_BANK(1, 32, "gpio1"),
2721 PIN_BANK(2, 32, "gpio2"),
2722 PIN_BANK(3, 32, "gpio3"),
2725 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2726 .pin_banks = rk2928_pin_banks,
2727 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2728 .label = "RK2928-GPIO",
2730 .grf_mux_offset = 0xa8,
2731 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2734 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2735 PIN_BANK(0, 32, "gpio0"),
2736 PIN_BANK(1, 32, "gpio1"),
2737 PIN_BANK(2, 32, "gpio2"),
2740 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2741 .pin_banks = rk3036_pin_banks,
2742 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2743 .label = "RK3036-GPIO",
2745 .grf_mux_offset = 0xa8,
2746 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2749 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2750 PIN_BANK(0, 32, "gpio0"),
2751 PIN_BANK(1, 32, "gpio1"),
2752 PIN_BANK(2, 32, "gpio2"),
2753 PIN_BANK(3, 32, "gpio3"),
2754 PIN_BANK(4, 32, "gpio4"),
2755 PIN_BANK(6, 16, "gpio6"),
2758 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2759 .pin_banks = rk3066a_pin_banks,
2760 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2761 .label = "RK3066a-GPIO",
2763 .grf_mux_offset = 0xa8,
2764 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2767 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2768 PIN_BANK(0, 32, "gpio0"),
2769 PIN_BANK(1, 32, "gpio1"),
2770 PIN_BANK(2, 32, "gpio2"),
2771 PIN_BANK(3, 32, "gpio3"),
2774 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2775 .pin_banks = rk3066b_pin_banks,
2776 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2777 .label = "RK3066b-GPIO",
2779 .grf_mux_offset = 0x60,
2782 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2783 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2784 PIN_BANK(1, 32, "gpio1"),
2785 PIN_BANK(2, 32, "gpio2"),
2786 PIN_BANK(3, 32, "gpio3"),
2789 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2790 .pin_banks = rk3188_pin_banks,
2791 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2792 .label = "RK3188-GPIO",
2794 .grf_mux_offset = 0x60,
2795 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2798 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2799 PIN_BANK(0, 32, "gpio0"),
2800 PIN_BANK(1, 32, "gpio1"),
2801 PIN_BANK(2, 32, "gpio2"),
2802 PIN_BANK(3, 32, "gpio3"),
2805 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2806 .pin_banks = rk3228_pin_banks,
2807 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2808 .label = "RK3228-GPIO",
2810 .grf_mux_offset = 0x0,
2811 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2812 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2815 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2816 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2821 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2826 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2827 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2828 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2833 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2838 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2839 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2844 PIN_BANK(8, 16, "gpio8"),
2847 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2848 .pin_banks = rk3288_pin_banks,
2849 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2850 .label = "RK3288-GPIO",
2852 .grf_mux_offset = 0x0,
2853 .pmu_mux_offset = 0x84,
2854 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2855 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
2858 static struct rockchip_pin_bank rk3366_pin_banks[] = {
2859 PIN_BANK_IOMUX_DRV_FLAGS(0, 32, "gpio0",
2864 DRV_TYPE_IO_NARROW_LEVEL,
2865 DRV_TYPE_IO_NARROW_LEVEL,
2866 DRV_TYPE_IO_NARROW_LEVEL,
2867 DRV_TYPE_IO_NARROW_LEVEL
2869 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
2878 DRV_TYPE_IO_NARROW_LEVEL,
2879 DRV_TYPE_IO_NARROW_LEVEL,
2880 DRV_TYPE_IO_NARROW_LEVEL,
2881 DRV_TYPE_IO_NARROW_LEVEL
2883 PIN_BANK_DRV_FLAGS(2, 32, "gpio2",
2884 DRV_TYPE_IO_WIDE_LEVEL,
2885 DRV_TYPE_IO_NARROW_LEVEL,
2886 DRV_TYPE_IO_WIDE_LEVEL,
2887 DRV_TYPE_IO_NARROW_LEVEL
2889 PIN_BANK_DRV_FLAGS(3, 32, "gpio3",
2890 DRV_TYPE_IO_NARROW_LEVEL,
2891 DRV_TYPE_IO_NARROW_LEVEL,
2892 DRV_TYPE_IO_NARROW_LEVEL,
2893 DRV_TYPE_IO_NARROW_LEVEL
2895 PIN_BANK_DRV_FLAGS(4, 32, "gpio4",
2896 DRV_TYPE_IO_NARROW_LEVEL,
2897 DRV_TYPE_IO_NARROW_LEVEL,
2898 DRV_TYPE_IO_NARROW_LEVEL,
2899 DRV_TYPE_IO_NARROW_LEVEL
2901 PIN_BANK_DRV_FLAGS(5, 32, "gpio5",
2902 DRV_TYPE_IO_NARROW_LEVEL,
2903 DRV_TYPE_IO_NARROW_LEVEL,
2904 DRV_TYPE_IO_NARROW_LEVEL,
2905 DRV_TYPE_IO_NARROW_LEVEL
2909 static struct rockchip_pin_ctrl rk3366_pin_ctrl = {
2910 .pin_banks = rk3366_pin_banks,
2911 .nr_banks = ARRAY_SIZE(rk3366_pin_banks),
2912 .label = "RK3366-GPIO",
2914 .grf_mux_offset = 0x10,
2915 .pmu_mux_offset = 0x0,
2916 .pull_calc_reg = rk3366_calc_pull_reg_and_bit,
2917 .drv_calc_reg = rk3366_calc_drv_reg_and_bit,
2918 .drv_calc_extra_reg = rk3366_calc_drv_extra_reg_and_bit,
2921 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2922 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2927 PIN_BANK(1, 32, "gpio1"),
2928 PIN_BANK(2, 32, "gpio2"),
2929 PIN_BANK(3, 32, "gpio3"),
2932 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2933 .pin_banks = rk3368_pin_banks,
2934 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2935 .label = "RK3368-GPIO",
2937 .grf_mux_offset = 0x0,
2938 .pmu_mux_offset = 0x0,
2939 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2940 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2943 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2944 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2948 DRV_TYPE_IO_1V8_ONLY,
2949 DRV_TYPE_IO_1V8_ONLY,
2950 DRV_TYPE_IO_DEFAULT,
2951 DRV_TYPE_IO_DEFAULT,
2957 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2961 DRV_TYPE_IO_1V8_OR_3V0,
2962 DRV_TYPE_IO_1V8_OR_3V0,
2963 DRV_TYPE_IO_1V8_OR_3V0,
2964 DRV_TYPE_IO_1V8_OR_3V0,
2970 PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2971 DRV_TYPE_IO_1V8_OR_3V0,
2972 DRV_TYPE_IO_1V8_ONLY,
2973 DRV_TYPE_IO_1V8_ONLY
2975 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2976 DRV_TYPE_IO_3V3_ONLY,
2977 DRV_TYPE_IO_3V3_ONLY,
2978 DRV_TYPE_IO_1V8_OR_3V0
2980 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2981 DRV_TYPE_IO_1V8_3V0_AUTO,
2982 DRV_TYPE_IO_1V8_OR_3V0,
2983 DRV_TYPE_IO_1V8_OR_3V0
2987 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2988 .pin_banks = rk3399_pin_banks,
2989 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2990 .label = "RK3399-GPIO",
2992 .grf_mux_offset = 0xe000,
2993 .pmu_mux_offset = 0x0,
2994 .grf_drv_offset = 0xe100,
2995 .pmu_drv_offset = 0x80,
2996 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2997 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3000 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3001 { .compatible = "rockchip,rk2928-pinctrl",
3002 .data = (void *)&rk2928_pin_ctrl },
3003 { .compatible = "rockchip,rk3036-pinctrl",
3004 .data = (void *)&rk3036_pin_ctrl },
3005 { .compatible = "rockchip,rk3066a-pinctrl",
3006 .data = (void *)&rk3066a_pin_ctrl },
3007 { .compatible = "rockchip,rk3066b-pinctrl",
3008 .data = (void *)&rk3066b_pin_ctrl },
3009 { .compatible = "rockchip,rk3188-pinctrl",
3010 .data = (void *)&rk3188_pin_ctrl },
3011 { .compatible = "rockchip,rk3228-pinctrl",
3012 .data = (void *)&rk3228_pin_ctrl },
3013 { .compatible = "rockchip,rk3288-pinctrl",
3014 .data = (void *)&rk3288_pin_ctrl },
3015 { .compatible = "rockchip,rk3366-pinctrl",
3016 .data = (void *)&rk3366_pin_ctrl },
3017 { .compatible = "rockchip,rk3368-pinctrl",
3018 .data = (void *)&rk3368_pin_ctrl },
3019 { .compatible = "rockchip,rk3399-pinctrl",
3020 .data = (void *)&rk3399_pin_ctrl },
3023 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3025 static struct platform_driver rockchip_pinctrl_driver = {
3026 .probe = rockchip_pinctrl_probe,
3028 .name = "rockchip-pinctrl",
3029 .pm = &rockchip_pinctrl_dev_pm_ops,
3030 .of_match_table = rockchip_pinctrl_dt_match,
3034 static int __init rockchip_pinctrl_drv_register(void)
3036 return platform_driver_register(&rockchip_pinctrl_driver);
3038 postcore_initcall(rockchip_pinctrl_drv_register);
3040 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
3041 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3042 MODULE_LICENSE("GPL v2");