drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <dt-bindings/pinctrl/rockchip.h>
  42
  43 #include "core.h"
  44 #include "pinconf.h"
  45
  46 /* GPIO control registers */
  47 #define GPIO_SWPORT_DR          0x00
  48 #define GPIO_SWPORT_DDR         0x04
  49 #define GPIO_INTEN              0x30
  50 #define GPIO_INTMASK            0x34
  51 #define GPIO_INTTYPE_LEVEL      0x38
  52 #define GPIO_INT_POLARITY       0x3c
  53 #define GPIO_INT_STATUS         0x40
  54 #define GPIO_INT_RAWSTATUS      0x44
  55 #define GPIO_DEBOUNCE           0x48
  56 #define GPIO_PORTS_EOI          0x4c
  57 #define GPIO_EXT_PORT           0x50
  58 #define GPIO_LS_SYNC            0x60
  59
  60 enum rockchip_pinctrl_type {
  61         RK2928,
  62         RK3066B,
  63         RK3188,
  64 };
  65
  66 enum rockchip_pin_bank_type {
  67         COMMON_BANK,
  68         RK3188_BANK0,
  69 };
  70
  71 /**
  72  * @reg_base: register base of the gpio bank
  73  * @reg_pull: optional separate register for additional pull settings
  74  * @clk: clock of the gpio bank
  75  * @irq: interrupt of the gpio bank
  76  * @pin_base: first pin number
  77  * @nr_pins: number of pins in this bank
  78  * @name: name of the bank
  79  * @bank_num: number of the bank, to account for holes
  80  * @valid: are all necessary informations present
  81  * @of_node: dt node of this bank
  82  * @drvdata: common pinctrl basedata
  83  * @domain: irqdomain of the gpio bank
  84  * @gpio_chip: gpiolib chip
  85  * @grange: gpio range
  86  * @slock: spinlock for the gpio bank
  87  */
  88 struct rockchip_pin_bank {
  89         void __iomem                    *reg_base;
  90         struct regmap                   *regmap_pull;
  91         struct clk                      *clk;
  92         int                             irq;
  93         u32                             pin_base;
  94         u8                              nr_pins;
  95         char                            *name;
  96         u8                              bank_num;
  97         enum rockchip_pin_bank_type     bank_type;
  98         bool                            valid;
  99         struct device_node              *of_node;
 100         struct rockchip_pinctrl         *drvdata;
 101         struct irq_domain               *domain;
 102         struct gpio_chip                gpio_chip;
 103         struct pinctrl_gpio_range       grange;
 104         spinlock_t                      slock;
 105         u32                             toggle_edge_mode;
 106 };
 107
 108 #define PIN_BANK(id, pins, label)                       \
 109         {                                               \
 110                 .bank_num       = id,                   \
 111                 .nr_pins        = pins,                 \
 112                 .name           = label,                \
 113         }
 114
 115 /**
 116  */
 117 struct rockchip_pin_ctrl {
 118         struct rockchip_pin_bank        *pin_banks;
 119         u32                             nr_banks;
 120         u32                             nr_pins;
 121         char                            *label;
 122         enum rockchip_pinctrl_type      type;
 123         int                             mux_offset;
 124         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 125                                     int pin_num, struct regmap **regmap,
 126                                     int *reg, u8 *bit);
 127 };
 128
 129 struct rockchip_pin_config {
 130         unsigned int            func;
 131         unsigned long           *configs;
 132         unsigned int            nconfigs;
 133 };
 134
 135 /**
 136  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 137  * @name: name of the pin group, used to lookup the group.
 138  * @pins: the pins included in this group.
 139  * @npins: number of pins included in this group.
 140  * @func: the mux function number to be programmed when selected.
 141  * @configs: the config values to be set for each pin
 142  * @nconfigs: number of configs for each pin
 143  */
 144 struct rockchip_pin_group {
 145         const char                      *name;
 146         unsigned int                    npins;
 147         unsigned int                    *pins;
 148         struct rockchip_pin_config      *data;
 149 };
 150
 151 /**
 152  * struct rockchip_pmx_func: represent a pin function.
 153  * @name: name of the pin function, used to lookup the function.
 154  * @groups: one or more names of pin groups that provide this function.
 155  * @num_groups: number of groups included in @groups.
 156  */
 157 struct rockchip_pmx_func {
 158         const char              *name;
 159         const char              **groups;
 160         u8                      ngroups;
 161 };
 162
 163 struct rockchip_pinctrl {
 164         struct regmap                   *regmap_base;
 165         int                             reg_size;
 166         struct regmap                   *regmap_pull;
 167         struct device                   *dev;
 168         struct rockchip_pin_ctrl        *ctrl;
 169         struct pinctrl_desc             pctl;
 170         struct pinctrl_dev              *pctl_dev;
 171         struct rockchip_pin_group       *groups;
 172         unsigned int                    ngroups;
 173         struct rockchip_pmx_func        *functions;
 174         unsigned int                    nfunctions;
 175 };
 176
 177 static struct regmap_config rockchip_regmap_config = {
 178         .reg_bits = 32,
 179         .val_bits = 32,
 180         .reg_stride = 4,
 181 };
 182
 183 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 184 {
 185         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 186 }
 187
 188 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 189                                         const struct rockchip_pinctrl *info,
 190                                         const char *name)
 191 {
 192         int i;
 193
 194         for (i = 0; i < info->ngroups; i++) {
 195                 if (!strcmp(info->groups[i].name, name))
 196                         return &info->groups[i];
 197         }
 198
 199         return NULL;
 200 }
 201
 202 /*
 203  * given a pin number that is local to a pin controller, find out the pin bank
 204  * and the register base of the pin bank.
 205  */
 206 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 207                                                                 unsigned pin)
 208 {
 209         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 210
 211         while (pin >= (b->pin_base + b->nr_pins))
 212                 b++;
 213
 214         return b;
 215 }
 216
 217 static struct rockchip_pin_bank *bank_num_to_bank(
 218                                         struct rockchip_pinctrl *info,
 219                                         unsigned num)
 220 {
 221         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 222         int i;
 223
 224         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 225                 if (b->bank_num == num)
 226                         return b;
 227         }
 228
 229         return ERR_PTR(-EINVAL);
 230 }
 231
 232 /*
 233  * Pinctrl_ops handling
 234  */
 235
 236 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 237 {
 238         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 239
 240         return info->ngroups;
 241 }
 242
 243 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 244                                                         unsigned selector)
 245 {
 246         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 247
 248         return info->groups[selector].name;
 249 }
 250
 251 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 252                                       unsigned selector, const unsigned **pins,
 253                                       unsigned *npins)
 254 {
 255         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 256
 257         if (selector >= info->ngroups)
 258                 return -EINVAL;
 259
 260         *pins = info->groups[selector].pins;
 261         *npins = info->groups[selector].npins;
 262
 263         return 0;
 264 }
 265
 266 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 267                                  struct device_node *np,
 268                                  struct pinctrl_map **map, unsigned *num_maps)
 269 {
 270         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 271         const struct rockchip_pin_group *grp;
 272         struct pinctrl_map *new_map;
 273         struct device_node *parent;
 274         int map_num = 1;
 275         int i;
 276
 277         /*
 278          * first find the group of this node and check if we need to create
 279          * config maps for pins
 280          */
 281         grp = pinctrl_name_to_group(info, np->name);
 282         if (!grp) {
 283                 dev_err(info->dev, "unable to find group for node %s\n",
 284                         np->name);
 285                 return -EINVAL;
 286         }
 287
 288         map_num += grp->npins;
 289         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 290                                                                 GFP_KERNEL);
 291         if (!new_map)
 292                 return -ENOMEM;
 293
 294         *map = new_map;
 295         *num_maps = map_num;
 296
 297         /* create mux map */
 298         parent = of_get_parent(np);
 299         if (!parent) {
 300                 devm_kfree(pctldev->dev, new_map);
 301                 return -EINVAL;
 302         }
 303         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 304         new_map[0].data.mux.function = parent->name;
 305         new_map[0].data.mux.group = np->name;
 306         of_node_put(parent);
 307
 308         /* create config map */
 309         new_map++;
 310         for (i = 0; i < grp->npins; i++) {
 311                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 312                 new_map[i].data.configs.group_or_pin =
 313                                 pin_get_name(pctldev, grp->pins[i]);
 314                 new_map[i].data.configs.configs = grp->data[i].configs;
 315                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 316         }
 317
 318         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 319                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 320
 321         return 0;
 322 }
 323
 324 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 325                                     struct pinctrl_map *map, unsigned num_maps)
 326 {
 327 }
 328
 329 static const struct pinctrl_ops rockchip_pctrl_ops = {
 330         .get_groups_count       = rockchip_get_groups_count,
 331         .get_group_name         = rockchip_get_group_name,
 332         .get_group_pins         = rockchip_get_group_pins,
 333         .dt_node_to_map         = rockchip_dt_node_to_map,
 334         .dt_free_map            = rockchip_dt_free_map,
 335 };
 336
 337 /*
 338  * Hardware access
 339  */
 340
 341 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 342 {
 343         struct rockchip_pinctrl *info = bank->drvdata;
 344         unsigned int val;
 345         int reg, ret;
 346         u8 bit;
 347
 348         if (bank->bank_type == RK3188_BANK0 && pin < 16)
 349                 return RK_FUNC_GPIO;
 350
 351         /* get basic quadrupel of mux registers and the correct reg inside */
 352         reg = info->ctrl->mux_offset;
 353         reg += bank->bank_num * 0x10;
 354         reg += (pin / 8) * 4;
 355         bit = (pin % 8) * 2;
 356
 357         ret = regmap_read(info->regmap_base, reg, &val);
 358         if (ret)
 359                 return ret;
 360
 361         return ((val >> bit) & 3);
 362 }
 363
 364 /*
 365  * Set a new mux function for a pin.
 366  *
 367  * The register is divided into the upper and lower 16 bit. When changing
 368  * a value, the previous register value is not read and changed. Instead
 369  * it seems the changed bits are marked in the upper 16 bit, while the
 370  * changed value gets set in the same offset in the lower 16 bit.
 371  * All pin settings seem to be 2 bit wide in both the upper and lower
 372  * parts.
 373  * @bank: pin bank to change
 374  * @pin: pin to change
 375  * @mux: new mux function to set
 376  */
 377 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 378 {
 379         struct rockchip_pinctrl *info = bank->drvdata;
 380         int reg, ret;
 381         unsigned long flags;
 382         u8 bit;
 383         u32 data;
 384
 385         /*
 386          * The first 16 pins of rk3188_bank0 are always gpios and do not have
 387          * a mux register at all.
 388          */
 389         if (bank->bank_type == RK3188_BANK0 && pin < 16) {
 390                 if (mux != RK_FUNC_GPIO) {
 391                         dev_err(info->dev,
 392                                 "pin %d only supports a gpio mux\n", pin);
 393                         return -ENOTSUPP;
 394                 } else {
 395                         return 0;
 396                 }
 397         }
 398
 399         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 400                                                 bank->bank_num, pin, mux);
 401
 402         /* get basic quadrupel of mux registers and the correct reg inside */
 403         reg = info->ctrl->mux_offset;
 404         reg += bank->bank_num * 0x10;
 405         reg += (pin / 8) * 4;
 406         bit = (pin % 8) * 2;
 407
 408         spin_lock_irqsave(&bank->slock, flags);
 409
 410         data = (3 << (bit + 16));
 411         data |= (mux & 3) << bit;
 412         ret = regmap_write(info->regmap_base, reg, data);
 413
 414         spin_unlock_irqrestore(&bank->slock, flags);
 415
 416         return ret;
 417 }
 418
 419 #define RK2928_PULL_OFFSET              0x118
 420 #define RK2928_PULL_PINS_PER_REG        16
 421 #define RK2928_PULL_BANK_STRIDE         8
 422
 423 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 424                                     int pin_num, struct regmap **regmap,
 425                                     int *reg, u8 *bit)
 426 {
 427         struct rockchip_pinctrl *info = bank->drvdata;
 428
 429         *regmap = info->regmap_base;
 430         *reg = RK2928_PULL_OFFSET;
 431         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 432         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 433
 434         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 435 };
 436
 437 #define RK3188_PULL_OFFSET              0x164
 438 #define RK3188_PULL_BITS_PER_PIN        2
 439 #define RK3188_PULL_PINS_PER_REG        8
 440 #define RK3188_PULL_BANK_STRIDE         16
 441
 442 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 443                                     int pin_num, struct regmap **regmap,
 444                                     int *reg, u8 *bit)
 445 {
 446         struct rockchip_pinctrl *info = bank->drvdata;
 447
 448         /* The first 12 pins of the first bank are located elsewhere */
 449         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 450                 *regmap = bank->regmap_pull;
 451                 *reg = 0;
 452                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 453                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 454                 *bit *= RK3188_PULL_BITS_PER_PIN;
 455         } else {
 456                 *regmap = info->regmap_pull ? info->regmap_pull
 457                                             : info->regmap_base;
 458                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 459
 460                 /* correct the offset, as it is the 2nd pull register */
 461                 *reg -= 4;
 462                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 463                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 464
 465                 /*
 466                  * The bits in these registers have an inverse ordering
 467                  * with the lowest pin being in bits 15:14 and the highest
 468                  * pin in bits 1:0
 469                  */
 470                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 471                 *bit *= RK3188_PULL_BITS_PER_PIN;
 472         }
 473 }
 474
 475 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 476 {
 477         struct rockchip_pinctrl *info = bank->drvdata;
 478         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 479         struct regmap *regmap;
 480         int reg, ret;
 481         u8 bit;
 482         u32 data;
 483
 484         /* rk3066b does support any pulls */
 485         if (ctrl->type == RK3066B)
 486                 return PIN_CONFIG_BIAS_DISABLE;
 487
 488         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 489
 490         ret = regmap_read(regmap, reg, &data);
 491         if (ret)
 492                 return ret;
 493
 494         switch (ctrl->type) {
 495         case RK2928:
 496                 return !(data & BIT(bit))
 497                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 498                                 : PIN_CONFIG_BIAS_DISABLE;
 499         case RK3188:
 500                 data >>= bit;
 501                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 502
 503                 switch (data) {
 504                 case 0:
 505                         return PIN_CONFIG_BIAS_DISABLE;
 506                 case 1:
 507                         return PIN_CONFIG_BIAS_PULL_UP;
 508                 case 2:
 509                         return PIN_CONFIG_BIAS_PULL_DOWN;
 510                 case 3:
 511                         return PIN_CONFIG_BIAS_BUS_HOLD;
 512                 }
 513
 514                 dev_err(info->dev, "unknown pull setting\n");
 515                 return -EIO;
 516         default:
 517                 dev_err(info->dev, "unsupported pinctrl type\n");
 518                 return -EINVAL;
 519         };
 520 }
 521
 522 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 523                                         int pin_num, int pull)
 524 {
 525         struct rockchip_pinctrl *info = bank->drvdata;
 526         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 527         struct regmap *regmap;
 528         int reg, ret;
 529         unsigned long flags;
 530         u8 bit;
 531         u32 data;
 532
 533         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 534                  bank->bank_num, pin_num, pull);
 535
 536         /* rk3066b does support any pulls */
 537         if (ctrl->type == RK3066B)
 538                 return pull ? -EINVAL : 0;
 539
 540         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 541
 542         switch (ctrl->type) {
 543         case RK2928:
 544                 spin_lock_irqsave(&bank->slock, flags);
 545
 546                 data = BIT(bit + 16);
 547                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 548                         data |= BIT(bit);
 549                 ret = regmap_write(regmap, reg, data);
 550
 551                 spin_unlock_irqrestore(&bank->slock, flags);
 552                 break;
 553         case RK3188:
 554                 spin_lock_irqsave(&bank->slock, flags);
 555
 556                 /* enable the write to the equivalent lower bits */
 557                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 558
 559                 switch (pull) {
 560                 case PIN_CONFIG_BIAS_DISABLE:
 561                         break;
 562                 case PIN_CONFIG_BIAS_PULL_UP:
 563                         data |= (1 << bit);
 564                         break;
 565                 case PIN_CONFIG_BIAS_PULL_DOWN:
 566                         data |= (2 << bit);
 567                         break;
 568                 case PIN_CONFIG_BIAS_BUS_HOLD:
 569                         data |= (3 << bit);
 570                         break;
 571                 default:
 572                         spin_unlock_irqrestore(&bank->slock, flags);
 573                         dev_err(info->dev, "unsupported pull setting %d\n",
 574                                 pull);
 575                         return -EINVAL;
 576                 }
 577
 578                 ret = regmap_write(regmap, reg, data);
 579
 580                 spin_unlock_irqrestore(&bank->slock, flags);
 581                 break;
 582         default:
 583                 dev_err(info->dev, "unsupported pinctrl type\n");
 584                 return -EINVAL;
 585         }
 586
 587         return ret;
 588 }
 589
 590 /*
 591  * Pinmux_ops handling
 592  */
 593
 594 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 595 {
 596         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 597
 598         return info->nfunctions;
 599 }
 600
 601 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 602                                           unsigned selector)
 603 {
 604         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 605
 606         return info->functions[selector].name;
 607 }
 608
 609 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 610                                 unsigned selector, const char * const **groups,
 611                                 unsigned * const num_groups)
 612 {
 613         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 614
 615         *groups = info->functions[selector].groups;
 616         *num_groups = info->functions[selector].ngroups;
 617
 618         return 0;
 619 }
 620
 621 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 622                                                             unsigned group)
 623 {
 624         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 625         const unsigned int *pins = info->groups[group].pins;
 626         const struct rockchip_pin_config *data = info->groups[group].data;
 627         struct rockchip_pin_bank *bank;
 628         int cnt, ret = 0;
 629
 630         dev_dbg(info->dev, "enable function %s group %s\n",
 631                 info->functions[selector].name, info->groups[group].name);
 632
 633         /*
 634          * for each pin in the pin group selected, program the correspoding pin
 635          * pin function number in the config register.
 636          */
 637         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 638                 bank = pin_to_bank(info, pins[cnt]);
 639                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 640                                        data[cnt].func);
 641                 if (ret)
 642                         break;
 643         }
 644
 645         if (ret) {
 646                 /* revert the already done pin settings */
 647                 for (cnt--; cnt >= 0; cnt--)
 648                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 649
 650                 return ret;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 657                                         unsigned selector, unsigned group)
 658 {
 659         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 660         const unsigned int *pins = info->groups[group].pins;
 661         struct rockchip_pin_bank *bank;
 662         int cnt;
 663
 664         dev_dbg(info->dev, "disable function %s group %s\n",
 665                 info->functions[selector].name, info->groups[group].name);
 666
 667         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 668                 bank = pin_to_bank(info, pins[cnt]);
 669                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 670         }
 671 }
 672
 673 /*
 674  * The calls to gpio_direction_output() and gpio_direction_input()
 675  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 676  * function called from the gpiolib interface).
 677  */
 678 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 679                                               struct pinctrl_gpio_range *range,
 680                                               unsigned offset, bool input)
 681 {
 682         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 683         struct rockchip_pin_bank *bank;
 684         struct gpio_chip *chip;
 685         int pin, ret;
 686         u32 data;
 687
 688         chip = range->gc;
 689         bank = gc_to_pin_bank(chip);
 690         pin = offset - chip->base;
 691
 692         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 693                  offset, range->name, pin, input ? "input" : "output");
 694
 695         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 696         if (ret < 0)
 697                 return ret;
 698
 699         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 700         /* set bit to 1 for output, 0 for input */
 701         if (!input)
 702                 data |= BIT(pin);
 703         else
 704                 data &= ~BIT(pin);
 705         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 706
 707         return 0;
 708 }
 709
 710 static const struct pinmux_ops rockchip_pmx_ops = {
 711         .get_functions_count    = rockchip_pmx_get_funcs_count,
 712         .get_function_name      = rockchip_pmx_get_func_name,
 713         .get_function_groups    = rockchip_pmx_get_groups,
 714         .enable                 = rockchip_pmx_enable,
 715         .disable                = rockchip_pmx_disable,
 716         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 717 };
 718
 719 /*
 720  * Pinconf_ops handling
 721  */
 722
 723 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 724                                         enum pin_config_param pull)
 725 {
 726         switch (ctrl->type) {
 727         case RK2928:
 728                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 729                                         pull == PIN_CONFIG_BIAS_DISABLE);
 730         case RK3066B:
 731                 return pull ? false : true;
 732         case RK3188:
 733                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 734         }
 735
 736         return false;
 737 }
 738
 739 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 740                                           unsigned offset, int value);
 741 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 742
 743 /* set the pin config settings for a specified pin */
 744 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 745                                 unsigned long *configs, unsigned num_configs)
 746 {
 747         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 748         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 749         enum pin_config_param param;
 750         u16 arg;
 751         int i;
 752         int rc;
 753
 754         for (i = 0; i < num_configs; i++) {
 755                 param = pinconf_to_config_param(configs[i]);
 756                 arg = pinconf_to_config_argument(configs[i]);
 757
 758                 switch (param) {
 759                 case PIN_CONFIG_BIAS_DISABLE:
 760                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 761                                 param);
 762                         if (rc)
 763                                 return rc;
 764                         break;
 765                 case PIN_CONFIG_BIAS_PULL_UP:
 766                 case PIN_CONFIG_BIAS_PULL_DOWN:
 767                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 768                 case PIN_CONFIG_BIAS_BUS_HOLD:
 769                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 770                                 return -ENOTSUPP;
 771
 772                         if (!arg)
 773                                 return -EINVAL;
 774
 775                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 776                                 param);
 777                         if (rc)
 778                                 return rc;
 779                         break;
 780                 case PIN_CONFIG_OUTPUT:
 781                         rc = rockchip_gpio_direction_output(&bank->gpio_chip,
 782                                                             pin - bank->pin_base,
 783                                                             arg);
 784                         if (rc)
 785                                 return rc;
 786                         break;
 787                 default:
 788                         return -ENOTSUPP;
 789                         break;
 790                 }
 791         } /* for each config */
 792
 793         return 0;
 794 }
 795
 796 /* get the pin config settings for a specified pin */
 797 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 798                                                         unsigned long *config)
 799 {
 800         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 801         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 802         enum pin_config_param param = pinconf_to_config_param(*config);
 803         u16 arg;
 804         int rc;
 805
 806         switch (param) {
 807         case PIN_CONFIG_BIAS_DISABLE:
 808                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 809                         return -EINVAL;
 810
 811                 arg = 0;
 812                 break;
 813         case PIN_CONFIG_BIAS_PULL_UP:
 814         case PIN_CONFIG_BIAS_PULL_DOWN:
 815         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 816         case PIN_CONFIG_BIAS_BUS_HOLD:
 817                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 818                         return -ENOTSUPP;
 819
 820                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 821                         return -EINVAL;
 822
 823                 arg = 1;
 824                 break;
 825         case PIN_CONFIG_OUTPUT:
 826                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
 827                 if (rc != RK_FUNC_GPIO)
 828                         return -EINVAL;
 829
 830                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
 831                 if (rc < 0)
 832                         return rc;
 833
 834                 arg = rc ? 1 : 0;
 835                 break;
 836         default:
 837                 return -ENOTSUPP;
 838                 break;
 839         }
 840
 841         *config = pinconf_to_config_packed(param, arg);
 842
 843         return 0;
 844 }
 845
 846 static const struct pinconf_ops rockchip_pinconf_ops = {
 847         .pin_config_get                 = rockchip_pinconf_get,
 848         .pin_config_set                 = rockchip_pinconf_set,
 849 };
 850
 851 static const struct of_device_id rockchip_bank_match[] = {
 852         { .compatible = "rockchip,gpio-bank" },
 853         { .compatible = "rockchip,rk3188-gpio-bank0" },
 854         {},
 855 };
 856
 857 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 858                                                 struct device_node *np)
 859 {
 860         struct device_node *child;
 861
 862         for_each_child_of_node(np, child) {
 863                 if (of_match_node(rockchip_bank_match, child))
 864                         continue;
 865
 866                 info->nfunctions++;
 867                 info->ngroups += of_get_child_count(child);
 868         }
 869 }
 870
 871 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 872                                               struct rockchip_pin_group *grp,
 873                                               struct rockchip_pinctrl *info,
 874                                               u32 index)
 875 {
 876         struct rockchip_pin_bank *bank;
 877         int size;
 878         const __be32 *list;
 879         int num;
 880         int i, j;
 881         int ret;
 882
 883         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 884
 885         /* Initialise group */
 886         grp->name = np->name;
 887
 888         /*
 889          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 890          * do sanity check and calculate pins number
 891          */
 892         list = of_get_property(np, "rockchip,pins", &size);
 893         /* we do not check return since it's safe node passed down */
 894         size /= sizeof(*list);
 895         if (!size || size % 4) {
 896                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 897                 return -EINVAL;
 898         }
 899
 900         grp->npins = size / 4;
 901
 902         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 903                                                 GFP_KERNEL);
 904         grp->data = devm_kzalloc(info->dev, grp->npins *
 905                                           sizeof(struct rockchip_pin_config),
 906                                         GFP_KERNEL);
 907         if (!grp->pins || !grp->data)
 908                 return -ENOMEM;
 909
 910         for (i = 0, j = 0; i < size; i += 4, j++) {
 911                 const __be32 *phandle;
 912                 struct device_node *np_config;
 913
 914                 num = be32_to_cpu(*list++);
 915                 bank = bank_num_to_bank(info, num);
 916                 if (IS_ERR(bank))
 917                         return PTR_ERR(bank);
 918
 919                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 920                 grp->data[j].func = be32_to_cpu(*list++);
 921
 922                 phandle = list++;
 923                 if (!phandle)
 924                         return -EINVAL;
 925
 926                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 927                 ret = pinconf_generic_parse_dt_config(np_config,
 928                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 929                 if (ret)
 930                         return ret;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 937                                                 struct rockchip_pinctrl *info,
 938                                                 u32 index)
 939 {
 940         struct device_node *child;
 941         struct rockchip_pmx_func *func;
 942         struct rockchip_pin_group *grp;
 943         int ret;
 944         static u32 grp_index;
 945         u32 i = 0;
 946
 947         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 948
 949         func = &info->functions[index];
 950
 951         /* Initialise function */
 952         func->name = np->name;
 953         func->ngroups = of_get_child_count(np);
 954         if (func->ngroups <= 0)
 955                 return 0;
 956
 957         func->groups = devm_kzalloc(info->dev,
 958                         func->ngroups * sizeof(char *), GFP_KERNEL);
 959         if (!func->groups)
 960                 return -ENOMEM;
 961
 962         for_each_child_of_node(np, child) {
 963                 func->groups[i] = child->name;
 964                 grp = &info->groups[grp_index++];
 965                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 966                 if (ret)
 967                         return ret;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 974                                               struct rockchip_pinctrl *info)
 975 {
 976         struct device *dev = &pdev->dev;
 977         struct device_node *np = dev->of_node;
 978         struct device_node *child;
 979         int ret;
 980         int i;
 981
 982         rockchip_pinctrl_child_count(info, np);
 983
 984         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 985         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 986
 987         info->functions = devm_kzalloc(dev, info->nfunctions *
 988                                               sizeof(struct rockchip_pmx_func),
 989                                               GFP_KERNEL);
 990         if (!info->functions) {
 991                 dev_err(dev, "failed to allocate memory for function list\n");
 992                 return -EINVAL;
 993         }
 994
 995         info->groups = devm_kzalloc(dev, info->ngroups *
 996                                             sizeof(struct rockchip_pin_group),
 997                                             GFP_KERNEL);
 998         if (!info->groups) {
 999                 dev_err(dev, "failed allocate memory for ping group list\n");
1000                 return -EINVAL;
1001         }
1002
1003         i = 0;
1004
1005         for_each_child_of_node(np, child) {
1006                 if (of_match_node(rockchip_bank_match, child))
1007                         continue;
1008
1009                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1010                 if (ret) {
1011                         dev_err(&pdev->dev, "failed to parse function\n");
1012                         return ret;
1013                 }
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int rockchip_pinctrl_register(struct platform_device *pdev,
1020                                         struct rockchip_pinctrl *info)
1021 {
1022         struct pinctrl_desc *ctrldesc = &info->pctl;
1023         struct pinctrl_pin_desc *pindesc, *pdesc;
1024         struct rockchip_pin_bank *pin_bank;
1025         int pin, bank, ret;
1026         int k;
1027
1028         ctrldesc->name = "rockchip-pinctrl";
1029         ctrldesc->owner = THIS_MODULE;
1030         ctrldesc->pctlops = &rockchip_pctrl_ops;
1031         ctrldesc->pmxops = &rockchip_pmx_ops;
1032         ctrldesc->confops = &rockchip_pinconf_ops;
1033
1034         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1035                         info->ctrl->nr_pins, GFP_KERNEL);
1036         if (!pindesc) {
1037                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1038                 return -ENOMEM;
1039         }
1040         ctrldesc->pins = pindesc;
1041         ctrldesc->npins = info->ctrl->nr_pins;
1042
1043         pdesc = pindesc;
1044         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1045                 pin_bank = &info->ctrl->pin_banks[bank];
1046                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1047                         pdesc->number = k;
1048                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1049                                                 pin_bank->name, pin);
1050                         pdesc++;
1051                 }
1052         }
1053
1054         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1055         if (!info->pctl_dev) {
1056                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1057                 return -EINVAL;
1058         }
1059
1060         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1061                 pin_bank = &info->ctrl->pin_banks[bank];
1062                 pin_bank->grange.name = pin_bank->name;
1063                 pin_bank->grange.id = bank;
1064                 pin_bank->grange.pin_base = pin_bank->pin_base;
1065                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1066                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1067                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1068                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1069         }
1070
1071         ret = rockchip_pinctrl_parse_dt(pdev, info);
1072         if (ret) {
1073                 pinctrl_unregister(info->pctl_dev);
1074                 return ret;
1075         }
1076
1077         return 0;
1078 }
1079
1080 /*
1081  * GPIO handling
1082  */
1083
1084 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1085 {
1086         return pinctrl_request_gpio(chip->base + offset);
1087 }
1088
1089 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1090 {
1091         pinctrl_free_gpio(chip->base + offset);
1092 }
1093
1094 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1095 {
1096         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1097         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1098         unsigned long flags;
1099         u32 data;
1100
1101         spin_lock_irqsave(&bank->slock, flags);
1102
1103         data = readl(reg);
1104         data &= ~BIT(offset);
1105         if (value)
1106                 data |= BIT(offset);
1107         writel(data, reg);
1108
1109         spin_unlock_irqrestore(&bank->slock, flags);
1110 }
1111
1112 /*
1113  * Returns the level of the pin for input direction and setting of the DR
1114  * register for output gpios.
1115  */
1116 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1117 {
1118         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1119         u32 data;
1120
1121         data = readl(bank->reg_base + GPIO_EXT_PORT);
1122         data >>= offset;
1123         data &= 1;
1124         return data;
1125 }
1126
1127 /*
1128  * gpiolib gpio_direction_input callback function. The setting of the pin
1129  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1130  * interface.
1131  */
1132 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1133 {
1134         return pinctrl_gpio_direction_input(gc->base + offset);
1135 }
1136
1137 /*
1138  * gpiolib gpio_direction_output callback function. The setting of the pin
1139  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1140  * interface.
1141  */
1142 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1143                                           unsigned offset, int value)
1144 {
1145         rockchip_gpio_set(gc, offset, value);
1146         return pinctrl_gpio_direction_output(gc->base + offset);
1147 }
1148
1149 /*
1150  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1151  * and a virtual IRQ, if not already present.
1152  */
1153 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1154 {
1155         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1156         unsigned int virq;
1157
1158         if (!bank->domain)
1159                 return -ENXIO;
1160
1161         virq = irq_create_mapping(bank->domain, offset);
1162
1163         return (virq) ? : -ENXIO;
1164 }
1165
1166 static const struct gpio_chip rockchip_gpiolib_chip = {
1167         .request = rockchip_gpio_request,
1168         .free = rockchip_gpio_free,
1169         .set = rockchip_gpio_set,
1170         .get = rockchip_gpio_get,
1171         .direction_input = rockchip_gpio_direction_input,
1172         .direction_output = rockchip_gpio_direction_output,
1173         .to_irq = rockchip_gpio_to_irq,
1174         .owner = THIS_MODULE,
1175 };
1176
1177 /*
1178  * Interrupt handling
1179  */
1180
1181 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1182 {
1183         struct irq_chip *chip = irq_get_chip(irq);
1184         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1185         u32 polarity = 0, data = 0;
1186         u32 pend;
1187         bool edge_changed = false;
1188
1189         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1190
1191         chained_irq_enter(chip, desc);
1192
1193         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1194
1195         if (bank->toggle_edge_mode) {
1196                 polarity = readl_relaxed(bank->reg_base +
1197                                          GPIO_INT_POLARITY);
1198                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1199         }
1200
1201         while (pend) {
1202                 unsigned int virq;
1203
1204                 irq = __ffs(pend);
1205                 pend &= ~BIT(irq);
1206                 virq = irq_linear_revmap(bank->domain, irq);
1207
1208                 if (!virq) {
1209                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1210                         continue;
1211                 }
1212
1213                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1214
1215                 /*
1216                  * Triggering IRQ on both rising and falling edge
1217                  * needs manual intervention.
1218                  */
1219                 if (bank->toggle_edge_mode & BIT(irq)) {
1220                         if (data & BIT(irq))
1221                                 polarity &= ~BIT(irq);
1222                         else
1223                                 polarity |= BIT(irq);
1224
1225                         edge_changed = true;
1226                 }
1227
1228                 generic_handle_irq(virq);
1229         }
1230
1231         if (bank->toggle_edge_mode && edge_changed) {
1232                 /* Interrupt params should only be set with ints disabled */
1233                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1234                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1235                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1236                 writel(data, bank->reg_base + GPIO_INTEN);
1237         }
1238
1239         chained_irq_exit(chip, desc);
1240 }
1241
1242 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1243 {
1244         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1245         struct rockchip_pin_bank *bank = gc->private;
1246         u32 mask = BIT(d->hwirq);
1247         u32 polarity;
1248         u32 level;
1249         u32 data;
1250         int ret;
1251
1252         /* make sure the pin is configured as gpio input */
1253         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1254         if (ret < 0)
1255                 return ret;
1256
1257         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1258         data &= ~mask;
1259         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1260
1261         if (type & IRQ_TYPE_EDGE_BOTH)
1262                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1263         else
1264                 __irq_set_handler_locked(d->irq, handle_level_irq);
1265
1266         irq_gc_lock(gc);
1267
1268         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1269         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1270
1271         switch (type) {
1272         case IRQ_TYPE_EDGE_BOTH:
1273                 bank->toggle_edge_mode |= mask;
1274                 level |= mask;
1275
1276                 /*
1277                  * Determine gpio state. If 1 next interrupt should be falling
1278                  * otherwise rising.
1279                  */
1280                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1281                 if (data & mask)
1282                         polarity &= ~mask;
1283                 else
1284                         polarity |= mask;
1285                 break;
1286         case IRQ_TYPE_EDGE_RISING:
1287                 bank->toggle_edge_mode &= ~mask;
1288                 level |= mask;
1289                 polarity |= mask;
1290                 break;
1291         case IRQ_TYPE_EDGE_FALLING:
1292                 bank->toggle_edge_mode &= ~mask;
1293                 level |= mask;
1294                 polarity &= ~mask;
1295                 break;
1296         case IRQ_TYPE_LEVEL_HIGH:
1297                 bank->toggle_edge_mode &= ~mask;
1298                 level &= ~mask;
1299                 polarity |= mask;
1300                 break;
1301         case IRQ_TYPE_LEVEL_LOW:
1302                 bank->toggle_edge_mode &= ~mask;
1303                 level &= ~mask;
1304                 polarity &= ~mask;
1305                 break;
1306         default:
1307                 irq_gc_unlock(gc);
1308                 return -EINVAL;
1309         }
1310
1311         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1312         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1313
1314         irq_gc_unlock(gc);
1315
1316         return 0;
1317 }
1318
1319 static int rockchip_interrupts_register(struct platform_device *pdev,
1320                                                 struct rockchip_pinctrl *info)
1321 {
1322         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1323         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1324         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1325         struct irq_chip_generic *gc;
1326         int ret;
1327         int i;
1328
1329         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1330                 if (!bank->valid) {
1331                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1332                                  bank->name);
1333                         continue;
1334                 }
1335
1336                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1337                                                 &irq_generic_chip_ops, NULL);
1338                 if (!bank->domain) {
1339                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1340                                  bank->name);
1341                         continue;
1342                 }
1343
1344                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1345                                          "rockchip_gpio_irq", handle_level_irq,
1346                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1347                 if (ret) {
1348                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1349                                 bank->name);
1350                         irq_domain_remove(bank->domain);
1351                         continue;
1352                 }
1353
1354                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1355                 gc->reg_base = bank->reg_base;
1356                 gc->private = bank;
1357                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1358                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1359                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1360                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1361                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1362                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1363                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1364
1365                 irq_set_handler_data(bank->irq, bank);
1366                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int rockchip_gpiolib_register(struct platform_device *pdev,
1373                                                 struct rockchip_pinctrl *info)
1374 {
1375         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1376         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1377         struct gpio_chip *gc;
1378         int ret;
1379         int i;
1380
1381         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1382                 if (!bank->valid) {
1383                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1384                                  bank->name);
1385                         continue;
1386                 }
1387
1388                 bank->gpio_chip = rockchip_gpiolib_chip;
1389
1390                 gc = &bank->gpio_chip;
1391                 gc->base = bank->pin_base;
1392                 gc->ngpio = bank->nr_pins;
1393                 gc->dev = &pdev->dev;
1394                 gc->of_node = bank->of_node;
1395                 gc->label = bank->name;
1396
1397                 ret = gpiochip_add(gc);
1398                 if (ret) {
1399                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1400                                                         gc->label, ret);
1401                         goto fail;
1402                 }
1403         }
1404
1405         rockchip_interrupts_register(pdev, info);
1406
1407         return 0;
1408
1409 fail:
1410         for (--i, --bank; i >= 0; --i, --bank) {
1411                 if (!bank->valid)
1412                         continue;
1413
1414                 if (gpiochip_remove(&bank->gpio_chip))
1415                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1416                                                         bank->gpio_chip.label);
1417         }
1418         return ret;
1419 }
1420
1421 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1422                                                 struct rockchip_pinctrl *info)
1423 {
1424         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1425         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1426         int ret = 0;
1427         int i;
1428
1429         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1430                 if (!bank->valid)
1431                         continue;
1432
1433                 ret = gpiochip_remove(&bank->gpio_chip);
1434         }
1435
1436         if (ret)
1437                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1438
1439         return ret;
1440 }
1441
1442 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1443                                   struct rockchip_pinctrl *info)
1444 {
1445         struct resource res;
1446         void __iomem *base;
1447
1448         if (of_address_to_resource(bank->of_node, 0, &res)) {
1449                 dev_err(info->dev, "cannot find IO resource for bank\n");
1450                 return -ENOENT;
1451         }
1452
1453         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1454         if (IS_ERR(bank->reg_base))
1455                 return PTR_ERR(bank->reg_base);
1456
1457         /*
1458          * special case, where parts of the pull setting-registers are
1459          * part of the PMU register space
1460          */
1461         if (of_device_is_compatible(bank->of_node,
1462                                     "rockchip,rk3188-gpio-bank0")) {
1463
1464                 bank->bank_type = RK3188_BANK0;
1465
1466                 if (of_address_to_resource(bank->of_node, 1, &res)) {
1467                         dev_err(info->dev, "cannot find IO resource for bank\n");
1468                         return -ENOENT;
1469                 }
1470
1471                 base = devm_ioremap_resource(info->dev, &res);
1472                 if (IS_ERR(base))
1473                         return PTR_ERR(base);
1474                 rockchip_regmap_config.max_register = resource_size(&res) - 4;
1475                 rockchip_regmap_config.name = "rockchip,rk3188-gpio-bank0-pull";
1476                 bank->regmap_pull = devm_regmap_init_mmio(info->dev, base,
1477                                                   &rockchip_regmap_config);
1478
1479         } else {
1480                 bank->bank_type = COMMON_BANK;
1481         }
1482
1483         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1484
1485         bank->clk = of_clk_get(bank->of_node, 0);
1486         if (IS_ERR(bank->clk))
1487                 return PTR_ERR(bank->clk);
1488
1489         return clk_prepare_enable(bank->clk);
1490 }
1491
1492 static const struct of_device_id rockchip_pinctrl_dt_match[];
1493
1494 /* retrieve the soc specific data */
1495 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1496                                                 struct rockchip_pinctrl *d,
1497                                                 struct platform_device *pdev)
1498 {
1499         const struct of_device_id *match;
1500         struct device_node *node = pdev->dev.of_node;
1501         struct device_node *np;
1502         struct rockchip_pin_ctrl *ctrl;
1503         struct rockchip_pin_bank *bank;
1504         int i;
1505
1506         match = of_match_node(rockchip_pinctrl_dt_match, node);
1507         ctrl = (struct rockchip_pin_ctrl *)match->data;
1508
1509         for_each_child_of_node(node, np) {
1510                 if (!of_find_property(np, "gpio-controller", NULL))
1511                         continue;
1512
1513                 bank = ctrl->pin_banks;
1514                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1515                         if (!strcmp(bank->name, np->name)) {
1516                                 bank->of_node = np;
1517
1518                                 if (!rockchip_get_bank_data(bank, d))
1519                                         bank->valid = true;
1520
1521                                 break;
1522                         }
1523                 }
1524         }
1525
1526         bank = ctrl->pin_banks;
1527         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1528                 spin_lock_init(&bank->slock);
1529                 bank->drvdata = d;
1530                 bank->pin_base = ctrl->nr_pins;
1531                 ctrl->nr_pins += bank->nr_pins;
1532         }
1533
1534         return ctrl;
1535 }
1536
1537 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1538 {
1539         struct rockchip_pinctrl *info;
1540         struct device *dev = &pdev->dev;
1541         struct rockchip_pin_ctrl *ctrl;
1542         struct resource *res;
1543         void __iomem *base;
1544         int ret;
1545
1546         if (!dev->of_node) {
1547                 dev_err(dev, "device tree node not found\n");
1548                 return -ENODEV;
1549         }
1550
1551         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1552         if (!info)
1553                 return -ENOMEM;
1554
1555         info->dev = dev;
1556
1557         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1558         if (!ctrl) {
1559                 dev_err(dev, "driver data not available\n");
1560                 return -EINVAL;
1561         }
1562         info->ctrl = ctrl;
1563
1564         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1565         base = devm_ioremap_resource(&pdev->dev, res);
1566         if (IS_ERR(base))
1567                 return PTR_ERR(base);
1568
1569         rockchip_regmap_config.max_register = resource_size(res) - 4;
1570         rockchip_regmap_config.name = "rockchip,pinctrl";
1571         info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1572                                                   &rockchip_regmap_config);
1573
1574         /* to check for the old dt-bindings */
1575         info->reg_size = resource_size(res);
1576
1577         /* Honor the old binding, with pull registers as 2nd resource */
1578         if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1579                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1580                 base = devm_ioremap_resource(&pdev->dev, res);
1581                 if (IS_ERR(base))
1582                         return PTR_ERR(base);
1583
1584                 rockchip_regmap_config.max_register = resource_size(res) - 4;
1585                 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1586                 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, base,
1587                                                   &rockchip_regmap_config);
1588         }
1589
1590         ret = rockchip_gpiolib_register(pdev, info);
1591         if (ret)
1592                 return ret;
1593
1594         ret = rockchip_pinctrl_register(pdev, info);
1595         if (ret) {
1596                 rockchip_gpiolib_unregister(pdev, info);
1597                 return ret;
1598         }
1599
1600         platform_set_drvdata(pdev, info);
1601
1602         return 0;
1603 }
1604
1605 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1606         PIN_BANK(0, 32, "gpio0"),
1607         PIN_BANK(1, 32, "gpio1"),
1608         PIN_BANK(2, 32, "gpio2"),
1609         PIN_BANK(3, 32, "gpio3"),
1610 };
1611
1612 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1613                 .pin_banks              = rk2928_pin_banks,
1614                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1615                 .label                  = "RK2928-GPIO",
1616                 .type                   = RK2928,
1617                 .mux_offset             = 0xa8,
1618                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1619 };
1620
1621 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1622         PIN_BANK(0, 32, "gpio0"),
1623         PIN_BANK(1, 32, "gpio1"),
1624         PIN_BANK(2, 32, "gpio2"),
1625         PIN_BANK(3, 32, "gpio3"),
1626         PIN_BANK(4, 32, "gpio4"),
1627         PIN_BANK(6, 16, "gpio6"),
1628 };
1629
1630 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1631                 .pin_banks              = rk3066a_pin_banks,
1632                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1633                 .label                  = "RK3066a-GPIO",
1634                 .type                   = RK2928,
1635                 .mux_offset             = 0xa8,
1636                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1637 };
1638
1639 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1640         PIN_BANK(0, 32, "gpio0"),
1641         PIN_BANK(1, 32, "gpio1"),
1642         PIN_BANK(2, 32, "gpio2"),
1643         PIN_BANK(3, 32, "gpio3"),
1644 };
1645
1646 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1647                 .pin_banks      = rk3066b_pin_banks,
1648                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1649                 .label          = "RK3066b-GPIO",
1650                 .type           = RK3066B,
1651                 .mux_offset     = 0x60,
1652 };
1653
1654 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1655         PIN_BANK(0, 32, "gpio0"),
1656         PIN_BANK(1, 32, "gpio1"),
1657         PIN_BANK(2, 32, "gpio2"),
1658         PIN_BANK(3, 32, "gpio3"),
1659 };
1660
1661 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1662                 .pin_banks              = rk3188_pin_banks,
1663                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1664                 .label                  = "RK3188-GPIO",
1665                 .type                   = RK3188,
1666                 .mux_offset             = 0x60,
1667                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1668 };
1669
1670 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1671         { .compatible = "rockchip,rk2928-pinctrl",
1672                 .data = (void *)&rk2928_pin_ctrl },
1673         { .compatible = "rockchip,rk3066a-pinctrl",
1674                 .data = (void *)&rk3066a_pin_ctrl },
1675         { .compatible = "rockchip,rk3066b-pinctrl",
1676                 .data = (void *)&rk3066b_pin_ctrl },
1677         { .compatible = "rockchip,rk3188-pinctrl",
1678                 .data = (void *)&rk3188_pin_ctrl },
1679         {},
1680 };
1681 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1682
1683 static struct platform_driver rockchip_pinctrl_driver = {
1684         .probe          = rockchip_pinctrl_probe,
1685         .driver = {
1686                 .name   = "rockchip-pinctrl",
1687                 .owner  = THIS_MODULE,
1688                 .of_match_table = rockchip_pinctrl_dt_match,
1689         },
1690 };
1691
1692 static int __init rockchip_pinctrl_drv_register(void)
1693 {
1694         return platform_driver_register(&rockchip_pinctrl_driver);
1695 }
1696 postcore_initcall(rockchip_pinctrl_drv_register);
1697
1698 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1699 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1700 MODULE_LICENSE("GPL v2");