drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK2928,
  63         RK3066B,
  64         RK3188,
  65         RK3288,
  66 };
  67
  68 /**
  69  * Encode variants of iomux registers into a type variable
  70  */
  71 #define IOMUX_GPIO_ONLY         BIT(0)
  72 #define IOMUX_WIDTH_4BIT        BIT(1)
  73 #define IOMUX_SOURCE_PMU        BIT(2)
  74 #define IOMUX_UNROUTED          BIT(3)
  75
  76 /**
  77  * @type: iomux variant using IOMUX_* constants
  78  * @offset: if initialized to -1 it will be autocalculated, by specifying
  79  *          an initial offset value the relevant source offset can be reset
  80  *          to a new value for autocalculating the following iomux registers.
  81  */
  82 struct rockchip_iomux {
  83         int                             type;
  84         int                             offset;
  85 };
  86
  87 /**
  88  * @reg_base: register base of the gpio bank
  89  * @reg_pull: optional separate register for additional pull settings
  90  * @clk: clock of the gpio bank
  91  * @irq: interrupt of the gpio bank
  92  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
  93  * @pin_base: first pin number
  94  * @nr_pins: number of pins in this bank
  95  * @name: name of the bank
  96  * @bank_num: number of the bank, to account for holes
  97  * @iomux: array describing the 4 iomux sources of the bank
  98  * @valid: are all necessary informations present
  99  * @of_node: dt node of this bank
 100  * @drvdata: common pinctrl basedata
 101  * @domain: irqdomain of the gpio bank
 102  * @gpio_chip: gpiolib chip
 103  * @grange: gpio range
 104  * @slock: spinlock for the gpio bank
 105  */
 106 struct rockchip_pin_bank {
 107         void __iomem                    *reg_base;
 108         struct regmap                   *regmap_pull;
 109         struct clk                      *clk;
 110         int                             irq;
 111         u32                             saved_masks;
 112         u32                             pin_base;
 113         u8                              nr_pins;
 114         char                            *name;
 115         u8                              bank_num;
 116         struct rockchip_iomux           iomux[4];
 117         bool                            valid;
 118         struct device_node              *of_node;
 119         struct rockchip_pinctrl         *drvdata;
 120         struct irq_domain               *domain;
 121         struct gpio_chip                gpio_chip;
 122         struct pinctrl_gpio_range       grange;
 123         spinlock_t                      slock;
 124         u32                             toggle_edge_mode;
 125 };
 126
 127 #define PIN_BANK(id, pins, label)                       \
 128         {                                               \
 129                 .bank_num       = id,                   \
 130                 .nr_pins        = pins,                 \
 131                 .name           = label,                \
 132                 .iomux          = {                     \
 133                         { .offset = -1 },               \
 134                         { .offset = -1 },               \
 135                         { .offset = -1 },               \
 136                         { .offset = -1 },               \
 137                 },                                      \
 138         }
 139
 140 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 141         {                                                               \
 142                 .bank_num       = id,                                   \
 143                 .nr_pins        = pins,                                 \
 144                 .name           = label,                                \
 145                 .iomux          = {                                     \
 146                         { .type = iom0, .offset = -1 },                 \
 147                         { .type = iom1, .offset = -1 },                 \
 148                         { .type = iom2, .offset = -1 },                 \
 149                         { .type = iom3, .offset = -1 },                 \
 150                 },                                                      \
 151         }
 152
 153 /**
 154  */
 155 struct rockchip_pin_ctrl {
 156         struct rockchip_pin_bank        *pin_banks;
 157         u32                             nr_banks;
 158         u32                             nr_pins;
 159         char                            *label;
 160         enum rockchip_pinctrl_type      type;
 161         int                             grf_mux_offset;
 162         int                             pmu_mux_offset;
 163         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 164                                     int pin_num, struct regmap **regmap,
 165                                     int *reg, u8 *bit);
 166         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 167                                     int pin_num, struct regmap **regmap,
 168                                     int *reg, u8 *bit);
 169 };
 170
 171 struct rockchip_pin_config {
 172         unsigned int            func;
 173         unsigned long           *configs;
 174         unsigned int            nconfigs;
 175 };
 176
 177 /**
 178  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 179  * @name: name of the pin group, used to lookup the group.
 180  * @pins: the pins included in this group.
 181  * @npins: number of pins included in this group.
 182  * @func: the mux function number to be programmed when selected.
 183  * @configs: the config values to be set for each pin
 184  * @nconfigs: number of configs for each pin
 185  */
 186 struct rockchip_pin_group {
 187         const char                      *name;
 188         unsigned int                    npins;
 189         unsigned int                    *pins;
 190         struct rockchip_pin_config      *data;
 191 };
 192
 193 /**
 194  * struct rockchip_pmx_func: represent a pin function.
 195  * @name: name of the pin function, used to lookup the function.
 196  * @groups: one or more names of pin groups that provide this function.
 197  * @num_groups: number of groups included in @groups.
 198  */
 199 struct rockchip_pmx_func {
 200         const char              *name;
 201         const char              **groups;
 202         u8                      ngroups;
 203 };
 204
 205 struct rockchip_pinctrl {
 206         struct regmap                   *regmap_base;
 207         int                             reg_size;
 208         struct regmap                   *regmap_pull;
 209         struct regmap                   *regmap_pmu;
 210         struct device                   *dev;
 211         struct rockchip_pin_ctrl        *ctrl;
 212         struct pinctrl_desc             pctl;
 213         struct pinctrl_dev              *pctl_dev;
 214         struct rockchip_pin_group       *groups;
 215         unsigned int                    ngroups;
 216         struct rockchip_pmx_func        *functions;
 217         unsigned int                    nfunctions;
 218 };
 219
 220 static struct regmap_config rockchip_regmap_config = {
 221         .reg_bits = 32,
 222         .val_bits = 32,
 223         .reg_stride = 4,
 224 };
 225
 226 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 227 {
 228         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 229 }
 230
 231 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 232                                         const struct rockchip_pinctrl *info,
 233                                         const char *name)
 234 {
 235         int i;
 236
 237         for (i = 0; i < info->ngroups; i++) {
 238                 if (!strcmp(info->groups[i].name, name))
 239                         return &info->groups[i];
 240         }
 241
 242         return NULL;
 243 }
 244
 245 /*
 246  * given a pin number that is local to a pin controller, find out the pin bank
 247  * and the register base of the pin bank.
 248  */
 249 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 250                                                                 unsigned pin)
 251 {
 252         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 253
 254         while (pin >= (b->pin_base + b->nr_pins))
 255                 b++;
 256
 257         return b;
 258 }
 259
 260 static struct rockchip_pin_bank *bank_num_to_bank(
 261                                         struct rockchip_pinctrl *info,
 262                                         unsigned num)
 263 {
 264         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 265         int i;
 266
 267         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 268                 if (b->bank_num == num)
 269                         return b;
 270         }
 271
 272         return ERR_PTR(-EINVAL);
 273 }
 274
 275 /*
 276  * Pinctrl_ops handling
 277  */
 278
 279 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 280 {
 281         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 282
 283         return info->ngroups;
 284 }
 285
 286 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 287                                                         unsigned selector)
 288 {
 289         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 290
 291         return info->groups[selector].name;
 292 }
 293
 294 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 295                                       unsigned selector, const unsigned **pins,
 296                                       unsigned *npins)
 297 {
 298         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 299
 300         if (selector >= info->ngroups)
 301                 return -EINVAL;
 302
 303         *pins = info->groups[selector].pins;
 304         *npins = info->groups[selector].npins;
 305
 306         return 0;
 307 }
 308
 309 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 310                                  struct device_node *np,
 311                                  struct pinctrl_map **map, unsigned *num_maps)
 312 {
 313         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 314         const struct rockchip_pin_group *grp;
 315         struct pinctrl_map *new_map;
 316         struct device_node *parent;
 317         int map_num = 1;
 318         int i;
 319
 320         /*
 321          * first find the group of this node and check if we need to create
 322          * config maps for pins
 323          */
 324         grp = pinctrl_name_to_group(info, np->name);
 325         if (!grp) {
 326                 dev_err(info->dev, "unable to find group for node %s\n",
 327                         np->name);
 328                 return -EINVAL;
 329         }
 330
 331         map_num += grp->npins;
 332         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 333                                                                 GFP_KERNEL);
 334         if (!new_map)
 335                 return -ENOMEM;
 336
 337         *map = new_map;
 338         *num_maps = map_num;
 339
 340         /* create mux map */
 341         parent = of_get_parent(np);
 342         if (!parent) {
 343                 devm_kfree(pctldev->dev, new_map);
 344                 return -EINVAL;
 345         }
 346         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 347         new_map[0].data.mux.function = parent->name;
 348         new_map[0].data.mux.group = np->name;
 349         of_node_put(parent);
 350
 351         /* create config map */
 352         new_map++;
 353         for (i = 0; i < grp->npins; i++) {
 354                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 355                 new_map[i].data.configs.group_or_pin =
 356                                 pin_get_name(pctldev, grp->pins[i]);
 357                 new_map[i].data.configs.configs = grp->data[i].configs;
 358                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 359         }
 360
 361         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 362                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 363
 364         return 0;
 365 }
 366
 367 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 368                                     struct pinctrl_map *map, unsigned num_maps)
 369 {
 370 }
 371
 372 static const struct pinctrl_ops rockchip_pctrl_ops = {
 373         .get_groups_count       = rockchip_get_groups_count,
 374         .get_group_name         = rockchip_get_group_name,
 375         .get_group_pins         = rockchip_get_group_pins,
 376         .dt_node_to_map         = rockchip_dt_node_to_map,
 377         .dt_free_map            = rockchip_dt_free_map,
 378 };
 379
 380 /*
 381  * Hardware access
 382  */
 383
 384 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 385 {
 386         struct rockchip_pinctrl *info = bank->drvdata;
 387         int iomux_num = (pin / 8);
 388         struct regmap *regmap;
 389         unsigned int val;
 390         int reg, ret, mask;
 391         u8 bit;
 392
 393         if (iomux_num > 3)
 394                 return -EINVAL;
 395
 396         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 397                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 398                 return -EINVAL;
 399         }
 400
 401         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 402                 return RK_FUNC_GPIO;
 403
 404         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 405                                 ? info->regmap_pmu : info->regmap_base;
 406
 407         /* get basic quadrupel of mux registers and the correct reg inside */
 408         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 409         reg = bank->iomux[iomux_num].offset;
 410         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 411                 if ((pin % 8) >= 4)
 412                         reg += 0x4;
 413                 bit = (pin % 4) * 4;
 414         } else {
 415                 bit = (pin % 8) * 2;
 416         }
 417
 418         ret = regmap_read(regmap, reg, &val);
 419         if (ret)
 420                 return ret;
 421
 422         return ((val >> bit) & mask);
 423 }
 424
 425 /*
 426  * Set a new mux function for a pin.
 427  *
 428  * The register is divided into the upper and lower 16 bit. When changing
 429  * a value, the previous register value is not read and changed. Instead
 430  * it seems the changed bits are marked in the upper 16 bit, while the
 431  * changed value gets set in the same offset in the lower 16 bit.
 432  * All pin settings seem to be 2 bit wide in both the upper and lower
 433  * parts.
 434  * @bank: pin bank to change
 435  * @pin: pin to change
 436  * @mux: new mux function to set
 437  */
 438 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 439 {
 440         struct rockchip_pinctrl *info = bank->drvdata;
 441         int iomux_num = (pin / 8);
 442         struct regmap *regmap;
 443         int reg, ret, mask;
 444         unsigned long flags;
 445         u8 bit;
 446         u32 data, rmask;
 447
 448         if (iomux_num > 3)
 449                 return -EINVAL;
 450
 451         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 452                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 453                 return -EINVAL;
 454         }
 455
 456         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 457                 if (mux != RK_FUNC_GPIO) {
 458                         dev_err(info->dev,
 459                                 "pin %d only supports a gpio mux\n", pin);
 460                         return -ENOTSUPP;
 461                 } else {
 462                         return 0;
 463                 }
 464         }
 465
 466         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 467                                                 bank->bank_num, pin, mux);
 468
 469         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 470                                 ? info->regmap_pmu : info->regmap_base;
 471
 472         /* get basic quadrupel of mux registers and the correct reg inside */
 473         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 474         reg = bank->iomux[iomux_num].offset;
 475         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 476                 if ((pin % 8) >= 4)
 477                         reg += 0x4;
 478                 bit = (pin % 4) * 4;
 479         } else {
 480                 bit = (pin % 8) * 2;
 481         }
 482
 483         spin_lock_irqsave(&bank->slock, flags);
 484
 485         data = (mask << (bit + 16));
 486         rmask = data | (data >> 16);
 487         data |= (mux & mask) << bit;
 488         ret = regmap_update_bits(regmap, reg, rmask, data);
 489
 490         spin_unlock_irqrestore(&bank->slock, flags);
 491
 492         return ret;
 493 }
 494
 495 #define RK2928_PULL_OFFSET              0x118
 496 #define RK2928_PULL_PINS_PER_REG        16
 497 #define RK2928_PULL_BANK_STRIDE         8
 498
 499 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 500                                     int pin_num, struct regmap **regmap,
 501                                     int *reg, u8 *bit)
 502 {
 503         struct rockchip_pinctrl *info = bank->drvdata;
 504
 505         *regmap = info->regmap_base;
 506         *reg = RK2928_PULL_OFFSET;
 507         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 508         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 509
 510         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 511 };
 512
 513 #define RK3188_PULL_OFFSET              0x164
 514 #define RK3188_PULL_BITS_PER_PIN        2
 515 #define RK3188_PULL_PINS_PER_REG        8
 516 #define RK3188_PULL_BANK_STRIDE         16
 517 #define RK3188_PULL_PMU_OFFSET          0x64
 518
 519 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 520                                     int pin_num, struct regmap **regmap,
 521                                     int *reg, u8 *bit)
 522 {
 523         struct rockchip_pinctrl *info = bank->drvdata;
 524
 525         /* The first 12 pins of the first bank are located elsewhere */
 526         if (bank->bank_num == 0 && pin_num < 12) {
 527                 *regmap = info->regmap_pmu ? info->regmap_pmu
 528                                            : bank->regmap_pull;
 529                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 530                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 531                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 532                 *bit *= RK3188_PULL_BITS_PER_PIN;
 533         } else {
 534                 *regmap = info->regmap_pull ? info->regmap_pull
 535                                             : info->regmap_base;
 536                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 537
 538                 /* correct the offset, as it is the 2nd pull register */
 539                 *reg -= 4;
 540                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 541                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 542
 543                 /*
 544                  * The bits in these registers have an inverse ordering
 545                  * with the lowest pin being in bits 15:14 and the highest
 546                  * pin in bits 1:0
 547                  */
 548                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 549                 *bit *= RK3188_PULL_BITS_PER_PIN;
 550         }
 551 }
 552
 553 #define RK3288_PULL_OFFSET              0x140
 554 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 555                                     int pin_num, struct regmap **regmap,
 556                                     int *reg, u8 *bit)
 557 {
 558         struct rockchip_pinctrl *info = bank->drvdata;
 559
 560         /* The first 24 pins of the first bank are located in PMU */
 561         if (bank->bank_num == 0) {
 562                 *regmap = info->regmap_pmu;
 563                 *reg = RK3188_PULL_PMU_OFFSET;
 564
 565                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 566                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 567                 *bit *= RK3188_PULL_BITS_PER_PIN;
 568         } else {
 569                 *regmap = info->regmap_base;
 570                 *reg = RK3288_PULL_OFFSET;
 571
 572                 /* correct the offset, as we're starting with the 2nd bank */
 573                 *reg -= 0x10;
 574                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 575                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 576
 577                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 578                 *bit *= RK3188_PULL_BITS_PER_PIN;
 579         }
 580 }
 581
 582 #define RK3288_DRV_PMU_OFFSET           0x70
 583 #define RK3288_DRV_GRF_OFFSET           0x1c0
 584 #define RK3288_DRV_BITS_PER_PIN         2
 585 #define RK3288_DRV_PINS_PER_REG         8
 586 #define RK3288_DRV_BANK_STRIDE          16
 587
 588 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 589                                     int pin_num, struct regmap **regmap,
 590                                     int *reg, u8 *bit)
 591 {
 592         struct rockchip_pinctrl *info = bank->drvdata;
 593
 594         /* The first 24 pins of the first bank are located in PMU */
 595         if (bank->bank_num == 0) {
 596                 *regmap = info->regmap_pmu;
 597                 *reg = RK3288_DRV_PMU_OFFSET;
 598
 599                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 600                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 601                 *bit *= RK3288_DRV_BITS_PER_PIN;
 602         } else {
 603                 *regmap = info->regmap_base;
 604                 *reg = RK3288_DRV_GRF_OFFSET;
 605
 606                 /* correct the offset, as we're starting with the 2nd bank */
 607                 *reg -= 0x10;
 608                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 609                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 610
 611                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 612                 *bit *= RK3288_DRV_BITS_PER_PIN;
 613         }
 614 }
 615
 616 static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
 617
 618 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 619                                      int pin_num)
 620 {
 621         struct rockchip_pinctrl *info = bank->drvdata;
 622         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 623         struct regmap *regmap;
 624         int reg, ret;
 625         u32 data;
 626         u8 bit;
 627
 628         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 629
 630         ret = regmap_read(regmap, reg, &data);
 631         if (ret)
 632                 return ret;
 633
 634         data >>= bit;
 635         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 636
 637         return rockchip_perpin_drv_list[data];
 638 }
 639
 640 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 641                                      int pin_num, int strength)
 642 {
 643         struct rockchip_pinctrl *info = bank->drvdata;
 644         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 645         struct regmap *regmap;
 646         unsigned long flags;
 647         int reg, ret, i;
 648         u32 data, rmask;
 649         u8 bit;
 650
 651         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 652
 653         ret = -EINVAL;
 654         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
 655                 if (rockchip_perpin_drv_list[i] == strength) {
 656                         ret = i;
 657                         break;
 658                 }
 659         }
 660
 661         if (ret < 0) {
 662                 dev_err(info->dev, "unsupported driver strength %d\n",
 663                         strength);
 664                 return ret;
 665         }
 666
 667         spin_lock_irqsave(&bank->slock, flags);
 668
 669         /* enable the write to the equivalent lower bits */
 670         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 671         rmask = data | (data >> 16);
 672         data |= (ret << bit);
 673
 674         ret = regmap_update_bits(regmap, reg, rmask, data);
 675         spin_unlock_irqrestore(&bank->slock, flags);
 676
 677         return ret;
 678 }
 679
 680 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 681 {
 682         struct rockchip_pinctrl *info = bank->drvdata;
 683         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 684         struct regmap *regmap;
 685         int reg, ret;
 686         u8 bit;
 687         u32 data;
 688
 689         /* rk3066b does support any pulls */
 690         if (ctrl->type == RK3066B)
 691                 return PIN_CONFIG_BIAS_DISABLE;
 692
 693         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 694
 695         ret = regmap_read(regmap, reg, &data);
 696         if (ret)
 697                 return ret;
 698
 699         switch (ctrl->type) {
 700         case RK2928:
 701                 return !(data & BIT(bit))
 702                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 703                                 : PIN_CONFIG_BIAS_DISABLE;
 704         case RK3188:
 705         case RK3288:
 706                 data >>= bit;
 707                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 708
 709                 switch (data) {
 710                 case 0:
 711                         return PIN_CONFIG_BIAS_DISABLE;
 712                 case 1:
 713                         return PIN_CONFIG_BIAS_PULL_UP;
 714                 case 2:
 715                         return PIN_CONFIG_BIAS_PULL_DOWN;
 716                 case 3:
 717                         return PIN_CONFIG_BIAS_BUS_HOLD;
 718                 }
 719
 720                 dev_err(info->dev, "unknown pull setting\n");
 721                 return -EIO;
 722         default:
 723                 dev_err(info->dev, "unsupported pinctrl type\n");
 724                 return -EINVAL;
 725         };
 726 }
 727
 728 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 729                                         int pin_num, int pull)
 730 {
 731         struct rockchip_pinctrl *info = bank->drvdata;
 732         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 733         struct regmap *regmap;
 734         int reg, ret;
 735         unsigned long flags;
 736         u8 bit;
 737         u32 data, rmask;
 738
 739         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 740                  bank->bank_num, pin_num, pull);
 741
 742         /* rk3066b does support any pulls */
 743         if (ctrl->type == RK3066B)
 744                 return pull ? -EINVAL : 0;
 745
 746         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 747
 748         switch (ctrl->type) {
 749         case RK2928:
 750                 spin_lock_irqsave(&bank->slock, flags);
 751
 752                 data = BIT(bit + 16);
 753                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 754                         data |= BIT(bit);
 755                 ret = regmap_write(regmap, reg, data);
 756
 757                 spin_unlock_irqrestore(&bank->slock, flags);
 758                 break;
 759         case RK3188:
 760         case RK3288:
 761                 spin_lock_irqsave(&bank->slock, flags);
 762
 763                 /* enable the write to the equivalent lower bits */
 764                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 765                 rmask = data | (data >> 16);
 766
 767                 switch (pull) {
 768                 case PIN_CONFIG_BIAS_DISABLE:
 769                         break;
 770                 case PIN_CONFIG_BIAS_PULL_UP:
 771                         data |= (1 << bit);
 772                         break;
 773                 case PIN_CONFIG_BIAS_PULL_DOWN:
 774                         data |= (2 << bit);
 775                         break;
 776                 case PIN_CONFIG_BIAS_BUS_HOLD:
 777                         data |= (3 << bit);
 778                         break;
 779                 default:
 780                         spin_unlock_irqrestore(&bank->slock, flags);
 781                         dev_err(info->dev, "unsupported pull setting %d\n",
 782                                 pull);
 783                         return -EINVAL;
 784                 }
 785
 786                 ret = regmap_update_bits(regmap, reg, rmask, data);
 787
 788                 spin_unlock_irqrestore(&bank->slock, flags);
 789                 break;
 790         default:
 791                 dev_err(info->dev, "unsupported pinctrl type\n");
 792                 return -EINVAL;
 793         }
 794
 795         return ret;
 796 }
 797
 798 /*
 799  * Pinmux_ops handling
 800  */
 801
 802 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 803 {
 804         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 805
 806         return info->nfunctions;
 807 }
 808
 809 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 810                                           unsigned selector)
 811 {
 812         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 813
 814         return info->functions[selector].name;
 815 }
 816
 817 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 818                                 unsigned selector, const char * const **groups,
 819                                 unsigned * const num_groups)
 820 {
 821         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 822
 823         *groups = info->functions[selector].groups;
 824         *num_groups = info->functions[selector].ngroups;
 825
 826         return 0;
 827 }
 828
 829 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 830                             unsigned group)
 831 {
 832         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 833         const unsigned int *pins = info->groups[group].pins;
 834         const struct rockchip_pin_config *data = info->groups[group].data;
 835         struct rockchip_pin_bank *bank;
 836         int cnt, ret = 0;
 837
 838         dev_dbg(info->dev, "enable function %s group %s\n",
 839                 info->functions[selector].name, info->groups[group].name);
 840
 841         /*
 842          * for each pin in the pin group selected, program the correspoding pin
 843          * pin function number in the config register.
 844          */
 845         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 846                 bank = pin_to_bank(info, pins[cnt]);
 847                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 848                                        data[cnt].func);
 849                 if (ret)
 850                         break;
 851         }
 852
 853         if (ret) {
 854                 /* revert the already done pin settings */
 855                 for (cnt--; cnt >= 0; cnt--)
 856                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 857
 858                 return ret;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * The calls to gpio_direction_output() and gpio_direction_input()
 866  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 867  * function called from the gpiolib interface).
 868  */
 869 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 870                                             int pin, bool input)
 871 {
 872         struct rockchip_pin_bank *bank;
 873         int ret;
 874         unsigned long flags;
 875         u32 data;
 876
 877         bank = gc_to_pin_bank(chip);
 878
 879         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 880         if (ret < 0)
 881                 return ret;
 882
 883         spin_lock_irqsave(&bank->slock, flags);
 884
 885         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 886         /* set bit to 1 for output, 0 for input */
 887         if (!input)
 888                 data |= BIT(pin);
 889         else
 890                 data &= ~BIT(pin);
 891         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 892
 893         spin_unlock_irqrestore(&bank->slock, flags);
 894
 895         return 0;
 896 }
 897
 898 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 899                                               struct pinctrl_gpio_range *range,
 900                                               unsigned offset, bool input)
 901 {
 902         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 903         struct gpio_chip *chip;
 904         int pin;
 905
 906         chip = range->gc;
 907         pin = offset - chip->base;
 908         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 909                  offset, range->name, pin, input ? "input" : "output");
 910
 911         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
 912                                                 input);
 913 }
 914
 915 static const struct pinmux_ops rockchip_pmx_ops = {
 916         .get_functions_count    = rockchip_pmx_get_funcs_count,
 917         .get_function_name      = rockchip_pmx_get_func_name,
 918         .get_function_groups    = rockchip_pmx_get_groups,
 919         .set_mux                = rockchip_pmx_set,
 920         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 921 };
 922
 923 /*
 924  * Pinconf_ops handling
 925  */
 926
 927 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 928                                         enum pin_config_param pull)
 929 {
 930         switch (ctrl->type) {
 931         case RK2928:
 932                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 933                                         pull == PIN_CONFIG_BIAS_DISABLE);
 934         case RK3066B:
 935                 return pull ? false : true;
 936         case RK3188:
 937         case RK3288:
 938                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 939         }
 940
 941         return false;
 942 }
 943
 944 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
 945 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 946
 947 /* set the pin config settings for a specified pin */
 948 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 949                                 unsigned long *configs, unsigned num_configs)
 950 {
 951         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 952         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 953         enum pin_config_param param;
 954         u16 arg;
 955         int i;
 956         int rc;
 957
 958         for (i = 0; i < num_configs; i++) {
 959                 param = pinconf_to_config_param(configs[i]);
 960                 arg = pinconf_to_config_argument(configs[i]);
 961
 962                 switch (param) {
 963                 case PIN_CONFIG_BIAS_DISABLE:
 964                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 965                                 param);
 966                         if (rc)
 967                                 return rc;
 968                         break;
 969                 case PIN_CONFIG_BIAS_PULL_UP:
 970                 case PIN_CONFIG_BIAS_PULL_DOWN:
 971                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 972                 case PIN_CONFIG_BIAS_BUS_HOLD:
 973                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 974                                 return -ENOTSUPP;
 975
 976                         if (!arg)
 977                                 return -EINVAL;
 978
 979                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 980                                 param);
 981                         if (rc)
 982                                 return rc;
 983                         break;
 984                 case PIN_CONFIG_OUTPUT:
 985                         rockchip_gpio_set(&bank->gpio_chip,
 986                                           pin - bank->pin_base, arg);
 987                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
 988                                           pin - bank->pin_base, false);
 989                         if (rc)
 990                                 return rc;
 991                         break;
 992                 case PIN_CONFIG_DRIVE_STRENGTH:
 993                         /* rk3288 is the first with per-pin drive-strength */
 994                         if (!info->ctrl->drv_calc_reg)
 995                                 return -ENOTSUPP;
 996
 997                         rc = rockchip_set_drive_perpin(bank,
 998                                                 pin - bank->pin_base, arg);
 999                         if (rc < 0)
1000                                 return rc;
1001                         break;
1002                 default:
1003                         return -ENOTSUPP;
1004                         break;
1005                 }
1006         } /* for each config */
1007
1008         return 0;
1009 }
1010
1011 /* get the pin config settings for a specified pin */
1012 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1013                                                         unsigned long *config)
1014 {
1015         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1016         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1017         enum pin_config_param param = pinconf_to_config_param(*config);
1018         u16 arg;
1019         int rc;
1020
1021         switch (param) {
1022         case PIN_CONFIG_BIAS_DISABLE:
1023                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1024                         return -EINVAL;
1025
1026                 arg = 0;
1027                 break;
1028         case PIN_CONFIG_BIAS_PULL_UP:
1029         case PIN_CONFIG_BIAS_PULL_DOWN:
1030         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1031         case PIN_CONFIG_BIAS_BUS_HOLD:
1032                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1033                         return -ENOTSUPP;
1034
1035                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1036                         return -EINVAL;
1037
1038                 arg = 1;
1039                 break;
1040         case PIN_CONFIG_OUTPUT:
1041                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1042                 if (rc != RK_FUNC_GPIO)
1043                         return -EINVAL;
1044
1045                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1046                 if (rc < 0)
1047                         return rc;
1048
1049                 arg = rc ? 1 : 0;
1050                 break;
1051         case PIN_CONFIG_DRIVE_STRENGTH:
1052                 /* rk3288 is the first with per-pin drive-strength */
1053                 if (!info->ctrl->drv_calc_reg)
1054                         return -ENOTSUPP;
1055
1056                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1057                 if (rc < 0)
1058                         return rc;
1059
1060                 arg = rc;
1061                 break;
1062         default:
1063                 return -ENOTSUPP;
1064                 break;
1065         }
1066
1067         *config = pinconf_to_config_packed(param, arg);
1068
1069         return 0;
1070 }
1071
1072 static const struct pinconf_ops rockchip_pinconf_ops = {
1073         .pin_config_get                 = rockchip_pinconf_get,
1074         .pin_config_set                 = rockchip_pinconf_set,
1075         .is_generic                     = true,
1076 };
1077
1078 static const struct of_device_id rockchip_bank_match[] = {
1079         { .compatible = "rockchip,gpio-bank" },
1080         { .compatible = "rockchip,rk3188-gpio-bank0" },
1081         {},
1082 };
1083
1084 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1085                                                 struct device_node *np)
1086 {
1087         struct device_node *child;
1088
1089         for_each_child_of_node(np, child) {
1090                 if (of_match_node(rockchip_bank_match, child))
1091                         continue;
1092
1093                 info->nfunctions++;
1094                 info->ngroups += of_get_child_count(child);
1095         }
1096 }
1097
1098 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1099                                               struct rockchip_pin_group *grp,
1100                                               struct rockchip_pinctrl *info,
1101                                               u32 index)
1102 {
1103         struct rockchip_pin_bank *bank;
1104         int size;
1105         const __be32 *list;
1106         int num;
1107         int i, j;
1108         int ret;
1109
1110         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1111
1112         /* Initialise group */
1113         grp->name = np->name;
1114
1115         /*
1116          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1117          * do sanity check and calculate pins number
1118          */
1119         list = of_get_property(np, "rockchip,pins", &size);
1120         /* we do not check return since it's safe node passed down */
1121         size /= sizeof(*list);
1122         if (!size || size % 4) {
1123                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1124                 return -EINVAL;
1125         }
1126
1127         grp->npins = size / 4;
1128
1129         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1130                                                 GFP_KERNEL);
1131         grp->data = devm_kzalloc(info->dev, grp->npins *
1132                                           sizeof(struct rockchip_pin_config),
1133                                         GFP_KERNEL);
1134         if (!grp->pins || !grp->data)
1135                 return -ENOMEM;
1136
1137         for (i = 0, j = 0; i < size; i += 4, j++) {
1138                 const __be32 *phandle;
1139                 struct device_node *np_config;
1140
1141                 num = be32_to_cpu(*list++);
1142                 bank = bank_num_to_bank(info, num);
1143                 if (IS_ERR(bank))
1144                         return PTR_ERR(bank);
1145
1146                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1147                 grp->data[j].func = be32_to_cpu(*list++);
1148
1149                 phandle = list++;
1150                 if (!phandle)
1151                         return -EINVAL;
1152
1153                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1154                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1155                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1156                 if (ret)
1157                         return ret;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1164                                                 struct rockchip_pinctrl *info,
1165                                                 u32 index)
1166 {
1167         struct device_node *child;
1168         struct rockchip_pmx_func *func;
1169         struct rockchip_pin_group *grp;
1170         int ret;
1171         static u32 grp_index;
1172         u32 i = 0;
1173
1174         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1175
1176         func = &info->functions[index];
1177
1178         /* Initialise function */
1179         func->name = np->name;
1180         func->ngroups = of_get_child_count(np);
1181         if (func->ngroups <= 0)
1182                 return 0;
1183
1184         func->groups = devm_kzalloc(info->dev,
1185                         func->ngroups * sizeof(char *), GFP_KERNEL);
1186         if (!func->groups)
1187                 return -ENOMEM;
1188
1189         for_each_child_of_node(np, child) {
1190                 func->groups[i] = child->name;
1191                 grp = &info->groups[grp_index++];
1192                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1193                 if (ret)
1194                         return ret;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1201                                               struct rockchip_pinctrl *info)
1202 {
1203         struct device *dev = &pdev->dev;
1204         struct device_node *np = dev->of_node;
1205         struct device_node *child;
1206         int ret;
1207         int i;
1208
1209         rockchip_pinctrl_child_count(info, np);
1210
1211         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1212         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1213
1214         info->functions = devm_kzalloc(dev, info->nfunctions *
1215                                               sizeof(struct rockchip_pmx_func),
1216                                               GFP_KERNEL);
1217         if (!info->functions) {
1218                 dev_err(dev, "failed to allocate memory for function list\n");
1219                 return -EINVAL;
1220         }
1221
1222         info->groups = devm_kzalloc(dev, info->ngroups *
1223                                             sizeof(struct rockchip_pin_group),
1224                                             GFP_KERNEL);
1225         if (!info->groups) {
1226                 dev_err(dev, "failed allocate memory for ping group list\n");
1227                 return -EINVAL;
1228         }
1229
1230         i = 0;
1231
1232         for_each_child_of_node(np, child) {
1233                 if (of_match_node(rockchip_bank_match, child))
1234                         continue;
1235
1236                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1237                 if (ret) {
1238                         dev_err(&pdev->dev, "failed to parse function\n");
1239                         return ret;
1240                 }
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int rockchip_pinctrl_register(struct platform_device *pdev,
1247                                         struct rockchip_pinctrl *info)
1248 {
1249         struct pinctrl_desc *ctrldesc = &info->pctl;
1250         struct pinctrl_pin_desc *pindesc, *pdesc;
1251         struct rockchip_pin_bank *pin_bank;
1252         int pin, bank, ret;
1253         int k;
1254
1255         ctrldesc->name = "rockchip-pinctrl";
1256         ctrldesc->owner = THIS_MODULE;
1257         ctrldesc->pctlops = &rockchip_pctrl_ops;
1258         ctrldesc->pmxops = &rockchip_pmx_ops;
1259         ctrldesc->confops = &rockchip_pinconf_ops;
1260
1261         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1262                         info->ctrl->nr_pins, GFP_KERNEL);
1263         if (!pindesc) {
1264                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1265                 return -ENOMEM;
1266         }
1267         ctrldesc->pins = pindesc;
1268         ctrldesc->npins = info->ctrl->nr_pins;
1269
1270         pdesc = pindesc;
1271         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1272                 pin_bank = &info->ctrl->pin_banks[bank];
1273                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1274                         pdesc->number = k;
1275                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1276                                                 pin_bank->name, pin);
1277                         pdesc++;
1278                 }
1279         }
1280
1281         ret = rockchip_pinctrl_parse_dt(pdev, info);
1282         if (ret)
1283                 return ret;
1284
1285         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1286         if (IS_ERR(info->pctl_dev)) {
1287                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1288                 return PTR_ERR(info->pctl_dev);
1289         }
1290
1291         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1292                 pin_bank = &info->ctrl->pin_banks[bank];
1293                 pin_bank->grange.name = pin_bank->name;
1294                 pin_bank->grange.id = bank;
1295                 pin_bank->grange.pin_base = pin_bank->pin_base;
1296                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1297                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1298                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1299                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1300         }
1301
1302         return 0;
1303 }
1304
1305 /*
1306  * GPIO handling
1307  */
1308
1309 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1310 {
1311         return pinctrl_request_gpio(chip->base + offset);
1312 }
1313
1314 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1315 {
1316         pinctrl_free_gpio(chip->base + offset);
1317 }
1318
1319 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1320 {
1321         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1322         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1323         unsigned long flags;
1324         u32 data;
1325
1326         spin_lock_irqsave(&bank->slock, flags);
1327
1328         data = readl(reg);
1329         data &= ~BIT(offset);
1330         if (value)
1331                 data |= BIT(offset);
1332         writel(data, reg);
1333
1334         spin_unlock_irqrestore(&bank->slock, flags);
1335 }
1336
1337 /*
1338  * Returns the level of the pin for input direction and setting of the DR
1339  * register for output gpios.
1340  */
1341 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1342 {
1343         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1344         u32 data;
1345
1346         data = readl(bank->reg_base + GPIO_EXT_PORT);
1347         data >>= offset;
1348         data &= 1;
1349         return data;
1350 }
1351
1352 /*
1353  * gpiolib gpio_direction_input callback function. The setting of the pin
1354  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1355  * interface.
1356  */
1357 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1358 {
1359         return pinctrl_gpio_direction_input(gc->base + offset);
1360 }
1361
1362 /*
1363  * gpiolib gpio_direction_output callback function. The setting of the pin
1364  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1365  * interface.
1366  */
1367 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1368                                           unsigned offset, int value)
1369 {
1370         rockchip_gpio_set(gc, offset, value);
1371         return pinctrl_gpio_direction_output(gc->base + offset);
1372 }
1373
1374 /*
1375  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1376  * and a virtual IRQ, if not already present.
1377  */
1378 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1379 {
1380         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1381         unsigned int virq;
1382
1383         if (!bank->domain)
1384                 return -ENXIO;
1385
1386         virq = irq_create_mapping(bank->domain, offset);
1387
1388         return (virq) ? : -ENXIO;
1389 }
1390
1391 static const struct gpio_chip rockchip_gpiolib_chip = {
1392         .request = rockchip_gpio_request,
1393         .free = rockchip_gpio_free,
1394         .set = rockchip_gpio_set,
1395         .get = rockchip_gpio_get,
1396         .direction_input = rockchip_gpio_direction_input,
1397         .direction_output = rockchip_gpio_direction_output,
1398         .to_irq = rockchip_gpio_to_irq,
1399         .owner = THIS_MODULE,
1400 };
1401
1402 /*
1403  * Interrupt handling
1404  */
1405
1406 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1407 {
1408         struct irq_chip *chip = irq_get_chip(irq);
1409         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1410         u32 pend;
1411
1412         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1413
1414         chained_irq_enter(chip, desc);
1415
1416         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1417
1418         while (pend) {
1419                 unsigned int virq;
1420
1421                 irq = __ffs(pend);
1422                 pend &= ~BIT(irq);
1423                 virq = irq_linear_revmap(bank->domain, irq);
1424
1425                 if (!virq) {
1426                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1427                         continue;
1428                 }
1429
1430                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1431
1432                 /*
1433                  * Triggering IRQ on both rising and falling edge
1434                  * needs manual intervention.
1435                  */
1436                 if (bank->toggle_edge_mode & BIT(irq)) {
1437                         u32 data, data_old, polarity;
1438                         unsigned long flags;
1439
1440                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1441                         do {
1442                                 spin_lock_irqsave(&bank->slock, flags);
1443
1444                                 polarity = readl_relaxed(bank->reg_base +
1445                                                          GPIO_INT_POLARITY);
1446                                 if (data & BIT(irq))
1447                                         polarity &= ~BIT(irq);
1448                                 else
1449                                         polarity |= BIT(irq);
1450                                 writel(polarity,
1451                                        bank->reg_base + GPIO_INT_POLARITY);
1452
1453                                 spin_unlock_irqrestore(&bank->slock, flags);
1454
1455                                 data_old = data;
1456                                 data = readl_relaxed(bank->reg_base +
1457                                                      GPIO_EXT_PORT);
1458                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1459                 }
1460
1461                 generic_handle_irq(virq);
1462         }
1463
1464         chained_irq_exit(chip, desc);
1465 }
1466
1467 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1468 {
1469         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1470         struct rockchip_pin_bank *bank = gc->private;
1471         u32 mask = BIT(d->hwirq);
1472         u32 polarity;
1473         u32 level;
1474         u32 data;
1475         unsigned long flags;
1476         int ret;
1477
1478         /* make sure the pin is configured as gpio input */
1479         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1480         if (ret < 0)
1481                 return ret;
1482
1483         spin_lock_irqsave(&bank->slock, flags);
1484
1485         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1486         data &= ~mask;
1487         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1488
1489         spin_unlock_irqrestore(&bank->slock, flags);
1490
1491         if (type & IRQ_TYPE_EDGE_BOTH)
1492                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1493         else
1494                 __irq_set_handler_locked(d->irq, handle_level_irq);
1495
1496         spin_lock_irqsave(&bank->slock, flags);
1497         irq_gc_lock(gc);
1498
1499         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1500         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1501
1502         switch (type) {
1503         case IRQ_TYPE_EDGE_BOTH:
1504                 bank->toggle_edge_mode |= mask;
1505                 level |= mask;
1506
1507                 /*
1508                  * Determine gpio state. If 1 next interrupt should be falling
1509                  * otherwise rising.
1510                  */
1511                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1512                 if (data & mask)
1513                         polarity &= ~mask;
1514                 else
1515                         polarity |= mask;
1516                 break;
1517         case IRQ_TYPE_EDGE_RISING:
1518                 bank->toggle_edge_mode &= ~mask;
1519                 level |= mask;
1520                 polarity |= mask;
1521                 break;
1522         case IRQ_TYPE_EDGE_FALLING:
1523                 bank->toggle_edge_mode &= ~mask;
1524                 level |= mask;
1525                 polarity &= ~mask;
1526                 break;
1527         case IRQ_TYPE_LEVEL_HIGH:
1528                 bank->toggle_edge_mode &= ~mask;
1529                 level &= ~mask;
1530                 polarity |= mask;
1531                 break;
1532         case IRQ_TYPE_LEVEL_LOW:
1533                 bank->toggle_edge_mode &= ~mask;
1534                 level &= ~mask;
1535                 polarity &= ~mask;
1536                 break;
1537         default:
1538                 irq_gc_unlock(gc);
1539                 spin_unlock_irqrestore(&bank->slock, flags);
1540                 return -EINVAL;
1541         }
1542
1543         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1544         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1545
1546         irq_gc_unlock(gc);
1547         spin_unlock_irqrestore(&bank->slock, flags);
1548
1549         return 0;
1550 }
1551
1552 static void rockchip_irq_suspend(struct irq_data *d)
1553 {
1554         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1555         struct rockchip_pin_bank *bank = gc->private;
1556
1557         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1558         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1559 }
1560
1561 static void rockchip_irq_resume(struct irq_data *d)
1562 {
1563         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1564         struct rockchip_pin_bank *bank = gc->private;
1565
1566         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
1567 }
1568
1569 static int rockchip_interrupts_register(struct platform_device *pdev,
1570                                                 struct rockchip_pinctrl *info)
1571 {
1572         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1573         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1574         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1575         struct irq_chip_generic *gc;
1576         int ret;
1577         int i;
1578
1579         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1580                 if (!bank->valid) {
1581                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1582                                  bank->name);
1583                         continue;
1584                 }
1585
1586                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1587                                                 &irq_generic_chip_ops, NULL);
1588                 if (!bank->domain) {
1589                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1590                                  bank->name);
1591                         continue;
1592                 }
1593
1594                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1595                                          "rockchip_gpio_irq", handle_level_irq,
1596                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1597                 if (ret) {
1598                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1599                                 bank->name);
1600                         irq_domain_remove(bank->domain);
1601                         continue;
1602                 }
1603
1604                 /*
1605                  * Linux assumes that all interrupts start out disabled/masked.
1606                  * Our driver only uses the concept of masked and always keeps
1607                  * things enabled, so for us that's all masked and all enabled.
1608                  */
1609                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1610                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1611
1612                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1613                 gc->reg_base = bank->reg_base;
1614                 gc->private = bank;
1615                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
1616                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1617                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1618                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
1619                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
1620                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1621                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1622                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
1623                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1624                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1625
1626                 irq_set_handler_data(bank->irq, bank);
1627                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1628         }
1629
1630         return 0;
1631 }
1632
1633 static int rockchip_gpiolib_register(struct platform_device *pdev,
1634                                                 struct rockchip_pinctrl *info)
1635 {
1636         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1637         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1638         struct gpio_chip *gc;
1639         int ret;
1640         int i;
1641
1642         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1643                 if (!bank->valid) {
1644                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1645                                  bank->name);
1646                         continue;
1647                 }
1648
1649                 bank->gpio_chip = rockchip_gpiolib_chip;
1650
1651                 gc = &bank->gpio_chip;
1652                 gc->base = bank->pin_base;
1653                 gc->ngpio = bank->nr_pins;
1654                 gc->dev = &pdev->dev;
1655                 gc->of_node = bank->of_node;
1656                 gc->label = bank->name;
1657
1658                 ret = gpiochip_add(gc);
1659                 if (ret) {
1660                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1661                                                         gc->label, ret);
1662                         goto fail;
1663                 }
1664         }
1665
1666         rockchip_interrupts_register(pdev, info);
1667
1668         return 0;
1669
1670 fail:
1671         for (--i, --bank; i >= 0; --i, --bank) {
1672                 if (!bank->valid)
1673                         continue;
1674                 gpiochip_remove(&bank->gpio_chip);
1675         }
1676         return ret;
1677 }
1678
1679 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1680                                                 struct rockchip_pinctrl *info)
1681 {
1682         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1683         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1684         int i;
1685
1686         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1687                 if (!bank->valid)
1688                         continue;
1689                 gpiochip_remove(&bank->gpio_chip);
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1696                                   struct rockchip_pinctrl *info)
1697 {
1698         struct resource res;
1699         void __iomem *base;
1700
1701         if (of_address_to_resource(bank->of_node, 0, &res)) {
1702                 dev_err(info->dev, "cannot find IO resource for bank\n");
1703                 return -ENOENT;
1704         }
1705
1706         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1707         if (IS_ERR(bank->reg_base))
1708                 return PTR_ERR(bank->reg_base);
1709
1710         /*
1711          * special case, where parts of the pull setting-registers are
1712          * part of the PMU register space
1713          */
1714         if (of_device_is_compatible(bank->of_node,
1715                                     "rockchip,rk3188-gpio-bank0")) {
1716                 struct device_node *node;
1717
1718                 node = of_parse_phandle(bank->of_node->parent,
1719                                         "rockchip,pmu", 0);
1720                 if (!node) {
1721                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1722                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1723                                 return -ENOENT;
1724                         }
1725
1726                         base = devm_ioremap_resource(info->dev, &res);
1727                         if (IS_ERR(base))
1728                                 return PTR_ERR(base);
1729                         rockchip_regmap_config.max_register =
1730                                                     resource_size(&res) - 4;
1731                         rockchip_regmap_config.name =
1732                                             "rockchip,rk3188-gpio-bank0-pull";
1733                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1734                                                     base,
1735                                                     &rockchip_regmap_config);
1736                 }
1737         }
1738
1739         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1740
1741         bank->clk = of_clk_get(bank->of_node, 0);
1742         if (IS_ERR(bank->clk))
1743                 return PTR_ERR(bank->clk);
1744
1745         return clk_prepare_enable(bank->clk);
1746 }
1747
1748 static const struct of_device_id rockchip_pinctrl_dt_match[];
1749
1750 /* retrieve the soc specific data */
1751 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1752                                                 struct rockchip_pinctrl *d,
1753                                                 struct platform_device *pdev)
1754 {
1755         const struct of_device_id *match;
1756         struct device_node *node = pdev->dev.of_node;
1757         struct device_node *np;
1758         struct rockchip_pin_ctrl *ctrl;
1759         struct rockchip_pin_bank *bank;
1760         int grf_offs, pmu_offs, i, j;
1761
1762         match = of_match_node(rockchip_pinctrl_dt_match, node);
1763         ctrl = (struct rockchip_pin_ctrl *)match->data;
1764
1765         for_each_child_of_node(node, np) {
1766                 if (!of_find_property(np, "gpio-controller", NULL))
1767                         continue;
1768
1769                 bank = ctrl->pin_banks;
1770                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1771                         if (!strcmp(bank->name, np->name)) {
1772                                 bank->of_node = np;
1773
1774                                 if (!rockchip_get_bank_data(bank, d))
1775                                         bank->valid = true;
1776
1777                                 break;
1778                         }
1779                 }
1780         }
1781
1782         grf_offs = ctrl->grf_mux_offset;
1783         pmu_offs = ctrl->pmu_mux_offset;
1784         bank = ctrl->pin_banks;
1785         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1786                 int bank_pins = 0;
1787
1788                 spin_lock_init(&bank->slock);
1789                 bank->drvdata = d;
1790                 bank->pin_base = ctrl->nr_pins;
1791                 ctrl->nr_pins += bank->nr_pins;
1792
1793                 /* calculate iomux offsets */
1794                 for (j = 0; j < 4; j++) {
1795                         struct rockchip_iomux *iom = &bank->iomux[j];
1796                         int inc;
1797
1798                         if (bank_pins >= bank->nr_pins)
1799                                 break;
1800
1801                         /* preset offset value, set new start value */
1802                         if (iom->offset >= 0) {
1803                                 if (iom->type & IOMUX_SOURCE_PMU)
1804                                         pmu_offs = iom->offset;
1805                                 else
1806                                         grf_offs = iom->offset;
1807                         } else { /* set current offset */
1808                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1809                                                         pmu_offs : grf_offs;
1810                         }
1811
1812                         dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1813                                  i, j, iom->offset);
1814
1815                         /*
1816                          * Increase offset according to iomux width.
1817                          * 4bit iomux'es are spread over two registers.
1818                          */
1819                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1820                         if (iom->type & IOMUX_SOURCE_PMU)
1821                                 pmu_offs += inc;
1822                         else
1823                                 grf_offs += inc;
1824
1825                         bank_pins += 8;
1826                 }
1827         }
1828
1829         return ctrl;
1830 }
1831
1832 #define RK3288_GRF_GPIO6C_IOMUX         0x64
1833 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
1834
1835 static u32 rk3288_grf_gpio6c_iomux;
1836
1837 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
1838 {
1839         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1840         int ret = pinctrl_force_sleep(info->pctl_dev);
1841
1842         if (ret)
1843                 return ret;
1844
1845         /*
1846          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
1847          * the setting here, and restore it at resume.
1848          */
1849         if (info->ctrl->type == RK3288) {
1850                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1851                                   &rk3288_grf_gpio6c_iomux);
1852                 if (ret) {
1853                         pinctrl_force_default(info->pctl_dev);
1854                         return ret;
1855                 }
1856         }
1857
1858         return 0;
1859 }
1860
1861 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
1862 {
1863         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1864         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1865                                rk3288_grf_gpio6c_iomux |
1866                                GPIO6C6_SEL_WRITE_ENABLE);
1867
1868         if (ret)
1869                 return ret;
1870
1871         return pinctrl_force_default(info->pctl_dev);
1872 }
1873
1874 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
1875                          rockchip_pinctrl_resume);
1876
1877 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1878 {
1879         struct rockchip_pinctrl *info;
1880         struct device *dev = &pdev->dev;
1881         struct rockchip_pin_ctrl *ctrl;
1882         struct device_node *np = pdev->dev.of_node, *node;
1883         struct resource *res;
1884         void __iomem *base;
1885         int ret;
1886
1887         if (!dev->of_node) {
1888                 dev_err(dev, "device tree node not found\n");
1889                 return -ENODEV;
1890         }
1891
1892         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1893         if (!info)
1894                 return -ENOMEM;
1895
1896         info->dev = dev;
1897
1898         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1899         if (!ctrl) {
1900                 dev_err(dev, "driver data not available\n");
1901                 return -EINVAL;
1902         }
1903         info->ctrl = ctrl;
1904
1905         node = of_parse_phandle(np, "rockchip,grf", 0);
1906         if (node) {
1907                 info->regmap_base = syscon_node_to_regmap(node);
1908                 if (IS_ERR(info->regmap_base))
1909                         return PTR_ERR(info->regmap_base);
1910         } else {
1911                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1912                 base = devm_ioremap_resource(&pdev->dev, res);
1913                 if (IS_ERR(base))
1914                         return PTR_ERR(base);
1915
1916                 rockchip_regmap_config.max_register = resource_size(res) - 4;
1917                 rockchip_regmap_config.name = "rockchip,pinctrl";
1918                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1919                                                     &rockchip_regmap_config);
1920
1921                 /* to check for the old dt-bindings */
1922                 info->reg_size = resource_size(res);
1923
1924                 /* Honor the old binding, with pull registers as 2nd resource */
1925                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1926                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1927                         base = devm_ioremap_resource(&pdev->dev, res);
1928                         if (IS_ERR(base))
1929                                 return PTR_ERR(base);
1930
1931                         rockchip_regmap_config.max_register =
1932                                                         resource_size(res) - 4;
1933                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1934                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1935                                                     base,
1936                                                     &rockchip_regmap_config);
1937                 }
1938         }
1939
1940         /* try to find the optional reference to the pmu syscon */
1941         node = of_parse_phandle(np, "rockchip,pmu", 0);
1942         if (node) {
1943                 info->regmap_pmu = syscon_node_to_regmap(node);
1944                 if (IS_ERR(info->regmap_pmu))
1945                         return PTR_ERR(info->regmap_pmu);
1946         }
1947
1948         ret = rockchip_gpiolib_register(pdev, info);
1949         if (ret)
1950                 return ret;
1951
1952         ret = rockchip_pinctrl_register(pdev, info);
1953         if (ret) {
1954                 rockchip_gpiolib_unregister(pdev, info);
1955                 return ret;
1956         }
1957
1958         platform_set_drvdata(pdev, info);
1959
1960         return 0;
1961 }
1962
1963 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1964         PIN_BANK(0, 32, "gpio0"),
1965         PIN_BANK(1, 32, "gpio1"),
1966         PIN_BANK(2, 32, "gpio2"),
1967         PIN_BANK(3, 32, "gpio3"),
1968 };
1969
1970 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1971                 .pin_banks              = rk2928_pin_banks,
1972                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1973                 .label                  = "RK2928-GPIO",
1974                 .type                   = RK2928,
1975                 .grf_mux_offset         = 0xa8,
1976                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1977 };
1978
1979 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1980         PIN_BANK(0, 32, "gpio0"),
1981         PIN_BANK(1, 32, "gpio1"),
1982         PIN_BANK(2, 32, "gpio2"),
1983         PIN_BANK(3, 32, "gpio3"),
1984         PIN_BANK(4, 32, "gpio4"),
1985         PIN_BANK(6, 16, "gpio6"),
1986 };
1987
1988 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1989                 .pin_banks              = rk3066a_pin_banks,
1990                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1991                 .label                  = "RK3066a-GPIO",
1992                 .type                   = RK2928,
1993                 .grf_mux_offset         = 0xa8,
1994                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1995 };
1996
1997 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1998         PIN_BANK(0, 32, "gpio0"),
1999         PIN_BANK(1, 32, "gpio1"),
2000         PIN_BANK(2, 32, "gpio2"),
2001         PIN_BANK(3, 32, "gpio3"),
2002 };
2003
2004 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2005                 .pin_banks      = rk3066b_pin_banks,
2006                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2007                 .label          = "RK3066b-GPIO",
2008                 .type           = RK3066B,
2009                 .grf_mux_offset = 0x60,
2010 };
2011
2012 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2013         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2014         PIN_BANK(1, 32, "gpio1"),
2015         PIN_BANK(2, 32, "gpio2"),
2016         PIN_BANK(3, 32, "gpio3"),
2017 };
2018
2019 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2020                 .pin_banks              = rk3188_pin_banks,
2021                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2022                 .label                  = "RK3188-GPIO",
2023                 .type                   = RK3188,
2024                 .grf_mux_offset         = 0x60,
2025                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2026 };
2027
2028 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2029         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2030                                              IOMUX_SOURCE_PMU,
2031                                              IOMUX_SOURCE_PMU,
2032                                              IOMUX_UNROUTED
2033                             ),
2034         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2035                                              IOMUX_UNROUTED,
2036                                              IOMUX_UNROUTED,
2037                                              0
2038                             ),
2039         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2040         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2041         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2042                                              IOMUX_WIDTH_4BIT,
2043                                              0,
2044                                              0
2045                             ),
2046         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2047                                              0,
2048                                              0,
2049                                              IOMUX_UNROUTED
2050                             ),
2051         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2052         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2053                                              0,
2054                                              IOMUX_WIDTH_4BIT,
2055                                              IOMUX_UNROUTED
2056                             ),
2057         PIN_BANK(8, 16, "gpio8"),
2058 };
2059
2060 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2061                 .pin_banks              = rk3288_pin_banks,
2062                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2063                 .label                  = "RK3288-GPIO",
2064                 .type                   = RK3288,
2065                 .grf_mux_offset         = 0x0,
2066                 .pmu_mux_offset         = 0x84,
2067                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2068                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2069 };
2070
2071 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2072         { .compatible = "rockchip,rk2928-pinctrl",
2073                 .data = (void *)&rk2928_pin_ctrl },
2074         { .compatible = "rockchip,rk3066a-pinctrl",
2075                 .data = (void *)&rk3066a_pin_ctrl },
2076         { .compatible = "rockchip,rk3066b-pinctrl",
2077                 .data = (void *)&rk3066b_pin_ctrl },
2078         { .compatible = "rockchip,rk3188-pinctrl",
2079                 .data = (void *)&rk3188_pin_ctrl },
2080         { .compatible = "rockchip,rk3288-pinctrl",
2081                 .data = (void *)&rk3288_pin_ctrl },
2082         {},
2083 };
2084 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2085
2086 static struct platform_driver rockchip_pinctrl_driver = {
2087         .probe          = rockchip_pinctrl_probe,
2088         .driver = {
2089                 .name   = "rockchip-pinctrl",
2090                 .pm = &rockchip_pinctrl_dev_pm_ops,
2091                 .of_match_table = rockchip_pinctrl_dt_match,
2092         },
2093 };
2094
2095 static int __init rockchip_pinctrl_drv_register(void)
2096 {
2097         return platform_driver_register(&rockchip_pinctrl_driver);
2098 }
2099 postcore_initcall(rockchip_pinctrl_drv_register);
2100
2101 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2102 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2103 MODULE_LICENSE("GPL v2");