drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2016 Rockchip electronic L.T.D
   5  * Author: Luo Wei <lw@rock-chips.com>
   6  *
   7  * Thanks to Heiko Stuebner <heiko@sntech.de>
   8  * With some ideas taken from pinctrl-samsung
   9  *
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as published
  13  * by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/io.h>
  24 #include <linux/bitops.h>
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/gpio.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/pinctrl/machine.h>
  31 #include <linux/pinctrl/pinconf.h>
  32 #include <linux/pinctrl/pinctrl.h>
  33 #include <linux/pinctrl/pinmux.h>
  34 #include <linux/pinctrl/pinconf-generic.h>
  35 #include <linux/irqchip/chained_irq.h>
  36 #include <linux/clk.h>
  37 #include <linux/syscore_ops.h>
  38 #include <linux/highmem.h>
  39 #include <dt-bindings/pinctrl/rockchip.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/pinctrl/consumer.h>
  43 #include <linux/slab.h>
  44 #include <linux/delay.h>
  45 #include <linux/rockchip/grf.h>
  46 #include <linux/of_gpio.h>
  47
  48
  49 #ifdef CONFIG_DEBUG_FS
  50 #include <linux/debugfs.h>
  51 #endif
  52
  53
  54 #include "core.h"
  55 #include "pinconf.h"
  56
  57
  58 #if 1
  59 #define DBG_PINCTRL(x...) do { if((((atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)) && (atomic_read(&info->pin_debug_flag) == (pin + 1))) || ((atomic_read(&info->pin_debug_flag) == 0) && (atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)))) && bank && info) printk(x); } while (0)
  60 #else
  61 #define DBG_PINCTRL(x...)
  62 #endif
  63
  64
  65 /* GPIO control registers */
  66 #define GPIO_SWPORT_DR          0x00
  67 #define GPIO_SWPORT_DDR         0x04
  68 #define GPIO_INTEN              0x30
  69 #define GPIO_INTMASK            0x34
  70 #define GPIO_INTTYPE_LEVEL      0x38
  71 #define GPIO_INT_POLARITY       0x3c
  72 #define GPIO_INT_STATUS         0x40
  73 #define GPIO_INT_RAWSTATUS      0x44
  74 #define GPIO_DEBOUNCE           0x48
  75 #define GPIO_PORTS_EOI          0x4c
  76 #define GPIO_EXT_PORT           0x50
  77 #define GPIO_LS_SYNC            0x60
  78
  79 enum rockchip_pinctrl_type {
  80         RK2928,
  81         RK3066B,
  82         RK3188,
  83         RK3288,
  84         RK3036,
  85         RK312X,
  86 };
  87
  88 enum rockchip_pin_bank_type {
  89         COMMON_BANK,
  90         RK3188_BANK0,
  91         RK3288_BANK0,
  92 };
  93
  94 /**
  95  * @reg_base: register base of the gpio bank
  96  * @reg_pull: optional separate register for additional pull settings
  97  * @clk: clock of the gpio bank
  98  * @irq: interrupt of the gpio bank
  99  * @pin_base: first pin number
 100  * @nr_pins: number of pins in this bank
 101  * @name: name of the bank
 102  * @bank_num: number of the bank, to account for holes
 103  * @valid: are all necessary informations present
 104  * @of_node: dt node of this bank
 105  * @drvdata: common pinctrl basedata
 106  * @domain: irqdomain of the gpio bank
 107  * @gpio_chip: gpiolib chip
 108  * @grange: gpio range
 109  * @slock: spinlock for the gpio bank
 110  */
 111 struct rockchip_pin_bank {
 112         void __iomem                    *reg_base;
 113         void __iomem                    *reg_mux_bank0;
 114         void __iomem                    *reg_pull_bank0;
 115         void __iomem                    *reg_drv_bank0;
 116         struct clk                      *clk;
 117         int                             irq;
 118         u32                             pin_base;
 119         u8                              nr_pins;
 120         char                            *name;
 121         u8                              bank_num;
 122         enum rockchip_pin_bank_type     bank_type;
 123         bool                            valid;
 124         struct device_node              *of_node;
 125         struct rockchip_pinctrl         *drvdata;
 126         struct irq_domain               *domain;
 127         struct gpio_chip                gpio_chip;
 128         struct pinctrl_gpio_range       grange;
 129         spinlock_t                      slock;
 130         u32                             toggle_edge_mode;
 131         u32                             suspend_wakeup;
 132         u32                             saved_wakeup;
 133 };
 134
 135 #define PIN_BANK(id, pins, label)                       \
 136         {                                               \
 137                 .bank_num       = id,                   \
 138                 .nr_pins        = pins,                 \
 139                 .name           = label,                \
 140         }
 141
 142 /**
 143  */
 144 struct rockchip_pin_ctrl {
 145         struct rockchip_pin_bank        *pin_banks;
 146         u32                             nr_banks;
 147         u32                             nr_pins;
 148         char                            *label;
 149         enum rockchip_pinctrl_type      type;
 150         int                             mux_offset;
 151         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 152                                  void __iomem **reg, u8 *bit);
 153         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 154                                  void __iomem **reg, u8 *bit);
 155 };
 156
 157 struct rockchip_pin_config {
 158         unsigned int            func;
 159         unsigned long           *configs;
 160         unsigned int            nconfigs;
 161 };
 162
 163 /**
 164  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 165  * @name: name of the pin group, used to lookup the group.
 166  * @pins: the pins included in this group.
 167  * @npins: number of pins included in this group.
 168  * @func: the mux function number to be programmed when selected.
 169  * @configs: the config values to be set for each pin
 170  * @nconfigs: number of configs for each pin
 171  */
 172 struct rockchip_pin_group {
 173         const char                      *name;
 174         const char                      *func_name;
 175         unsigned int                    npins;
 176         unsigned int                    *pins;
 177         struct rockchip_pin_config      *data;
 178         unsigned long   gconfigs;
 179 };
 180
 181 /**
 182  * struct rockchip_pmx_func: represent a pin function.
 183  * @name: name of the pin function, used to lookup the function.
 184  * @groups: one or more names of pin groups that provide this function.
 185  * @num_groups: number of groups included in @groups.
 186  */
 187 struct rockchip_pmx_func {
 188         const char              *name;
 189         const char              **groups;
 190         u8                      ngroups;
 191 };
 192
 193 struct gpio_init_config {
 194         struct gpio *gpios;
 195         int nr_gpios;
 196 };
 197
 198
 199 struct rockchip_pinctrl {
 200         void __iomem                    *reg_base;
 201
 202         void __iomem                    *reg_mux;
 203         void __iomem                    *reg_pull;
 204         void __iomem                    *reg_drv;
 205
 206         struct device                   *dev;
 207         struct rockchip_pin_ctrl        *ctrl;
 208         struct pinctrl_desc             pctl;
 209         struct pinctrl_dev              *pctl_dev;
 210         struct rockchip_pin_group       *groups;
 211         unsigned int                    ngroups;
 212         struct rockchip_pmx_func        *functions;
 213         unsigned int                    nfunctions;
 214
 215         atomic_t                        bank_debug_flag;
 216         atomic_t                        pin_debug_flag;
 217 #ifdef CONFIG_DEBUG_FS
 218         struct dentry *debugfs;
 219 #endif
 220         struct gpio_init_config         *config;
 221 };
 222
 223 struct iomux_mode{
 224         unsigned int mode:4,
 225                      off:4,
 226                      goff:4,
 227                      bank:4,
 228                      reserve:16;
 229 };
 230
 231 struct union_mode{
 232         union{
 233                 struct iomux_mode mux;
 234                 unsigned int mode;
 235         };
 236 };
 237
 238 struct func_to_reg_offset {
 239         unsigned int reg_type;
 240         const char *vol_name;
 241         const char *func_name;
 242         const char *group_name;
 243         unsigned int reg_offset;
 244         unsigned int bit_offset;
 245         unsigned int bit_mask;
 246 };
 247
 248 #define FUNC_GROUP_TO_REG_OFFSET(type, vol, func, group, reg, bit, mask)        \
 249         {                                               \
 250                 .reg_type       = type,         \
 251                 .vol_name       = vol,          \
 252                 .func_name      = func,         \
 253                 .group_name     = group,        \
 254                 .reg_offset     = reg,          \
 255                 .bit_offset     = bit,          \
 256                 .bit_mask       = mask,         \
 257         }
 258
 259
 260 static struct rockchip_pinctrl *g_info;
 261
 262
 263 #ifdef CONFIG_DEBUG_FS
 264 #define PINCTRL_REGS_BUFSIZE    (1024<<4)
 265 static ssize_t pinctrl_write_proc_data(struct file *file, const char __user *buffer,
 266                            size_t count, loff_t *data)
 267 {
 268         struct rockchip_pinctrl *info;
 269         char *buf;
 270         ssize_t ret;
 271         int bank_value, pin_value;
 272
 273         info = file->private_data;
 274
 275         buf = kzalloc(32, GFP_KERNEL);
 276         if (!buf)
 277         return 0;
 278
 279         ret = copy_from_user(buf, buffer, count);
 280         if (ret)
 281         {
 282                 return ret;
 283         }
 284
 285         if((strstr(buf, "debug") != NULL) || (strstr(buf, "DEBUG") != NULL))
 286         {
 287                 if(strstr(buf, "-") != NULL)
 288                 {
 289                         if(strstr(buf, "debug") != NULL)
 290                         sscanf(buf, "debug%d-%d", &bank_value, &pin_value);
 291                         else if(strstr(buf, "DEBUG") != NULL)
 292                         sscanf(buf, "DEBUG%d-%d", &bank_value, &pin_value);
 293
 294                         if((bank_value < 0) || (pin_value < 0))
 295                         {
 296                                 printk("%s:error:bank %d or pin %d is out of range %d-%d\n",__func__, bank_value, pin_value, info->ctrl->nr_banks-1, info->ctrl->nr_pins);
 297                         }
 298                         else
 299                         {
 300                                 atomic_set(&info->bank_debug_flag, bank_value+1);
 301                                 atomic_set(&info->pin_debug_flag, pin_value+1);
 302                                 printk("%s:open debug for bank%d-%d\n",__func__,bank_value, pin_value);
 303                         }
 304                 }
 305                 else
 306                 {
 307                         if(strstr(buf, "debug") != NULL)
 308                         sscanf(buf, "debug%d", &bank_value);
 309                         else if(strstr(buf, "DEBUG") != NULL)
 310                         sscanf(buf, "DEBUG%d", &bank_value);
 311
 312                         if((bank_value < 0))
 313                         {
 314                                 printk("%s:error:bank%d is out of range %d\n",__func__, bank_value,info->ctrl->nr_banks-1);
 315                         }
 316                         else
 317                         {
 318                                 atomic_set(&info->bank_debug_flag, bank_value+1);
 319                                 atomic_set(&info->pin_debug_flag, 0);
 320                                 printk("%s:open debug for bank%d\n",__func__,bank_value);
 321                         }
 322                 }
 323
 324         }
 325         else if((strstr(buf, "stop") != NULL) || (strstr(buf, "STOP") != NULL))
 326         {
 327                 atomic_set(&info->bank_debug_flag, 0);
 328                 atomic_set(&info->pin_debug_flag, 0);
 329                 printk("%s:close debug\n",__func__);
 330         }
 331
 332         kfree(buf);
 333
 334         return count;
 335 }
 336
 337 static ssize_t  pinctrl_show_regs(struct file *file, char __user *user_buf,
 338                                 size_t count, loff_t *ppos)
 339 {
 340         struct rockchip_pinctrl *info;
 341         struct rockchip_pin_ctrl *ctrl;
 342         struct rockchip_pin_bank *bank, *bank0;
 343         char *buf;
 344         u32 len = 0;
 345         ssize_t ret;
 346         int i = 0, n = 0;
 347         int value = 0;
 348
 349         info = file->private_data;
 350         ctrl = info->ctrl;
 351         bank = ctrl->pin_banks;
 352         bank0 = bank;
 353
 354         buf = kzalloc(PINCTRL_REGS_BUFSIZE, GFP_KERNEL);
 355         if (!buf)
 356                 return 0;
 357
 358         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 359                         "%s registers:\n",ctrl->label);
 360         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 361                         "=================================\n");
 362
 363         for(n=0; n<ctrl->nr_banks-1; n++)
 364         {
 365                 for(i=GPIO_SWPORT_DR; i<GPIO_LS_SYNC; i=i+4)
 366                 {
 367                         value = readl_relaxed(bank->reg_base + i);
 368                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "bank%d reg[0x%p+0x%x]=0x%08x\n",bank->bank_num, (int *)bank->reg_base, i, value);
 369                 }
 370                 bank++;
 371         }
 372
 373         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 374                         "=================================\n\n");
 375
 376         if(bank0 && bank0->reg_mux_bank0 && bank0->reg_pull_bank0 && bank0->reg_drv_bank0)
 377         {
 378                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 379                                 "BANK0 GRF registers:\n");
 380                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 381                                 "=================================\n");
 382
 383                 for(i=0; i<0x0c; i=i+4)
 384                 {
 385                         value = readl_relaxed(bank0->reg_mux_bank0 + i);
 386                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "MUX_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_mux_bank0, i, value);
 387                 }
 388
 389                 for(i=0; i<0x0c; i=i+4)
 390                 {
 391                         value = readl_relaxed(bank0->reg_pull_bank0 + i);
 392                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "PULL_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_pull_bank0, i, value);
 393                 }
 394
 395                 for(i=0; i<0x0c; i=i+4)
 396                 {
 397                         value = readl_relaxed(bank0->reg_drv_bank0 + i);
 398                         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "DRV_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_drv_bank0, i, value);
 399                 }
 400
 401                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 402                                 "=================================\n\n");
 403         }
 404
 405
 406         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 407                         "rockchip pinctrl GRF registers:\n");
 408         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 409                         "=================================\n");
 410
 411
 412         for(i=0; i<0x400; i=i+4)
 413         {
 414                 value = readl_relaxed(info->reg_base + i);
 415                 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "GRF[0x%p+0x%x]=0x%08x\n",(int *)info->reg_base, i, value);
 416         }
 417
 418         len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
 419                         "=================================\n\n");
 420
 421         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 422         kfree(buf);
 423
 424         return ret;
 425 }
 426
 427 static const struct file_operations pinctrl_regs_ops = {
 428         .owner          = THIS_MODULE,
 429         .open           = simple_open,
 430         .read           = pinctrl_show_regs,
 431         .write          = pinctrl_write_proc_data,
 432         .llseek         = default_llseek,
 433 };
 434
 435 static int pinctrl_debugfs_init(struct rockchip_pinctrl *info)
 436 {
 437         info->debugfs = debugfs_create_dir("rockchip_pinctrl", NULL);
 438         if (!info->debugfs)
 439                 return -ENOMEM;
 440
 441         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 442                 info->debugfs, (void *)info, &pinctrl_regs_ops);
 443         return 0;
 444 }
 445
 446 #if 0
 447 static void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
 448 {
 449         if (info->debugfs)
 450                 debugfs_remove_recursive(info->debugfs);
 451 }
 452 #endif
 453
 454 #else
 455 static inline int pinctrl_debugfs_init(struct rockchip_pinctrl*info)
 456 {
 457         return 0;
 458 }
 459
 460 #if 0
 461 static inline void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
 462 {
 463 }
 464 #endif
 465 #endif /* CONFIG_DEBUG_FS */
 466
 467
 468 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 469 {
 470         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 471 }
 472
 473 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 474                                         const struct rockchip_pinctrl *info,
 475                                         const char *name)
 476 {
 477         int i;
 478
 479         for (i = 0; i < info->ngroups; i++) {
 480                 if (!strcmp(info->groups[i].name, name))
 481                         return &info->groups[i];
 482         }
 483
 484         return NULL;
 485 }
 486
 487 /*
 488  * given a pin number that is local to a pin controller, find out the pin bank
 489  * and the register base of the pin bank.
 490  */
 491 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 492                                                                 unsigned pin)
 493 {
 494         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 495
 496         while (pin >= (b->pin_base + b->nr_pins))
 497                 b++;
 498
 499         return b;
 500 }
 501
 502 static struct rockchip_pin_bank *bank_num_to_bank(
 503                                         struct rockchip_pinctrl *info,
 504                                         unsigned num)
 505 {
 506         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 507         int i;
 508
 509         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 510                 if (b->bank_num == num)
 511                         return b;
 512         }
 513
 514         return ERR_PTR(-EINVAL);
 515 }
 516
 517 /*
 518  * Pinctrl_ops handling
 519  */
 520
 521 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 522 {
 523         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 524
 525         return info->ngroups;
 526 }
 527
 528 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 529                                                         unsigned selector)
 530 {
 531         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 532
 533         return info->groups[selector].name;
 534 }
 535
 536 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 537                                       unsigned selector, const unsigned **pins,
 538                                       unsigned *npins)
 539 {
 540         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 541
 542         if (selector >= info->ngroups)
 543                 return -EINVAL;
 544
 545         *pins = info->groups[selector].pins;
 546         *npins = info->groups[selector].npins;
 547
 548         return 0;
 549 }
 550
 551 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 552                                  struct device_node *np,
 553                                  struct pinctrl_map **map, unsigned *num_maps)
 554 {
 555         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 556         const struct rockchip_pin_group *grp;
 557         struct pinctrl_map *new_map;
 558         struct device_node *parent;
 559         int map_num = 1;
 560         int i;
 561
 562         /*
 563          * first find the group of this node and check if we need to create
 564          * config maps for pins
 565          */
 566         grp = pinctrl_name_to_group(info, np->name);
 567         if (!grp) {
 568                 dev_err(info->dev, "unable to find group for node %s\n",
 569                         np->name);
 570                 return -EINVAL;
 571         }
 572
 573         map_num += grp->npins;
 574         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 575                                                                 GFP_KERNEL);
 576         if (!new_map)
 577                 return -ENOMEM;
 578
 579         *map = new_map;
 580         *num_maps = map_num;
 581
 582         /* create mux map */
 583         parent = of_get_parent(np);
 584         if (!parent) {
 585                 devm_kfree(pctldev->dev, new_map);
 586                 return -EINVAL;
 587         }
 588         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 589         new_map[0].data.mux.function = parent->name;
 590         new_map[0].data.mux.group = np->name;
 591         of_node_put(parent);
 592
 593         /* create config map */
 594         new_map++;
 595         for (i = 0; i < grp->npins; i++) {
 596                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 597                 new_map[i].data.configs.group_or_pin = grp->name;
 598                                 //pin_get_name(pctldev, grp->pins[i]);
 599                 new_map[i].data.configs.configs = grp->data[i].configs;
 600                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 601         }
 602
 603         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 604                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 605
 606         return 0;
 607 }
 608
 609 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 610                                     struct pinctrl_map *map, unsigned num_maps)
 611 {
 612 }
 613
 614 static const struct pinctrl_ops rockchip_pctrl_ops = {
 615         .get_groups_count       = rockchip_get_groups_count,
 616         .get_group_name         = rockchip_get_group_name,
 617         .get_group_pins         = rockchip_get_group_pins,
 618         .dt_node_to_map         = rockchip_dt_node_to_map,
 619         .dt_free_map            = rockchip_dt_free_map,
 620 };
 621
 622
 623 #define RK3288_GRF_GPIO1A_IOMUX         0x0000
 624 #define RK3288_GRF_GPIO5A_IOMUX         0x004C
 625
 626 static int rk32_iomux_bit_op(struct rockchip_pin_bank *bank, int pin, int mux, void __iomem *reg, int bits)
 627 {
 628         u32 data = 0,result;
 629         u8 bit;
 630         unsigned long flags;
 631         struct rockchip_pinctrl *info = bank->drvdata;
 632
 633         if(bits == 2)
 634         {
 635                 reg += (pin / 8) * 4;
 636                 bit = (pin % 8) * 2;
 637
 638                 spin_lock_irqsave(&bank->slock, flags);
 639                 if(bank->bank_num == 0)
 640                 {
 641                         data = readl_relaxed(reg);
 642                         data &= ~(3<<bit);
 643                         data |= (mux & 3) << bit;
 644                         writel(data, reg);
 645                 }
 646                 else
 647                 {
 648                         data = (3 << (bit + 16));
 649                         data |= (mux & 3) << bit;
 650                         writel(data, reg);
 651                 }
 652
 653                 spin_unlock_irqrestore(&bank->slock, flags);
 654
 655         }
 656         else if(bits == 4)
 657         {
 658                 reg += (pin / 4) * 4;
 659                 bit = (pin % 4) * 4;
 660
 661                 spin_lock_irqsave(&bank->slock, flags);
 662                 if(bank->bank_num == 0)
 663                 {
 664                         data = readl_relaxed(reg);
 665                         data &= ~(0x0f<<bit);
 666                         data |= (mux & 0x0f) << bit;
 667                         writel(data, reg);
 668                 }
 669                 else
 670                 {
 671                         data = (0x0f << (bit + 16));
 672                         data |= (mux & 0x0f) << bit;
 673                         writel(data, reg);
 674                 }
 675
 676                 spin_unlock_irqrestore(&bank->slock, flags);
 677         }
 678         else
 679         {
 680                 printk("%s:unknow bits %d\n",__func__, bits);
 681         }
 682
 683
 684         result = readl_relaxed(reg);
 685         if(bank->bank_num == 0)
 686         DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - bank->reg_mux_bank0, data, result);
 687         else
 688         DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - info->reg_base, data, result);
 689
 690         return 0;
 691
 692 }
 693
 694
 695 static int rockchip_set_rk32_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 696 {
 697         struct rockchip_pinctrl *info = bank->drvdata;
 698         void __iomem *reg = info->reg_mux;
 699         struct union_mode m;
 700         u8 bits = 0;
 701
 702         m.mode = mux;
 703
 704         if((m.mux.bank != bank->bank_num))
 705         {
 706                 printk("%s:error:mux_bank(%d) != gpio_bank(%d)\n",__func__, m.mux.bank, bank->bank_num);
 707                 return 0;
 708         }
 709
 710         switch(bank->bank_num)
 711         {
 712                 case 0:
 713                 //pmu
 714                 reg = bank->reg_mux_bank0;
 715                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 716                 {
 717                         bits = 2;
 718                 }
 719                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 720                 break;
 721
 722                 case 1:
 723                 reg += RK3288_GRF_GPIO1A_IOMUX;
 724                 if((m.mux.goff == 0x0d))
 725                 {
 726                         bits = 2;
 727                 }
 728                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 729                 break;
 730
 731                 case 2:
 732                 reg += RK3288_GRF_GPIO2A_IOMUX;
 733                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 734                 {
 735                         bits = 2;
 736                 }
 737                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 738                 break;
 739
 740                 case 3:
 741                 reg += RK3288_GRF_GPIO3A_IOMUX;
 742                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 743                 {
 744                         bits = 2;
 745                 }
 746                 else if(m.mux.goff == 0x0d)
 747                 {
 748                         reg -= 3*4;
 749                         bits = 4;
 750                 }
 751
 752                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 753                 break;
 754
 755                 case 4:
 756                 reg += RK3288_GRF_GPIO4AL_IOMUX;
 757                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 758                 {
 759                         bits = 4;
 760                 }
 761                 else if((m.mux.goff == 0x0c) || (m.mux.goff == 0x0d))
 762                 {
 763                         reg += 2*4;
 764                         bits = 2;
 765                 }
 766
 767                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 768
 769                 break;
 770
 771                 case 5:
 772                 reg += RK3288_GRF_GPIO5A_IOMUX;
 773                 if((m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 774                 {
 775                         bits = 2;
 776                 }
 777
 778                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 779
 780                 break;
 781
 782                 case 6:
 783                 reg += RK3288_GRF_GPIO6A_IOMUX;
 784                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
 785                 {
 786                         bits = 2;
 787                 }
 788
 789                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 790                 break;
 791
 792                 case 7:
 793                 reg += RK3288_GRF_GPIO7A_IOMUX;
 794                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 795                 {
 796                         bits = 2;
 797                 }
 798                 else if((m.mux.goff == 0x0c))
 799                 {
 800                         reg -= 2*4;
 801                         bits = 4;
 802                 }
 803
 804                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 805                 break;
 806
 807                 case 8:
 808                 reg += RK3288_GRF_GPIO8A_IOMUX;
 809                 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
 810                 {
 811                         bits = 2;
 812                 }
 813
 814                 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
 815                 break;
 816
 817                 default:
 818                 printk("%s:unknow bank num %d\n", __func__, bank->bank_num);
 819                 break;
 820
 821         }
 822
 823         return 0;
 824
 825 }
 826
 827
 828
 829 /*
 830  * Set a new mux function for a pin.
 831  *
 832  * The register is divided into the upper and lower 16 bit. When changing
 833  * a value, the previous register value is not read and changed. Instead
 834  * it seems the changed bits are marked in the upper 16 bit, while the
 835  * changed value gets set in the same offset in the lower 16 bit.
 836  * All pin settings seem to be 2 bit wide in both the upper and lower
 837  * parts.
 838  * @bank: pin bank to change
 839  * @pin: pin to change
 840  * @mux: new mux function to set
 841  */
 842 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 843 {
 844         struct rockchip_pinctrl *info = bank->drvdata;
 845         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 846         unsigned long flags;
 847         u8 bit;
 848         u32 data;
 849         struct union_mode m;
 850
 851         /* GPIO0_C */
 852         /*GPIO0_C0 = 0x0c00, NAND_D8, */
 853         /*GPIO0_C1 = 0x0c10, NAND_D9, */
 854
 855         if(bank->bank_num == 15)
 856         {
 857                 printk("%s:warning ignore bank num %d\n",__func__, bank->bank_num);
 858                 return ;
 859         }
 860
 861         if(info->ctrl->type == RK3288)
 862         {
 863                 rockchip_set_rk32_mux(bank, pin, mux);
 864                 return;
 865         }
 866
 867         m.mode = mux;
 868
 869         if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
 870         {
 871                 printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
 872                 m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
 873                 return;
 874         }
 875
 876         if((info->ctrl->type == RK312X) && (bank->bank_num == 2) && (pin >= 20) && (pin <= 24))
 877         {
 878                 /*RK321X GPIO2C_IOMUX2 and GPIO2D_IOMUX are special */
 879                 if((pin >= 20) && (pin <= 23))
 880                 {
 881                         reg -= info->ctrl->mux_offset;
 882                         reg += 0xe8;
 883                         bit = (pin % 4) * 4;
 884                 }
 885                 else
 886                 {
 887                         reg -= info->ctrl->mux_offset;
 888                         reg += 0xd4;
 889                         bit = 12;
 890                 }
 891                 spin_lock_irqsave(&bank->slock, flags);
 892
 893                 data = (0x0f << (bit + 16));
 894                 data |= (mux & 0x0f) << bit;
 895                 writel(data, reg);
 896
 897                 spin_unlock_irqrestore(&bank->slock, flags);
 898
 899         }
 900
 901         else
 902         {
 903                 /* get basic quadrupel of mux registers and the correct reg inside */
 904                 reg += bank->bank_num * 0x10;
 905                 reg += (pin / 8) * 4;
 906                 bit = (pin % 8) * 2;
 907
 908                 spin_lock_irqsave(&bank->slock, flags);
 909
 910                 data = (3 << (bit + 16));
 911                 data |= (mux & 3) << bit;
 912                 writel(data, reg);
 913
 914                 spin_unlock_irqrestore(&bank->slock, flags);
 915         }
 916
 917         DBG_PINCTRL("%s:setting GPIO%d-%d to mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
 918
 919         //DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
 920 }
 921
 922
 923 /*
 924  * Pinmux_ops handling
 925  */
 926
 927 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 928 {
 929         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 930
 931         return info->nfunctions;
 932 }
 933
 934 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 935                                           unsigned selector)
 936 {
 937         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 938
 939         return info->functions[selector].name;
 940 }
 941
 942 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 943                                 unsigned selector, const char * const **groups,
 944                                 unsigned * const num_groups)
 945 {
 946         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 947
 948         *groups = info->functions[selector].groups;
 949         *num_groups = info->functions[selector].ngroups;
 950
 951         return 0;
 952 }
 953
 954 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 955                                                             unsigned group)
 956 {
 957         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 958         const unsigned int *pins = info->groups[group].pins;
 959         const struct rockchip_pin_config *data = info->groups[group].data;
 960         struct rockchip_pin_bank *bank;
 961         int cnt;
 962         int pin;
 963
 964         /*
 965          * for each pin in the pin group selected, program the correspoding pin
 966          * pin function number in the config register.
 967          */
 968         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 969                 bank = pin_to_bank(info, pins[cnt]);
 970                 pin = pins[cnt];
 971                 DBG_PINCTRL("%s:enable function %s group %s\n",
 972                 __func__, info->functions[selector].name, info->groups[group].name);
 973                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 974                                  data[cnt].func);
 975         }
 976
 977         return 0;
 978 }
 979
 980 #if 0
 981 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 982                                         unsigned selector, unsigned group)
 983 {
 984         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 985         const unsigned int *pins = info->groups[group].pins;
 986         const struct rockchip_pin_config *data = info->groups[group].data;
 987         struct rockchip_pin_bank *bank;
 988         int cnt;
 989         int pin;
 990
 991         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 992                 bank = pin_to_bank(info, pins[cnt]);
 993                 pin = pins[cnt];
 994                 DBG_PINCTRL("%s:disable function %s group %s\n",
 995                 __func__, info->functions[selector].name, info->groups[group].name);
 996                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, FUNC_TO_GPIO(data[cnt].func));
 997         }
 998 }
 999 #endif
1000
1001 /*
1002  * The calls to gpio_direction_output() and gpio_direction_input()
1003  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1004  * function called from the gpiolib interface).
1005  */
1006 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1007                                               struct pinctrl_gpio_range *range,
1008                                               unsigned offset, bool input)
1009 {
1010         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1011         struct rockchip_pin_bank *bank;
1012         struct gpio_chip *chip;
1013         int pin;
1014         u32 data, result;
1015         u32 mux;
1016
1017         chip = range->gc;
1018         bank = gc_to_pin_bank(chip);
1019         pin = offset - chip->base;
1020
1021         mux = (bank->bank_num << 12) | (((pin / 8) + 0x0A) << 8) | ((pin % 8)<< 4) | RK_FUNC_GPIO;
1022
1023         rockchip_set_mux(bank, pin, mux);
1024
1025         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1026         /* set bit to 1 for output, 0 for input */
1027         if (!input)
1028                 data |= BIT(pin);
1029         else
1030                 data &= ~BIT(pin);
1031         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1032
1033         result = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1034
1035         DBG_PINCTRL("%s:gpio_direction for pin %u as %s-%d to %s,data=0x%x,result=0x%x\n",
1036                          __func__, offset, range->name, pin, input ? "input" : "output", data, result);
1037         return 0;
1038 }
1039
1040 static const struct pinmux_ops rockchip_pmx_ops = {
1041         .get_functions_count    = rockchip_pmx_get_funcs_count,
1042         .get_function_name      = rockchip_pmx_get_func_name,
1043         .get_function_groups    = rockchip_pmx_get_groups,
1044         .enable                 = rockchip_pmx_enable,
1045         //.disable              = rockchip_pmx_disable,
1046         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1047 };
1048
1049
1050
1051 /*
1052  * Hardware access
1053  */
1054
1055 static struct func_to_reg_offset rk3188_func_to_drv_reg_offset[] =
1056 {
1057         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL",  "reserve" ,"NULL", RK3188_GRF_IO_CON0, 0 ,3),
1058         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 2, 3),
1059         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 4 ,3),
1060         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_d" ,"NULL", RK3188_GRF_IO_CON0, 6 ,3),
1061         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio1_uart0" ,"NULL", RK3188_GRF_IO_CON0, 8 ,3),
1062         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_uart1" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1063         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_spi0" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1064         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "gpio1_uart2" ,"NULL", RK3188_GRF_IO_CON0, 12 ,3),
1065         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_uart3" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1066         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_spi1" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1067         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_gps" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1068
1069         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 0 ,3),
1070         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 2 ,3),
1071         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_c" ,"NULL", RK3188_GRF_IO_CON1, 4 ,3),
1072         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c0" ,"NULL", RK3188_GRF_IO_CON1, 6 ,3),
1073         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c1" ,"NULL", RK3188_GRF_IO_CON1, 8 ,3),
1074         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c2" ,"NULL", RK3188_GRF_IO_CON1, 10 ,3),
1075         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2c4" ,"NULL", RK3188_GRF_IO_CON1, 12 ,3),
1076         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON1, 14 ,3),
1077
1078         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON2, 0 ,3),
1079         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_smc" ,"NULL", RK3188_GRF_IO_CON2, 2 ,3),
1080         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON2, 4 ,3),
1081         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1082         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1083         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1084         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1085         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_b" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1086         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_i2c3" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1087         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 12 ,3),
1088         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 14 ,3),
1089
1090         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 0 ,3),
1091         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 2 ,3),
1092         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_pwm" ,"NULL", RK3188_GRF_IO_CON3, 4 ,3),
1093         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_d" ,"NULL", RK3188_GRF_IO_CON3, 6 ,3),
1094         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 8 ,3),
1095         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 10 ,3),
1096         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "cif" ,"NULL", RK3188_GRF_IO_CON3, 12 ,3),
1097         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON3, 14 ,3),
1098
1099         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON4, 0 ,3),
1100         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "jtag" ,"NULL", RK3188_GRF_IO_CON4, 2 ,3),
1101         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "misc" ,"NULL", RK3188_GRF_IO_CON4, 4 ,3),
1102         FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON4, 6 ,3),
1103
1104 };
1105
1106 static struct func_to_reg_offset rk3188_func_to_vol_reg_offset[] =
1107 {
1108         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap0-vcc", "vol_domain", "ap0-vcc", RK3188_GRF_IO_CON4, 8 ,1),
1109         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap1-vcc", "vol_domain", "ap1-vcc", RK3188_GRF_IO_CON4, 9 ,1),
1110         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "cif-vcc", "vol_domain", "cif-vcc", RK3188_GRF_IO_CON4, 10 ,1),
1111         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash-vcc", "vol_domain", "flash-vcc", RK3188_GRF_IO_CON4, 11 ,1),
1112         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio0-vcc", "vol_domain", "vccio0-vcc", RK3188_GRF_IO_CON4, 12 ,1),
1113         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio1-vcc", "vol_domain", "vccio1-vcc", RK3188_GRF_IO_CON4, 13 ,1),
1114         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc0-vcc", "vol_domain", "lcdc0-vcc", RK3188_GRF_IO_CON4, 14 ,1),
1115         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1-vcc", "vol_domain", "lcdc1-vcc", RK3188_GRF_IO_CON4, 15 ,1),
1116 };
1117
1118
1119 static struct func_to_reg_offset rk3288_func_to_vol_reg_offset[] =
1120 {
1121         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc-vcc", "vol_domain", "lcdc-vcc", RK3288_GRF_IO_VSEL, 0 ,1),
1122         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "dvp-vcc", "vol_domain", "dvp-vcc", RK3288_GRF_IO_VSEL, 1 ,1),
1123         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash0-vcc", "vol_domain", "flash0-vcc", RK3288_GRF_IO_VSEL, 2 ,1),
1124         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash1-vcc", "vol_domain", "flash1-vcc", RK3288_GRF_IO_VSEL, 3 ,1),
1125         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "wifi-vcc", "vol_domain", "wifi-vcc", RK3288_GRF_IO_VSEL, 4 ,1),
1126         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "bb-vcc", "vol_domain", "bb-vcc", RK3288_GRF_IO_VSEL, 5 ,1),
1127         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "audio-vcc", "vol_domain", "audio-vcc", RK3288_GRF_IO_VSEL, 6 ,1),
1128         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "sdcard-vcc", "vol_domain", "sdcard-vcc", RK3288_GRF_IO_VSEL, 7 ,1),
1129
1130         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio30-vcc", "vol_domain", "gpio30-vcc", RK3288_GRF_IO_VSEL, 8 ,1),
1131         FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio1830-vcc", "vol_domain", "gpio1830-vcc", RK3288_GRF_IO_VSEL, 9 ,1),
1132 };
1133
1134
1135 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1136                                     int pin_num, void __iomem **reg, u8 *bit)
1137 {
1138         struct rockchip_pinctrl *info = bank->drvdata;
1139         void __iomem *reg_base;
1140         int pin = pin_num;
1141
1142         *reg = info->reg_base + RK2928_PULL_OFFSET;
1143         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1144         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1145
1146         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1147
1148         reg_base = info->reg_base;
1149
1150         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1151 };
1152
1153
1154 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1155                                     int pin_num, void __iomem **reg, u8 *bit)
1156 {
1157         struct rockchip_pinctrl *info = bank->drvdata;
1158         void __iomem *reg_base;
1159         int pin = pin_num;
1160
1161         /* The first 12 pins of the first bank are located elsewhere */
1162         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
1163                 *reg = bank->reg_pull_bank0 +
1164                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1165                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1166                 *bit *= RK3188_PULL_BITS_PER_PIN;
1167                 reg_base = bank->reg_pull_bank0;
1168         } else {
1169                 *reg = info->reg_pull - 4;
1170                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1171                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1172
1173                 /*
1174                  * The bits in these registers have an inverse ordering
1175                  * with the lowest pin being in bits 15:14 and the highest
1176                  * pin in bits 1:0
1177                  */
1178                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1179                 *bit *= RK3188_PULL_BITS_PER_PIN;
1180                 reg_base = info->reg_pull - 4;
1181         }
1182
1183         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1184 }
1185
1186 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1187                                     int pin_num, void __iomem **reg, u8 *bit)
1188 {
1189         struct rockchip_pinctrl *info = bank->drvdata;
1190         void __iomem *reg_base;
1191         int pin = pin_num;
1192
1193         /* The first 24 pins of the first bank are located elsewhere */
1194         if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1195                 *reg = bank->reg_pull_bank0 +
1196                                 ((pin_num / 8) * 4);
1197                 *bit = pin_num % 8;
1198                 *bit *= 2;
1199                 reg_base = bank->reg_pull_bank0;
1200         } else {
1201                 *reg = info->reg_pull - 0x10;
1202                 *reg += bank->bank_num * 0x10;
1203                 *reg += ((pin_num / 8) * 4);
1204
1205                 *bit = (pin_num % 8);
1206                 *bit *= 2;
1207                 reg_base = info->reg_pull - 0x10;
1208         }
1209
1210         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1211 }
1212
1213
1214 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1215                                     int pin_num, void __iomem **reg, u8 *bit)
1216 {
1217         struct rockchip_pinctrl *info = bank->drvdata;
1218         void __iomem *reg_base;
1219         int pin = pin_num;
1220
1221         /* The first 24 pins of the first bank are located elsewhere */
1222         if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1223                 *reg = bank->reg_drv_bank0 +
1224                                 ((pin_num / 8) * 4);
1225                 *bit = pin_num % 8;
1226                 *bit *= 2;
1227
1228                 reg_base = bank->reg_drv_bank0;
1229         } else {
1230                 *reg = info->reg_drv - 0x10;
1231                 *reg += bank->bank_num * 0x10;
1232                 *reg += ((pin_num / 8) * 4);
1233
1234                 *bit = (pin_num % 8);
1235                 *bit *= 2;
1236
1237                 reg_base = info->reg_drv - 0x10;
1238         }
1239
1240         DBG_PINCTRL("%s:GPIO%d-%d, drv_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1241 }
1242
1243
1244 static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1245                                     int pin_num, void __iomem **reg, u8 *bit)
1246 {
1247         struct rockchip_pinctrl *info = bank->drvdata;
1248         void __iomem *reg_base;
1249         int pin = pin_num;
1250
1251         *reg = info->reg_pull;
1252         *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
1253         *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
1254
1255         *bit = pin_num % RK3036_PULL_PINS_PER_REG;
1256
1257         reg_base = info->reg_pull;
1258
1259         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1260 }
1261
1262
1263 static void rk312x_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1264                                     int pin_num, void __iomem **reg, u8 *bit)
1265 {
1266         struct rockchip_pinctrl *info = bank->drvdata;
1267         void __iomem *reg_base;
1268         int pin = pin_num;
1269
1270         *reg = info->reg_pull;
1271         *reg += bank->bank_num * RK312X_PULL_BANK_STRIDE;
1272         *reg += (pin_num / RK312X_PULL_PINS_PER_REG) * 4;
1273
1274         *bit = pin_num % RK312X_PULL_PINS_PER_REG;
1275
1276         reg_base = info->reg_pull;
1277
1278         DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1279 }
1280
1281
1282
1283
1284 #if 0
1285 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1286 {
1287         struct rockchip_pinctrl *info = bank->drvdata;
1288         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1289         void __iomem *reg;
1290         u8 bit;
1291         u32 data;
1292         int pin = pin_num;
1293
1294         /* rk3066b does support any pulls */
1295         if (ctrl->type == RK3066B)
1296                 return PIN_CONFIG_BIAS_DISABLE;
1297
1298         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
1299
1300         switch (ctrl->type) {
1301         case RK2928:
1302                 return !(readl_relaxed(reg) & BIT(bit))
1303                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1304                                 : PIN_CONFIG_BIAS_DISABLE;
1305         case RK3188:
1306         case RK3288:
1307                 data = readl_relaxed(reg) >> bit;
1308                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1309
1310                 switch (data) {
1311                 case 0:
1312                         return PIN_CONFIG_BIAS_DISABLE;
1313                 case 1:
1314                         return PIN_CONFIG_BIAS_PULL_UP;
1315                 case 2:
1316                         return PIN_CONFIG_BIAS_PULL_DOWN;
1317                 case 3:
1318                         return PIN_CONFIG_BIAS_BUS_HOLD;
1319                 }
1320
1321                 dev_err(info->dev, "unknown pull setting\n");
1322                 return -EIO;
1323         default:
1324                 dev_err(info->dev, "unsupported pinctrl type\n");
1325                 return -EINVAL;
1326         };
1327
1328         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1329 }
1330 #endif
1331
1332 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1333                                         int pin_num, int pull)
1334 {
1335         struct rockchip_pinctrl *info = bank->drvdata;
1336         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1337         void __iomem *reg;
1338         unsigned long flags;
1339         u8 bit;
1340         u32 data;
1341         int pin = pin_num;
1342
1343
1344         /* rk3066b does support any pulls */
1345         if (ctrl->type == RK3066B)
1346                 return pull ? -EINVAL : 0;
1347
1348         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
1349
1350         switch (ctrl->type) {
1351         case RK2928:
1352         case RK3036:
1353         case RK312X:
1354                 spin_lock_irqsave(&bank->slock, flags);
1355
1356                 data = BIT(bit + 16);
1357                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1358                         data |= BIT(bit);
1359
1360                 if(pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
1361                 writel(data, reg);
1362
1363                 spin_unlock_irqrestore(&bank->slock, flags);
1364                 break;
1365         case RK3188:
1366         case RK3288:
1367                 spin_lock_irqsave(&bank->slock, flags);
1368
1369                 /* enable the write to the equivalent lower bits,
1370                  * but gpio0 has not the write_enable bit.
1371                  */
1372                 if (bank->bank_num == 0) {
1373                         data = readl_relaxed(reg);
1374                         data &= ~(3 << bit);
1375                 } else
1376                         data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1377
1378                 switch (pull) {
1379                 case PIN_CONFIG_BIAS_DISABLE:
1380                         break;
1381                 case PIN_CONFIG_BIAS_PULL_UP:
1382                         data |= (1 << bit);
1383                         break;
1384                 case PIN_CONFIG_BIAS_PULL_DOWN:
1385                         data |= (2 << bit);
1386                         break;
1387                 case PIN_CONFIG_BIAS_BUS_HOLD:
1388                         data |= (3 << bit);
1389                         break;
1390                 default:
1391                         dev_err(info->dev, "unsupported pull setting %d\n",
1392                                 pull);
1393                         return -EINVAL;
1394                 }
1395
1396                 writel(data, reg);
1397
1398                 spin_unlock_irqrestore(&bank->slock, flags);
1399                 break;
1400         default:
1401                 dev_err(info->dev, "unsupported pinctrl type\n");
1402                 return -EINVAL;
1403         }
1404
1405
1406         DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1407
1408         return 0;
1409 }
1410
1411 /*
1412  * Pinconf_ops handling
1413  */
1414
1415 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1416                                         enum pin_config_param pull)
1417 {
1418         switch (ctrl->type) {
1419         case RK2928:
1420         case RK3036:
1421         case RK312X:
1422                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1423                                         pull == PIN_CONFIG_BIAS_DISABLE);
1424         case RK3066B:
1425                 return pull ? false : true;
1426         case RK3188:
1427                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1428         case RK3288:
1429                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1430         }
1431
1432         return false;
1433 }
1434
1435 #if 0
1436 static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank,
1437                                         int pin_num, unsigned long *config, int config_type, unsigned group)
1438 {
1439         struct rockchip_pinctrl *info = bank->drvdata;
1440         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1441         struct func_to_reg_offset reg_offset[4];//same name count should be less four
1442         struct func_to_reg_offset *func_to_reg;
1443         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1444         int data = 0;
1445         u8 bit;
1446         unsigned long flags;
1447         void __iomem *reg;
1448         int pin = pin_num;
1449
1450
1451         if(group < 0)
1452                 return -1;
1453
1454         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1455
1456         switch(ctrl->type)
1457         {
1458                 case RK2928:
1459                 //to do
1460                 break;
1461
1462                 case RK3066B:
1463
1464                 break;
1465
1466                 case RK3188:
1467
1468                 switch(config_type)
1469                 {
1470                         case TYPE_PULL_REG:
1471                         //compare pin num
1472
1473                         break;
1474
1475                         case TYPE_VOL_REG:
1476                         //compare group_name
1477                         func_to_reg = rk3188_func_to_vol_reg_offset;
1478                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1479                         for(i = 0; i < num; i++)
1480                         {
1481                                 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1482                                 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1483                                 {
1484                                         reg_offset[j++] = func_to_reg[i];
1485                                         DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1486                                 }
1487                         }
1488
1489                         if(j == 0)
1490                         {
1491                                 func_to_reg = rk3188_func_to_drv_reg_offset;
1492                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1493                                 for(i = 0; i < num; i++)
1494                                 {
1495                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1496                                         {
1497
1498                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
1499                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1500                                                 for(ii = 0; ii < num; ii++)
1501                                                 {
1502                                                         if(!strcmp(func_to_reg[i].vol_name, func_to_reg[ii].group_name))
1503                                                         {
1504                                                                 reg_offset[jj++] = func_to_reg[ii];
1505                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1506                                                         }
1507                                                 }
1508
1509                                         }
1510                                 }
1511
1512
1513                                 j = jj;
1514
1515                         }
1516
1517
1518                         break;
1519
1520                         case TYPE_DRV_REG:
1521                         //compare func_name
1522                         func_to_reg = rk3188_func_to_drv_reg_offset;
1523                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1524                         for(i = 0; i < num; i++)
1525                         {
1526                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1527                                 {
1528                                         reg_offset[j++] = func_to_reg[i];
1529                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1530                                 }
1531                         }
1532
1533                         break;
1534
1535                         case TYPE_TRI_REG:
1536                         break;
1537
1538                         default:
1539                         break;
1540
1541                 }
1542
1543                 break;
1544
1545                 case RK3288:
1546
1547                 switch(config_type)
1548                 {
1549                         case TYPE_VOL_REG:
1550                                 //compare group_name
1551                                 func_to_reg = rk3288_func_to_vol_reg_offset;
1552                                 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1553                                 for(i = 0; i < num; i++)
1554                                 {
1555                                         //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1556                                         if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1557                                         {
1558                                                 reg_offset[j++] = func_to_reg[i];
1559                                                 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1560                                         }
1561                                 }
1562
1563                                 break;
1564
1565                         case TYPE_DRV_REG:
1566
1567                                 ctrl->drv_calc_reg(bank, pin_num, &reg, &bit);
1568
1569                                 data = readl_relaxed(reg) >> bit;
1570                                 data &= (1 << 2) - 1;
1571
1572                                 *config = data;
1573
1574                                 break;
1575                         default:
1576                                 break;
1577
1578                 }
1579
1580                 break;
1581
1582                 default:
1583                 break;
1584         }
1585
1586
1587         if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1588         {
1589                 if(j <= 0)
1590                 {
1591                         printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1592                         return -1;
1593                 }
1594
1595
1596                 for(i=0; i < j; i++)
1597                 {
1598                         reg = info->reg_base + reg_offset[i].reg_offset;
1599                         spin_lock_irqsave(&bank->slock, flags);
1600                         data = readl_relaxed(reg) >> reg_offset[i].bit_offset;
1601                         data &= reg_offset[i].bit_mask;
1602                         spin_unlock_irqrestore(&bank->slock, flags);
1603
1604                         *config = data;
1605
1606                         DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data);
1607                 }
1608
1609         }
1610         else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1611         {
1612                 DBG_PINCTRL("%s:GPIO-%d %d drv=0x%x\n",__func__, bank->bank_num, pin_num, (u32)*config);
1613         }
1614
1615         return 0;
1616 }
1617 #endif
1618
1619
1620 static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank,
1621                                         int pin_num, int arg, int config_type, unsigned group)
1622 {
1623         struct rockchip_pinctrl *info = bank->drvdata;
1624         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1625         struct func_to_reg_offset reg_offset[4];//same name count should be less four
1626         struct func_to_reg_offset *func_to_reg;
1627         int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1628         int data = 0, value = 0;
1629         u8 bit;
1630         unsigned long flags;
1631         void __iomem *reg;
1632         int pin = pin_num;
1633
1634
1635         if(group < 0)
1636                 return -1;
1637
1638         DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1639
1640         switch(ctrl->type)
1641         {
1642                 case RK2928:
1643                 //to do
1644                 break;
1645
1646                 case RK3066B:
1647
1648                 break;
1649
1650                 case RK3188:
1651
1652                 switch(config_type)
1653                 {
1654                         case TYPE_PULL_REG:
1655                         //compare pin num
1656
1657                         break;
1658
1659                         case TYPE_VOL_REG:
1660                         //compare group_name
1661                         func_to_reg = rk3188_func_to_vol_reg_offset;
1662                         num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1663                         for(i = 0; i < num; i++)
1664                         {
1665                                 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1666                                 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1667                                 {
1668                                         reg_offset[j++] = func_to_reg[i];
1669                                         DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1670                                 }
1671                         }
1672
1673                         if(j == 0)
1674                         {
1675                                 func_to_reg = rk3188_func_to_drv_reg_offset;
1676                                 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1677                                 for(i = 0; i < num; i++)
1678                                 {
1679                                         if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1680                                         {
1681
1682                                                 func_to_reg = rk3188_func_to_vol_reg_offset;
1683                                                 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1684                                                 for(ii = 0; ii < num; ii++)
1685                                                 {
1686                                                         if(!strcmp(rk3188_func_to_drv_reg_offset[i].vol_name, func_to_reg[ii].group_name))
1687                                                         {
1688                                                                 reg_offset[jj++] = func_to_reg[ii];
1689                                                                 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1690                                                         }
1691                                                 }
1692
1693                                         }
1694                                 }
1695
1696
1697                                 j = jj;
1698
1699                         }
1700
1701
1702                         break;
1703
1704                         case TYPE_DRV_REG:
1705                         //compare func_name
1706                         func_to_reg = rk3188_func_to_drv_reg_offset;
1707                         num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1708                         for(i = 0; i < num; i++)
1709                         {
1710                                 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1711                                 {
1712                                         reg_offset[j++] = func_to_reg[i];
1713                                         DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1714                                 }
1715                         }
1716
1717                         break;
1718
1719                         case TYPE_TRI_REG:
1720                         break;
1721
1722                         default:
1723                         break;
1724
1725                 }
1726
1727                 break;
1728
1729                 case RK3288:
1730
1731                 switch(config_type)
1732                 {
1733                         case TYPE_VOL_REG:
1734                                 //compare group_name
1735                                 func_to_reg = rk3288_func_to_vol_reg_offset;
1736                                 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1737                                 for(i = 0; i < num; i++)
1738                                 {
1739                                         //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1740                                         if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1741                                         {
1742                                                 reg_offset[j++] = func_to_reg[i];
1743                                                 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1744                                         }
1745                                 }
1746
1747                                 break;
1748
1749                         case TYPE_DRV_REG:
1750
1751                                 ctrl->drv_calc_reg(bank, pin_num, &reg, &bit);
1752
1753                                 spin_lock_irqsave(&bank->slock, flags);
1754
1755                                 if (bank->bank_num == 0) {
1756                                         data = readl_relaxed(reg);
1757                                         data &= ~(3<<bit);
1758                                         data |= arg << bit;
1759                                 } else {
1760                                         data = arg << bit;
1761                                         data |= (3<<(bit+16));
1762                                 }
1763
1764                                 writel_relaxed(data, reg);
1765                                 spin_unlock_irqrestore(&bank->slock, flags);
1766
1767                                 break;
1768                         default:
1769                                 break;
1770
1771                 }
1772
1773                 break;
1774
1775                 case RK3036:
1776
1777                 switch(config_type)
1778                 {
1779                         case TYPE_DRV_REG:
1780
1781                                 if((bank->bank_num == 1) && (pin_num >= 0) && (pin_num <= 3))
1782                                 {
1783                                         bit = pin_num*2 + 4;
1784                                         reg = info->reg_drv;
1785                                         spin_lock_irqsave(&bank->slock, flags);
1786
1787                                         data = arg << bit;
1788                                         data &= (3<<bit);
1789                                         data |= (3<<(bit+16));
1790
1791                                         writel_relaxed(data, reg);
1792                                         spin_unlock_irqrestore(&bank->slock, flags);
1793                                 }
1794                                 else
1795                                 {
1796                                         printk("%s:RK3036 GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1797                                 }
1798                                 break;
1799                         default:
1800                                 break;
1801
1802                 }
1803
1804                 break;
1805
1806                 case RK312X:
1807
1808                 switch(config_type)
1809                 {
1810                         case TYPE_DRV_REG:
1811
1812                                 if((bank->bank_num == 0)&&((pin_num == GPIO_A6)|| (pin_num == GPIO_A7)||(pin_num == GPIO_B7)||(pin_num == GPIO_C4)))
1813                                 {
1814                                         if(pin_num == GPIO_A6)
1815                                         bit = 4;
1816                                         else if(pin_num == GPIO_A7)
1817                                         bit = 6;
1818                                         else if(pin_num == GPIO_B7)
1819                                         bit = 8;
1820                                         else if(pin_num == GPIO_C4)
1821                                         bit = 10;
1822
1823                                         reg = info->reg_drv;
1824                                         spin_lock_irqsave(&bank->slock, flags);
1825
1826                                         data = arg << bit;
1827                                         data &= (3<<bit);
1828                                         data |= (3<<(bit+16));
1829
1830                                         writel_relaxed(data, reg);
1831                                         spin_unlock_irqrestore(&bank->slock, flags);
1832                                 }
1833                                 else
1834                                 {
1835                                         printk("%s:RK312X GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1836                                 }
1837                                 break;
1838                         default:
1839                                 break;
1840
1841                 }
1842
1843                 break;
1844
1845                 default:
1846                 break;
1847         }
1848
1849
1850         if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1851         {
1852                 if(j <= 0)
1853                 {
1854                         printk("%s:could not find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1855                         return -1;
1856                 }
1857
1858                 for(i=0; i < j; i++)
1859                 {
1860                         reg = info->reg_base + reg_offset[i].reg_offset;
1861                         data |= ((reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
1862                         data |= ((arg & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
1863                         spin_lock_irqsave(&bank->slock, flags);
1864                         writel_relaxed(data, reg);
1865                         value = readl_relaxed(reg);
1866                         spin_unlock_irqrestore(&bank->slock, flags);
1867                         DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=%d,data[%d]=0x%08x,result=0x%08x,arg=%d\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data, value, arg);
1868                 }
1869
1870         }
1871
1872         else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1873         {
1874                 DBG_PINCTRL("%s:GPIO-%d %d data=0x%x,type=%d\n",__func__, bank->bank_num, pin_num, data,TYPE_DRV_REG);
1875         }
1876
1877         return 0;
1878 }
1879
1880
1881 /* set the pin config settings for a specified pin */
1882 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1883                                 unsigned long configs, unsigned group)
1884 {
1885         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1886         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1887         struct rockchip_pin_group *grp = &info->groups[group];
1888         enum pin_config_param param;
1889         u16 arg;
1890         int rc;
1891
1892
1893         param = pinconf_to_config_param(configs);
1894         arg = pinconf_to_config_argument(configs);
1895
1896         switch (param) {
1897         case PIN_CONFIG_BIAS_DISABLE:
1898                 rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1899                         param);
1900                 if (rc)
1901                         return rc;
1902                 break;
1903         case PIN_CONFIG_BIAS_PULL_UP:
1904         case PIN_CONFIG_BIAS_PULL_DOWN:
1905         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1906         case PIN_CONFIG_BIAS_BUS_HOLD:
1907                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1908                         return -ENOTSUPP;
1909
1910                 if (!arg)
1911                         return -EINVAL;
1912
1913                 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1914                         param);
1915                 if (rc)
1916                         return rc;
1917                 break;
1918
1919         case PIN_CONFIG_POWER_SOURCE:
1920                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_VOL_REG, group);
1921                 if (rc)
1922                 return rc;
1923                 break;
1924
1925         case PIN_CONFIG_DRIVE_STRENGTH:
1926                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_DRV_REG, group);
1927                 if (rc)
1928                 return rc;
1929                 break;
1930         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1931                 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_TRI_REG, group);
1932                 if (rc)
1933                 return rc;
1934                 break;
1935         default:
1936                 return -ENOTSUPP;
1937                 break;
1938         }
1939
1940         /* cache the config value for rockchip_pinconf_get() */
1941         grp->gconfigs = configs;
1942
1943         DBG_PINCTRL("%s,bank_num=%d,pin=%d,param=%d, arg=%d\n",__func__,bank->bank_num, pin, param, arg);
1944
1945         return 0;
1946 }
1947
1948 #if 0
1949 /* get the pin config settings for a specified pin */
1950 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1951                                                         unsigned long *config, unsigned group)
1952 {
1953         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1954         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1955         enum pin_config_param param = pinconf_to_config_param(*config);
1956         int rc;
1957
1958         switch (param) {
1959         case PIN_CONFIG_BIAS_DISABLE:
1960                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1961                         return -EINVAL;
1962
1963                 *config = 0;
1964                 break;
1965         case PIN_CONFIG_BIAS_PULL_UP:
1966         case PIN_CONFIG_BIAS_PULL_DOWN:
1967         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1968         case PIN_CONFIG_BIAS_BUS_HOLD:
1969                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1970                         return -ENOTSUPP;
1971
1972                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1973                         return -EINVAL;
1974
1975                 *config = 1;
1976                 break;
1977
1978         case PIN_CONFIG_POWER_SOURCE:
1979                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_VOL_REG, group);
1980                 if (rc)
1981                 return rc;
1982                 break;
1983
1984         case PIN_CONFIG_DRIVE_STRENGTH:
1985                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_DRV_REG, group);
1986                 if (rc)
1987                 return rc;
1988                 break;
1989         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1990                 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_TRI_REG, group);
1991                 if (rc)
1992                 return rc;
1993                 break;
1994
1995         default:
1996                 return -ENOTSUPP;
1997                 break;
1998         }
1999
2000
2001         DBG_PINCTRL("%s:bank_num=%d, pin=%d, param=%d\n",__func__, bank->bank_num, pin, param);
2002
2003         return 0;
2004 }
2005 #endif
2006
2007 /* set the pin config settings for a specified pin group */
2008 static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev,
2009                         unsigned group, unsigned long config)
2010 {
2011         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2012         const unsigned int *pins;
2013         unsigned int cnt;
2014         struct rockchip_pin_bank *bank;
2015         int pin;
2016
2017         pins = info->groups[group].pins;
2018
2019         for (cnt = 0; cnt < info->groups[group].npins; cnt++)
2020         {
2021                 bank = pin_to_bank(info, pins[cnt]);
2022                 pin = pins[cnt];
2023                 DBG_PINCTRL("%s:group[%d]:%s, pins[%d]=%d\n",__func__, group, info->groups[group].name, cnt, pins[cnt]);
2024                 rockchip_pinconf_set(pctldev, pins[cnt], config, group);
2025         }
2026
2027         return 0;
2028 }
2029
2030 /* get the pin config settings for a specified pin group */
2031 static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev,
2032                                 unsigned int group, unsigned long *config)
2033 {
2034         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2035         const unsigned int *pins;
2036         struct rockchip_pin_bank *bank;
2037
2038         pins = info->groups[group].pins;
2039         bank = pin_to_bank(info, pins[0]);
2040
2041         //rockchip_pinconf_get(pctldev, pins[0], config, group);
2042         *config = info->groups[group].gconfigs;
2043         if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2044         printk("%s:group[%d]:%s,config=0x%lx\n",__func__, group, info->groups[group].name, *config);
2045         return 0;
2046 }
2047
2048 static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev,
2049                                  struct seq_file *s, unsigned pin)
2050 {
2051         //to do
2052 }
2053
2054 static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
2055                                        struct seq_file *s, unsigned group)
2056 {
2057         //to do
2058 }
2059
2060
2061 static const struct pinconf_ops rockchip_pinconf_ops = {
2062         .pin_config_group_get           = rockchip_pinconf_group_get,
2063         .pin_config_group_set           = rockchip_pinconf_group_set,
2064         .pin_config_dbg_show            = rockchip_pinconf_dbg_show,
2065         .pin_config_group_dbg_show      = rockchip_pinconf_group_dbg_show,
2066 };
2067
2068 static const struct of_device_id rockchip_bank_match[] = {
2069         { .compatible = "rockchip,gpio-bank" },
2070         { .compatible = "rockchip,rk3188-gpio-bank0" },
2071         { .compatible = "rockchip,rk3288-gpio-bank0" },
2072         {},
2073 };
2074
2075 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2076                                                 struct device_node *np)
2077 {
2078         struct device_node *child;
2079
2080         for_each_child_of_node(np, child) {
2081                 if (of_match_node(rockchip_bank_match, child))
2082                         continue;
2083
2084                 info->nfunctions++;
2085                 info->ngroups += of_get_child_count(child);
2086         }
2087 }
2088
2089 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2090                                               struct rockchip_pin_group *grp,
2091                                               struct rockchip_pinctrl *info,
2092                                               u32 index)
2093 {
2094         struct rockchip_pin_bank *bank;
2095         int size;
2096         const __be32 *list;
2097         int i, j;
2098         struct union_mode m;
2099         int configlen = 0;
2100         unsigned long *pinconfig;
2101         u32 val;
2102
2103         //printk("%s:group(%d): %s\n", __func__, index, np->name);
2104
2105         /* Initialise group */
2106         grp->name = np->name;
2107
2108         /*
2109          * the binding format is rockchip,pins = <mux>,
2110          * do sanity check and calculate pins number
2111          */
2112         list = of_get_property(np, "rockchip,pins", &size);
2113         /* we do not check return since it's safe node passed down */
2114         size /= sizeof(*list);
2115         if (!size || size % 1) {
2116                 dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n");
2117                 return -EINVAL;
2118         }
2119
2120         grp->npins = size / 1;
2121
2122         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2123                                                 GFP_KERNEL);
2124         grp->data = devm_kzalloc(info->dev, grp->npins *
2125                                           sizeof(struct rockchip_pin_config),
2126                                         GFP_KERNEL);
2127         if (!grp->pins || !grp->data)
2128                 return -ENOMEM;
2129
2130         pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2131
2132         for (i = 0; i < size; i++) {
2133                 m.mode = be32_to_cpu(*list++);
2134
2135                 bank = bank_num_to_bank(info, m.mux.bank);
2136                 if (IS_ERR(bank))
2137                         return PTR_ERR(bank);
2138
2139                 grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
2140                 grp->data[i].func = m.mode;
2141
2142
2143                 j = 0;
2144                 configlen = 0;
2145
2146                 if (of_find_property(np, "rockchip,pull", NULL))
2147                         configlen++;
2148                 if (of_find_property(np, "rockchip,voltage", NULL))
2149                         configlen++;
2150                 if (of_find_property(np, "rockchip,drive", NULL))
2151                         configlen++;
2152                 if (of_find_property(np, "rockchip,tristate", NULL))
2153                         configlen++;
2154
2155                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2156
2157                 if (!of_property_read_u32(np, "rockchip,pull", &val)) {
2158                         enum pin_config_param pull = PIN_CONFIG_END;
2159                         if (val == 0)
2160                                 pull = PIN_CONFIG_BIAS_DISABLE;
2161                         if (val == 1)
2162                                 pull = PIN_CONFIG_BIAS_PULL_UP;
2163                         else if (val == 2)
2164                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
2165                         else if (val == 3)
2166                                 pull = PIN_CONFIG_BIAS_BUS_HOLD;
2167                         else if (val == 4)
2168                                 pull = PIN_CONFIG_BIAS_PULL_PIN_DEFAULT;
2169
2170                         pinconfig[j++] = pinconf_to_config_packed(pull, val);
2171                 }
2172
2173                 if (!of_property_read_u32(np, "rockchip,voltage", &val)) {
2174                         pinconfig[j++] =
2175                                 pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
2176                                                          val);
2177                 }
2178
2179                 if (!of_property_read_u32(np, "rockchip,drive", &val)) {
2180                         pinconfig[j++] =
2181                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
2182                                                          val);
2183                 }
2184
2185                 if (!of_property_read_u32(np, "rockchip,tristate", &val)) {
2186                         pinconfig[j++] =
2187                                 pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
2188                                                          val);
2189                 }
2190
2191                 grp->data[i].configs = pinconfig;
2192                 grp->data[i].nconfigs = configlen;
2193
2194         }
2195
2196         return 0;
2197 }
2198
2199
2200 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2201                                                 struct rockchip_pinctrl *info,
2202                                                 u32 index)
2203 {
2204         struct device_node *child;
2205         struct rockchip_pmx_func *func;
2206         struct rockchip_pin_group *grp;
2207         int ret;
2208         static u32 grp_index;
2209         u32 i = 0;
2210
2211         //printk("%s:parse function(%d): %s\n", __func__, index, np->name);
2212
2213         func = &info->functions[index];
2214
2215         /* Initialise function */
2216         func->name = np->name;
2217         func->ngroups = of_get_child_count(np);
2218         if (func->ngroups <= 0)
2219                 return 0;
2220
2221         func->groups = devm_kzalloc(info->dev,
2222                         func->ngroups * sizeof(char *), GFP_KERNEL);
2223         if (!func->groups)
2224                 return -ENOMEM;
2225
2226         for_each_child_of_node(np, child) {
2227                 func->groups[i] = child->name;
2228                 grp = &info->groups[grp_index++];
2229                 grp->func_name = np->name;
2230                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2231                 if (ret)
2232                         return ret;
2233
2234                 //printk("%s:grp->func_name(%d): %s\n", __func__, grp_index, grp->func_name);
2235         }
2236
2237         return 0;
2238 }
2239
2240 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2241                                               struct rockchip_pinctrl *info)
2242 {
2243         struct device *dev = &pdev->dev;
2244         struct device_node *np = dev->of_node;
2245         struct device_node *child;
2246         int ret;
2247         int i;
2248
2249         rockchip_pinctrl_child_count(info, np);
2250
2251         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2252         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2253
2254         info->functions = devm_kzalloc(dev, info->nfunctions *
2255                                               sizeof(struct rockchip_pmx_func),
2256                                               GFP_KERNEL);
2257         if (!info->functions) {
2258                 dev_err(dev, "failed to allocate memory for function list\n");
2259                 return -EINVAL;
2260         }
2261
2262         info->groups = devm_kzalloc(dev, info->ngroups *
2263                                             sizeof(struct rockchip_pin_group),
2264                                             GFP_KERNEL);
2265         if (!info->groups) {
2266                 dev_err(dev, "failed allocate memory for ping group list\n");
2267                 return -EINVAL;
2268         }
2269
2270         i = 0;
2271
2272         for_each_child_of_node(np, child) {
2273                 if (of_match_node(rockchip_bank_match, child))
2274                         continue;
2275
2276                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2277                 if (ret) {
2278                         dev_err(&pdev->dev, "failed to parse function\n");
2279                         return ret;
2280                 }
2281         }
2282
2283         return 0;
2284 }
2285
2286 static int rockchip_pinctrl_register(struct platform_device *pdev,
2287                                         struct rockchip_pinctrl *info)
2288 {
2289         struct pinctrl_desc *ctrldesc = &info->pctl;
2290         struct pinctrl_pin_desc *pindesc, *pdesc;
2291         struct rockchip_pin_bank *pin_bank;
2292         int pin, bank, ret;
2293         int k;
2294
2295         ctrldesc->name = "rockchip-pinctrl";
2296         ctrldesc->owner = THIS_MODULE;
2297         ctrldesc->pctlops = &rockchip_pctrl_ops;
2298         ctrldesc->pmxops = &rockchip_pmx_ops;
2299         ctrldesc->confops = &rockchip_pinconf_ops;
2300
2301         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2302                         info->ctrl->nr_pins, GFP_KERNEL);
2303         if (!pindesc) {
2304                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2305                 return -ENOMEM;
2306         }
2307         ctrldesc->pins = pindesc;
2308         ctrldesc->npins = info->ctrl->nr_pins;
2309
2310         pdesc = pindesc;
2311         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2312                 pin_bank = &info->ctrl->pin_banks[bank];
2313                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2314                         pdesc->number = k;
2315                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2316                                                 pin_bank->name, pin);
2317                         pdesc++;
2318                 }
2319         }
2320
2321         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2322         if (!info->pctl_dev) {
2323                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2324                 return -EINVAL;
2325         }
2326
2327         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2328                 pin_bank = &info->ctrl->pin_banks[bank];
2329                 pin_bank->grange.name = pin_bank->name;
2330                 pin_bank->grange.id = bank;
2331                 pin_bank->grange.pin_base = pin_bank->pin_base;
2332                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2333                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2334                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2335                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2336         }
2337
2338         ret = rockchip_pinctrl_parse_dt(pdev, info);
2339         if (ret) {
2340                 pinctrl_unregister(info->pctl_dev);
2341                 return ret;
2342         }
2343
2344         return 0;
2345 }
2346
2347 /*
2348  * GPIO handling
2349  */
2350
2351 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
2352 {
2353         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2354         struct rockchip_pinctrl *info = bank->drvdata;
2355         int pin = offset;
2356
2357         if(bank->bank_num == 15)
2358         {
2359                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2360                 return -1;
2361         }
2362
2363
2364         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2365         return pinctrl_request_gpio(chip->base + offset);
2366 }
2367
2368 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
2369 {
2370         struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2371         struct rockchip_pinctrl *info = bank->drvdata;
2372         int pin = offset;
2373
2374         if(bank->bank_num == 15)
2375         {
2376                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2377                 return ;
2378         }
2379         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2380         pinctrl_free_gpio(chip->base + offset);
2381 }
2382
2383 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2384 {
2385         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2386         struct rockchip_pinctrl *info = bank->drvdata;
2387         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2388         unsigned long flags;
2389         u32 data;
2390         int pin = offset;
2391
2392         spin_lock_irqsave(&bank->slock, flags);
2393
2394         data = readl(reg);
2395         data &= ~BIT(offset);
2396         if (value)
2397                 data |= BIT(offset);
2398         writel(data, reg);
2399
2400         spin_unlock_irqrestore(&bank->slock, flags);
2401
2402         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, value);
2403 }
2404
2405 /*
2406  * Returns the level of the pin for input direction and setting of the DR
2407  * register for output gpios.
2408  */
2409 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2410 {
2411         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2412         struct rockchip_pinctrl *info = bank->drvdata;
2413         u32 data;
2414         int pin = offset;
2415
2416         data = readl(bank->reg_base + GPIO_EXT_PORT);
2417         data >>= offset;
2418         data &= 1;
2419
2420         DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, data);
2421         return data;
2422 }
2423
2424 /*
2425  * gpiolib gpio_direction_input callback function. The setting of the pin
2426  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2427  * interface.
2428  */
2429 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2430 {
2431         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2432         struct rockchip_pinctrl *info = bank->drvdata;
2433         int pin = offset;
2434
2435         if(bank->bank_num == 15)
2436         {
2437                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2438                 return -1;
2439         }
2440
2441         DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2442         return pinctrl_gpio_direction_input(gc->base + offset);
2443 }
2444
2445 /*
2446  * gpiolib gpio_direction_output callback function. The setting of the pin
2447  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2448  * interface.
2449  */
2450 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2451                                           unsigned offset, int value)
2452 {
2453         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2454         struct rockchip_pinctrl *info = bank->drvdata;
2455         int pin = offset;
2456
2457         if(bank->bank_num == 15)
2458         {
2459                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2460                 return -1;
2461         }
2462
2463         rockchip_gpio_set(gc, offset, value);
2464
2465         DBG_PINCTRL("%s:set GPIO%d-%d level %d\n", __func__, bank->bank_num, offset, value);
2466         return pinctrl_gpio_direction_output(gc->base + offset);
2467 }
2468
2469 /*
2470  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2471  * and a virtual IRQ, if not already present.
2472  */
2473 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2474 {
2475         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2476         struct rockchip_pinctrl *info = bank->drvdata;
2477         int pin = offset;
2478
2479         unsigned int virq;
2480
2481         if(bank->bank_num == 15)
2482         {
2483                 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2484                 return -1;
2485         }
2486
2487         if (!bank->domain)
2488                 return -ENXIO;
2489
2490         virq = irq_create_mapping(bank->domain, offset);
2491
2492         DBG_PINCTRL("%s:virq=%d, GPIO%d-%d\n", __func__, virq, bank->bank_num, offset);
2493
2494         return (virq) ? : -ENXIO;
2495 }
2496
2497 static const struct gpio_chip rockchip_gpiolib_chip = {
2498         .request = rockchip_gpio_request,
2499         .free = rockchip_gpio_free,
2500         .set = rockchip_gpio_set,
2501         .get = rockchip_gpio_get,
2502         .direction_input = rockchip_gpio_direction_input,
2503         .direction_output = rockchip_gpio_direction_output,
2504         .to_irq = rockchip_gpio_to_irq,
2505         .owner = THIS_MODULE,
2506 };
2507
2508 /*
2509  * Interrupt handling
2510  */
2511
2512 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
2513 {
2514         struct irq_chip *chip = irq_get_chip(irq);
2515         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
2516         struct rockchip_pinctrl *info = bank->drvdata;
2517         int pin;
2518
2519         u32 polarity = 0, data = 0;
2520         u32 pend;
2521         bool edge_changed = false;
2522
2523         chained_irq_enter(chip, desc);
2524
2525         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2526
2527         if (bank->toggle_edge_mode) {
2528                 polarity = readl_relaxed(bank->reg_base +
2529                                          GPIO_INT_POLARITY);
2530                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2531         }
2532
2533         while (pend) {
2534                 unsigned int virq;
2535
2536                 irq = __ffs(pend);
2537                 pend &= ~BIT(irq);
2538                 virq = irq_linear_revmap(bank->domain, irq);
2539
2540                 if (!virq) {
2541                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2542                         continue;
2543                 }
2544
2545                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2546
2547                 /*
2548                  * Triggering IRQ on both rising and falling edge
2549                  * needs manual intervention.
2550                  */
2551                 if (bank->toggle_edge_mode & BIT(irq)) {
2552                         if (data & BIT(irq))
2553                                 polarity &= ~BIT(irq);
2554                         else
2555                                 polarity |= BIT(irq);
2556
2557                         edge_changed = true;
2558                 }
2559
2560                 generic_handle_irq(virq);
2561
2562                 pin = irq;
2563                 DBG_PINCTRL("%s:irq=%d,%s\n",__func__, irq, bank->name);
2564         }
2565
2566         if (bank->toggle_edge_mode && edge_changed) {
2567                 /* Interrupt params should only be set with ints disabled */
2568                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
2569                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
2570                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
2571                 writel(data, bank->reg_base + GPIO_INTEN);
2572         }
2573
2574         chained_irq_exit(chip, desc);
2575 }
2576
2577 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2578 {
2579         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2580         struct rockchip_pinctrl *info = bank->drvdata;
2581         u32 mask = BIT(d->hwirq);
2582         u32 polarity;
2583         u32 level;
2584         u32 data;
2585         u32 mux;
2586         unsigned long flags;
2587         int pin = d->hwirq;
2588
2589         /* make sure the pin is configured as gpio input */
2590         mux = (bank->bank_num << 12) | (((d->hwirq / 8) + 0x0A) << 8) | ((d->hwirq % 8)<< 4) | RK_FUNC_GPIO;
2591         rockchip_set_mux(bank, d->hwirq, mux);
2592
2593         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2594         data &= ~mask;
2595         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2596
2597         if (type & IRQ_TYPE_EDGE_BOTH)
2598                 __irq_set_handler_locked(d->irq, handle_edge_irq);
2599         else
2600                 __irq_set_handler_locked(d->irq, handle_level_irq);
2601
2602         spin_lock_irqsave(&bank->slock, flags);
2603
2604         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
2605         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
2606
2607         switch (type) {
2608         case IRQ_TYPE_EDGE_BOTH:
2609                 bank->toggle_edge_mode |= mask;
2610                 level |= mask;
2611
2612                 /*
2613                  * Determine gpio state. If 1 next interrupt should be falling
2614                  * otherwise rising.
2615                  */
2616                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2617                 if (data & mask)
2618                         polarity &= ~mask;
2619                 else
2620                         polarity |= mask;
2621                 break;
2622         case IRQ_TYPE_EDGE_RISING:
2623                 bank->toggle_edge_mode &= ~mask;
2624                 level |= mask;
2625                 polarity |= mask;
2626                 break;
2627         case IRQ_TYPE_EDGE_FALLING:
2628                 bank->toggle_edge_mode &= ~mask;
2629                 level |= mask;
2630                 polarity &= ~mask;
2631                 break;
2632         case IRQ_TYPE_LEVEL_HIGH:
2633                 bank->toggle_edge_mode &= ~mask;
2634                 level &= ~mask;
2635                 polarity |= mask;
2636                 break;
2637         case IRQ_TYPE_LEVEL_LOW:
2638                 bank->toggle_edge_mode &= ~mask;
2639                 level &= ~mask;
2640                 polarity &= ~mask;
2641                 break;
2642         default:
2643                 //spin_unlock_irqrestore(&bank->slock, flags);
2644                 return -EINVAL;
2645         }
2646
2647         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
2648         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
2649
2650         spin_unlock_irqrestore(&bank->slock, flags);
2651
2652         DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
2653         return 0;
2654 }
2655
2656
2657 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
2658 {
2659         u32 val = __raw_readl(reg_base + offset);
2660         if (flag)
2661                 val |= BIT(bit);
2662         else
2663                 val &= ~BIT(bit);
2664
2665
2666         __raw_writel(val, reg_base + offset);
2667 }
2668
2669 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
2670 {
2671         while (gpio >= (bank->pin_base + bank->nr_pins))
2672                 bank++;
2673
2674         return gpio - bank->pin_base;
2675 }
2676
2677 static inline unsigned offset_to_bit(unsigned offset)
2678 {
2679         return 1u << offset;
2680 }
2681
2682 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
2683 {
2684         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
2685 }
2686
2687 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
2688 {
2689         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
2690 }
2691
2692 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
2693 {
2694         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
2695 }
2696
2697 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
2698 {
2699         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2700         struct rockchip_pinctrl *info = bank->drvdata;
2701
2702         u32 bit = d->hwirq;
2703         unsigned long flags;
2704         int pin = d->hwirq;
2705
2706         spin_lock_irqsave(&bank->slock, flags);
2707
2708         if (on)
2709         {
2710                 bank->suspend_wakeup |= BIT(bit);
2711         }
2712         else
2713         {
2714                 bank->suspend_wakeup &= ~BIT(bit);
2715         }
2716         spin_unlock_irqrestore(&bank->slock, flags);
2717
2718         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2719         return 0;
2720 }
2721
2722 static void rockchip_gpio_irq_unmask(struct irq_data *d)
2723 {
2724         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2725         struct rockchip_pinctrl *info = bank->drvdata;
2726         u32 bit = d->hwirq;
2727         unsigned long flags;
2728         int pin = d->hwirq;
2729
2730         spin_lock_irqsave(&bank->slock, flags);
2731         GPIOEnableIntr(bank->reg_base, bit);
2732         spin_unlock_irqrestore(&bank->slock, flags);
2733
2734         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2735 }
2736
2737 static void rockchip_gpio_irq_mask(struct irq_data *d)
2738 {
2739         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2740         struct rockchip_pinctrl *info = bank->drvdata;
2741         //u32 bit = gpio_to_bit(bank, d->irq);
2742         u32 bit = d->hwirq;
2743         unsigned long flags;
2744         int pin = d->hwirq;
2745
2746         spin_lock_irqsave(&bank->slock, flags);
2747         GPIODisableIntr(bank->reg_base, bit);
2748         spin_unlock_irqrestore(&bank->slock, flags);
2749
2750         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2751 }
2752
2753 static void rockchip_gpio_irq_ack(struct irq_data *d)
2754 {
2755         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2756         struct rockchip_pinctrl *info = bank->drvdata;
2757         //u32 bit = gpio_to_bit(bank, d->irq);
2758         u32 bit = d->hwirq;
2759         int pin = d->hwirq;
2760
2761         GPIOAckIntr(bank->reg_base, bit);
2762
2763         DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2764 }
2765
2766
2767 static struct irq_chip rockchip_gpio_irq_chip = {
2768         .name           = "GPIO",
2769         .irq_ack        = rockchip_gpio_irq_ack,
2770         .irq_disable    = rockchip_gpio_irq_mask,
2771         .irq_mask       = rockchip_gpio_irq_mask,
2772         .irq_unmask     = rockchip_gpio_irq_unmask,
2773         .irq_set_type   = rockchip_gpio_irq_set_type,
2774         .irq_set_wake   = rockchip_gpio_irq_set_wake,
2775 };
2776
2777
2778 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
2779                                 irq_hw_number_t hwirq)
2780 {
2781         struct rockchip_pin_bank *bank = d->host_data;
2782         struct rockchip_pinctrl *info = bank->drvdata;
2783         struct irq_data *irq_data = irq_get_irq_data(irq);
2784         int pin = hwirq;
2785
2786         if (!bank)
2787         {
2788                 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
2789                 return -EINVAL;
2790         }
2791
2792         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
2793         irq_set_chip_data(irq, bank);
2794         set_irq_flags(irq, IRQF_VALID);
2795
2796         irq_data->hwirq = hwirq;
2797         irq_data->irq = irq;
2798
2799         DBG_PINCTRL("%s:irq=%d\n",__func__,irq);
2800         return 0;
2801 }
2802
2803 const struct irq_domain_ops rockchip_gpio_irq_ops = {
2804         .map = rockchip_gpio_irq_map,
2805         .xlate = irq_domain_xlate_twocell,
2806 };
2807
2808
2809 static int rockchip_interrupts_register(struct platform_device *pdev,
2810                                                 struct rockchip_pinctrl *info)
2811 {
2812         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2813         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2814         //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2815         int i;
2816
2817         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2818                 if (!bank->valid) {
2819                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2820                                  bank->name);
2821                         continue;
2822                 }
2823
2824                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
2825
2826                 bank->drvdata = info;
2827                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2828                                 &rockchip_gpio_irq_ops, bank);
2829                 if (!bank->domain) {
2830                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2831                                  bank->name);
2832                         continue;
2833                 }
2834
2835                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2836                 printk("%s:bank_num=%d\n",__func__,bank->bank_num);
2837
2838                 irq_set_handler_data(bank->irq, bank);
2839                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
2840         }
2841
2842
2843         return 0;
2844 }
2845
2846
2847 static int rockchip_gpiolib_register(struct platform_device *pdev,
2848                                                 struct rockchip_pinctrl *info)
2849 {
2850         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2851         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2852         struct gpio_chip *gc;
2853         int ret;
2854         int i;
2855
2856         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2857                 if (!bank->valid) {
2858                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2859                                  bank->name);
2860                         continue;
2861                 }
2862
2863                 bank->gpio_chip = rockchip_gpiolib_chip;
2864
2865                 gc = &bank->gpio_chip;
2866                 gc->base = bank->pin_base;
2867                 gc->ngpio = bank->nr_pins;
2868                 gc->dev = &pdev->dev;
2869                 gc->of_node = bank->of_node;
2870                 gc->label = bank->name;
2871
2872                 ret = gpiochip_add(gc);
2873                 if (ret) {
2874                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2875                                                         gc->label, ret);
2876                         goto fail;
2877                 }
2878         }
2879
2880         rockchip_interrupts_register(pdev, info);
2881
2882         return 0;
2883
2884 fail:
2885         for (--i, --bank; i >= 0; --i, --bank) {
2886                 if (!bank->valid)
2887                         continue;
2888
2889                 if (gpiochip_remove(&bank->gpio_chip))
2890                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
2891                                                         bank->gpio_chip.label);
2892         }
2893         return ret;
2894 }
2895
2896 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2897                                                 struct rockchip_pinctrl *info)
2898 {
2899         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2900         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2901         int ret = 0;
2902         int i;
2903
2904         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
2905                 if (!bank->valid)
2906                         continue;
2907
2908                 ret = gpiochip_remove(&bank->gpio_chip);
2909         }
2910
2911         if (ret)
2912                 dev_err(&pdev->dev, "gpio chip remove failed\n");
2913
2914         return ret;
2915 }
2916
2917 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2918                                   struct device *dev)
2919 {
2920         struct resource res;
2921         int rk3188 = 0, rk3288 = 0;
2922
2923         //"base", "mux_bank0", "pull_bank0", "drv_bank0"
2924         if (of_address_to_resource(bank->of_node, 0, &res)) {
2925                 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2926                 return -ENOENT;
2927         }
2928         bank->reg_base = devm_ioremap_resource(dev, &res);
2929         if (IS_ERR(bank->reg_base))
2930                 return PTR_ERR(bank->reg_base);
2931
2932         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2933
2934         /*
2935          * special case, where parts of the pull setting-registers are
2936          * part of the PMU register space
2937          */
2938         rk3188 = of_device_is_compatible(bank->of_node, "rockchip,rk3188-gpio-bank0");
2939
2940         rk3288 = of_device_is_compatible(bank->of_node, "rockchip,rk3288-gpio-bank0");
2941
2942         if(rk3188)
2943         {
2944                 bank->bank_type = RK3188_BANK0;
2945
2946                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2947                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2948                         return -ENOENT;
2949                 }
2950                 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2951                 if (IS_ERR(bank->reg_pull_bank0))
2952                 return PTR_ERR(bank->reg_pull_bank0);
2953
2954                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2955
2956         }
2957         else if (rk3288)
2958         {
2959                 bank->bank_type = RK3288_BANK0;
2960                 if (of_address_to_resource(bank->of_node, 1, &res)) {
2961                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2962                         return -ENOENT;
2963                 }
2964                 bank->reg_mux_bank0 = devm_ioremap_resource(dev, &res);
2965                 if (IS_ERR(bank->reg_mux_bank0))
2966                 return PTR_ERR(bank->reg_mux_bank0);
2967
2968                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2969
2970                 if (of_address_to_resource(bank->of_node, 2, &res)) {
2971                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2972                         return -ENOENT;
2973                 }
2974                 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2975                 if (IS_ERR(bank->reg_pull_bank0))
2976                 return PTR_ERR(bank->reg_pull_bank0);
2977
2978                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2979
2980                 if (of_address_to_resource(bank->of_node, 3, &res)) {
2981                         dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2982                         return -ENOENT;
2983                 }
2984                 bank->reg_drv_bank0 = devm_ioremap_resource(dev, &res);
2985                 if (IS_ERR(bank->reg_drv_bank0))
2986                 return PTR_ERR(bank->reg_drv_bank0);
2987
2988                 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2989
2990         }
2991         else
2992         {
2993                 bank->bank_type = COMMON_BANK;
2994         }
2995
2996         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2997
2998         bank->clk = of_clk_get(bank->of_node, 0);
2999         if (IS_ERR(bank->clk)) {
3000                 dev_warn(dev, "failed to get clk for bank %s\n", bank->name);
3001                 bank->clk = NULL;
3002         }
3003         clk_prepare_enable(bank->clk);
3004         return 0;
3005 }
3006
3007 static const struct of_device_id rockchip_pinctrl_dt_match[];
3008
3009 /* retrieve the soc specific data */
3010 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3011                                                 struct rockchip_pinctrl *d,
3012                                                 struct platform_device *pdev)
3013 {
3014         const struct of_device_id *match;
3015         struct device_node *node = pdev->dev.of_node;
3016         struct device_node *np;
3017         struct rockchip_pin_ctrl *ctrl;
3018         struct rockchip_pin_bank *bank;
3019         int i;
3020
3021         match = of_match_node(rockchip_pinctrl_dt_match, node);
3022         ctrl = (struct rockchip_pin_ctrl *)match->data;
3023
3024         for_each_child_of_node(node, np) {
3025                 if (!of_find_property(np, "gpio-controller", NULL))
3026                         continue;
3027
3028                 bank = ctrl->pin_banks;
3029                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3030                         if (!strcmp(bank->name, np->name)) {
3031                                 bank->of_node = np;
3032
3033                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
3034                                         bank->valid = true;
3035                                 break;
3036                         }
3037                 }
3038         }
3039
3040         bank = ctrl->pin_banks;
3041         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3042                 spin_lock_init(&bank->slock);
3043                 bank->drvdata = d;
3044                 bank->pin_base = ctrl->nr_pins;
3045                 ctrl->nr_pins += bank->nr_pins;
3046         }
3047
3048         return ctrl;
3049 }
3050
3051
3052 #ifdef CONFIG_PM
3053 static int rockchip_pinctrl_suspend(void)
3054 {
3055         struct rockchip_pinctrl *info = g_info;
3056         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3057         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3058         int n;
3059         //int value = 0;
3060
3061         for(n=0; n<ctrl->nr_banks-1; n++)
3062         {
3063 #if 0
3064                 int i;
3065                 for(i=0; i<0x60; i=i+4)
3066                 {
3067                         value = readl_relaxed(bank->reg_base + i);
3068                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3069                 }
3070 #endif
3071                 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
3072                 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
3073
3074                 if (!bank->suspend_wakeup)
3075                 clk_disable_unprepare(bank->clk);
3076
3077                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3078                 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->suspend_wakeup);
3079                 bank++;
3080         }
3081
3082         return 0;
3083 }
3084
3085 static void rockchip_pinctrl_resume(void)
3086 {
3087         struct rockchip_pinctrl *info = g_info;
3088         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3089         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3090         int n;
3091         u32 isr;
3092
3093         for(n=0; n<ctrl->nr_banks-1; n++)
3094         {
3095 #if 0
3096                 int i;
3097                 for(i=0; i<0x60; i=i+4)
3098                 {
3099                         u32 value = readl_relaxed(bank->reg_base + i);
3100                         printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3101                 }
3102 #endif
3103                 if (!bank->suspend_wakeup)
3104                 clk_prepare_enable(bank->clk);
3105
3106                 /* keep enable for resume irq */
3107                  isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
3108                 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->reg_base + GPIO_INTEN);
3109
3110                 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3111                 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->saved_wakeup | (bank->suspend_wakeup & isr));
3112
3113                 bank++;
3114         }
3115
3116 }
3117
3118 static struct syscore_ops rockchip_gpio_syscore_ops = {
3119         .suspend        = rockchip_pinctrl_suspend,
3120         .resume         = rockchip_pinctrl_resume,
3121 };
3122 #endif
3123
3124
3125 static struct gpio_init_config *
3126 of_get_gpio_init_config(struct device *dev, struct device_node *np)
3127 {
3128         struct gpio_init_config *config;
3129         int gpio, i;
3130         enum of_gpio_flags flags;
3131
3132         config = devm_kzalloc(dev,
3133                         sizeof(struct gpio_init_config),
3134                         GFP_KERNEL);
3135         if (!config)
3136                 return ERR_PTR(-ENOMEM);
3137
3138         /* Fetch GPIOs. */
3139         config->nr_gpios = of_gpio_named_count(np, "init-gpios");
3140
3141         config->gpios = devm_kzalloc(dev,
3142                                 sizeof(struct gpio) * config->nr_gpios,
3143                                 GFP_KERNEL);
3144         if (!config->gpios)
3145                 return ERR_PTR(-ENOMEM);
3146
3147         for (i = 0; i < config->nr_gpios; i++) {
3148                 //gpio = of_get_named_gpio(np, "gpios", i);
3149                 gpio = of_get_named_gpio_flags(np, "init-gpios", i, &flags);
3150                 if (gpio < 0)
3151                         break;
3152                 config->gpios[i].gpio = gpio;
3153                 config->gpios[i].flags = flags & OF_GPIO_ACTIVE_LOW;
3154
3155                 printk("%s:gpio[%d] = %d, value = %lu\n",__func__, i, gpio, config->gpios[i].flags);
3156         }
3157
3158         return config;
3159 }
3160
3161
3162 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3163 {
3164         struct rockchip_pinctrl *info;
3165         struct device *dev = &pdev->dev;
3166         struct rockchip_pin_ctrl *ctrl;
3167         struct resource *res;
3168         int ret;
3169         struct device_node *np;
3170         int i;
3171
3172         if (!dev->of_node) {
3173                 dev_err(dev, "device tree node not found\n");
3174                 return -ENODEV;
3175         }
3176
3177         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3178         if (!info)
3179                 return -ENOMEM;
3180
3181         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3182         if (!ctrl) {
3183                 dev_err(dev, "driver data not available\n");
3184                 return -EINVAL;
3185         }
3186         info->ctrl = ctrl;
3187         info->dev = dev;
3188
3189         g_info = info;
3190
3191         /*if debug GPIO0 then
3192         *atomic_set(&info->bank_debug_flag, 1);
3193         *atomic_set(&info->pin_debug_flag, 0);
3194         *if debug GPIO0-10 then
3195         *atomic_set(&info->bank_debug_flag, 1);
3196         *atomic_set(&info->pin_debug_flag, 11);
3197         */
3198         atomic_set(&info->bank_debug_flag, 8);
3199         atomic_set(&info->pin_debug_flag, 14);
3200
3201         printk("%s:name=%s,type=%d\n",__func__, ctrl->label, (int)ctrl->type);
3202
3203         //"base", "mux", "pull", "drv";
3204         switch(ctrl->type)
3205         {
3206                 case RK2928:
3207                 case RK3066B:
3208                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3209                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3210                         if (IS_ERR(info->reg_base))
3211                         return PTR_ERR(info->reg_base);
3212                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3213                         break;
3214
3215                 case RK3188:
3216                 case RK3036:
3217                 case RK312X:
3218                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3219                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3220                         if (IS_ERR(info->reg_base))
3221                         return PTR_ERR(info->reg_base);
3222                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3223
3224                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3225                         info->reg_mux = devm_ioremap_resource(&pdev->dev, res);
3226                         if (IS_ERR(info->reg_mux))
3227                         return PTR_ERR(info->reg_mux);
3228                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3229
3230                         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3231                         info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3232                         if (IS_ERR(info->reg_pull))
3233                         return PTR_ERR(info->reg_pull);
3234                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3235
3236                         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
3237                         info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3238                         if (IS_ERR(info->reg_drv))
3239                         return PTR_ERR(info->reg_drv);
3240                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3241
3242                         break;
3243
3244                 case RK3288:
3245                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3246                         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3247                         if (IS_ERR(info->reg_base))
3248                         return PTR_ERR(info->reg_base);
3249                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3250
3251                         info->reg_mux = info->reg_base;
3252
3253                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3254                         info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3255                         if (IS_ERR(info->reg_pull))
3256                         return PTR_ERR(info->reg_pull);
3257                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3258
3259                         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3260                         info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3261                         if (IS_ERR(info->reg_drv))
3262                         return PTR_ERR(info->reg_drv);
3263                         printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3264
3265                         break;
3266
3267                 default:
3268                         printk("%s:unknown chip type %d\n",__func__, (int)ctrl->type);
3269                         return -1;
3270
3271         }
3272
3273
3274         ret = rockchip_gpiolib_register(pdev, info);
3275         if (ret)
3276                 return ret;
3277
3278         ret = rockchip_pinctrl_register(pdev, info);
3279         if (ret) {
3280                 rockchip_gpiolib_unregister(pdev, info);
3281                 return ret;
3282         }
3283
3284         np = dev->of_node;
3285         if (of_find_property(np, "init-gpios", NULL))
3286         {
3287                 info->config = of_get_gpio_init_config(&pdev->dev, np);
3288                 if (IS_ERR(info->config))
3289                 return PTR_ERR(info->config);
3290
3291                 ret = gpio_request_array(info->config->gpios, info->config->nr_gpios);
3292                 if (ret) {
3293                         dev_err(&pdev->dev, "Could not obtain init GPIOs: %d\n", ret);
3294                         return ret;
3295                 }
3296
3297                 for(i=0; i<info->config->nr_gpios; i++)
3298                 {
3299                         gpio_direction_output(info->config->gpios[i].gpio, info->config->gpios[i].flags);
3300                 }
3301         }
3302
3303         pinctrl_debugfs_init(info);
3304
3305         platform_set_drvdata(pdev, info);
3306 #ifdef CONFIG_PM
3307         register_syscore_ops(&rockchip_gpio_syscore_ops);
3308 #endif
3309         printk("%s:init ok\n",__func__);
3310
3311         return 0;
3312 }
3313
3314 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3315         PIN_BANK(0, 32, "gpio0"),
3316         PIN_BANK(1, 32, "gpio1"),
3317         PIN_BANK(2, 32, "gpio2"),
3318         PIN_BANK(3, 32, "gpio3"),
3319
3320         PIN_BANK(15, 32, "gpio15"),//virtual bank
3321 };
3322
3323 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3324                 .pin_banks              = rk2928_pin_banks,
3325                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3326                 .label                  = "RK2928-GPIO",
3327                 .type                   = RK2928,
3328                 .mux_offset             = 0xa8,
3329                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3330 };
3331
3332 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3333         PIN_BANK(0, 32, "gpio0"),
3334         PIN_BANK(1, 32, "gpio1"),
3335         PIN_BANK(2, 32, "gpio2"),
3336         PIN_BANK(3, 32, "gpio3"),
3337         PIN_BANK(4, 32, "gpio4"),
3338         PIN_BANK(6, 16, "gpio6"),
3339         PIN_BANK(15, 32, "gpio15"),//virtual bank
3340 };
3341
3342 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3343                 .pin_banks              = rk3066a_pin_banks,
3344                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3345                 .label                  = "RK3066a-GPIO",
3346                 .type                   = RK2928,
3347                 .mux_offset             = 0xa8,
3348                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3349 };
3350
3351 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3352         PIN_BANK(0, 32, "gpio0"),
3353         PIN_BANK(1, 32, "gpio1"),
3354         PIN_BANK(2, 32, "gpio2"),
3355         PIN_BANK(3, 32, "gpio3"),
3356
3357         PIN_BANK(15, 32, "gpio15"),//virtual bank
3358 };
3359
3360 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3361                 .pin_banks      = rk3066b_pin_banks,
3362                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3363                 .label          = "RK3066b-GPIO",
3364                 .type           = RK3066B,
3365                 .mux_offset     = 0x60,
3366 };
3367
3368 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3369         PIN_BANK(0, 32, "gpio0"),
3370         PIN_BANK(1, 32, "gpio1"),
3371         PIN_BANK(2, 32, "gpio2"),
3372         PIN_BANK(3, 32, "gpio3"),
3373
3374         PIN_BANK(15, 32, "gpio15"),//virtual bank
3375 };
3376
3377 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3378                 .pin_banks              = rk3188_pin_banks,
3379                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3380                 .label                  = "RK3188-GPIO",
3381                 .type                   = RK3188,
3382                 .mux_offset             = 0x60,
3383                 .pull_calc_reg  = rk3188_calc_pull_reg_and_bit,
3384 };
3385
3386
3387 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3388         PIN_BANK(0, 24, "gpio0"),
3389         PIN_BANK(1, 32, "gpio1"),
3390         PIN_BANK(2, 32, "gpio2"),
3391         PIN_BANK(3, 32, "gpio3"),
3392         PIN_BANK(4, 32, "gpio4"),
3393         PIN_BANK(5, 32, "gpio5"),
3394         PIN_BANK(6, 32, "gpio6"),
3395         PIN_BANK(7, 32, "gpio7"),
3396         PIN_BANK(8, 32, "gpio8"),
3397
3398
3399         PIN_BANK(15, 32, "gpio15"),//virtual bank
3400 };
3401
3402 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3403                 .pin_banks              = rk3288_pin_banks,
3404                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3405                 .label                  = "RK3288-GPIO",
3406                 .type                   = RK3288,
3407                 .mux_offset             = 0x0,
3408                 .pull_calc_reg  = rk3288_calc_pull_reg_and_bit,
3409                 .drv_calc_reg   = rk3288_calc_drv_reg_and_bit,
3410 };
3411
3412
3413 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3414         PIN_BANK(0, 32, "gpio0"),
3415         PIN_BANK(1, 32, "gpio1"),
3416         PIN_BANK(2, 32, "gpio2"),
3417
3418         PIN_BANK(15, 32, "gpio15"),//virtual bank
3419 };
3420
3421 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3422                 .pin_banks              = rk3036_pin_banks,
3423                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3424                 .label                  = "rk3036-GPIO",
3425                 .type                   = RK3036,
3426                 .mux_offset             = 0xa8,
3427                 .pull_calc_reg  = rk3036_calc_pull_reg_and_bit,
3428 };
3429
3430
3431 static struct rockchip_pin_bank rk312x_pin_banks[] = {
3432         PIN_BANK(0, 32, "gpio0"),
3433         PIN_BANK(1, 32, "gpio1"),
3434         PIN_BANK(2, 32, "gpio2"),
3435         PIN_BANK(3, 32, "gpio3"),
3436
3437         PIN_BANK(15, 32, "gpio15"),//virtual bank
3438 };
3439
3440 static struct rockchip_pin_ctrl rk312x_pin_ctrl = {
3441                 .pin_banks              = rk312x_pin_banks,
3442                 .nr_banks               = ARRAY_SIZE(rk312x_pin_banks),
3443                 .label                  = "rk312x-GPIO",
3444                 .type                   = RK312X,
3445                 .mux_offset             = 0xa8,
3446                 .pull_calc_reg  = rk312x_calc_pull_reg_and_bit,
3447 };
3448
3449
3450
3451 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3452         { .compatible = "rockchip,rk2928-pinctrl",
3453                 .data = (void *)&rk2928_pin_ctrl },
3454         { .compatible = "rockchip,rk3066a-pinctrl",
3455                 .data = (void *)&rk3066a_pin_ctrl },
3456         { .compatible = "rockchip,rk3066b-pinctrl",
3457                 .data = (void *)&rk3066b_pin_ctrl },
3458         { .compatible = "rockchip,rk3188-pinctrl",
3459                 .data = (void *)&rk3188_pin_ctrl },
3460         { .compatible = "rockchip,rk3288-pinctrl",
3461                 .data = (void *)&rk3288_pin_ctrl },
3462         { .compatible = "rockchip,rk3036-pinctrl",
3463                 .data = (void *)&rk3036_pin_ctrl },
3464         { .compatible = "rockchip,rk312x-pinctrl",
3465                 .data = (void *)&rk312x_pin_ctrl },
3466         {},
3467 };
3468 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3469
3470 static struct platform_driver rockchip_pinctrl_driver = {
3471         .probe          = rockchip_pinctrl_probe,
3472         .driver = {
3473                 .name   = "rockchip-pinctrl",
3474                 .owner  = THIS_MODULE,
3475                 .of_match_table = rockchip_pinctrl_dt_match,
3476         },
3477 };
3478
3479 static int __init rockchip_pinctrl_drv_register(void)
3480 {
3481         return platform_driver_register(&rockchip_pinctrl_driver);
3482 }
3483 postcore_initcall(rockchip_pinctrl_drv_register);
3484
3485 MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
3486 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3487 MODULE_LICENSE("GPL v2");