2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2016 Rockchip electronic L.T.D
5 * Author: Luo Wei <lw@rock-chips.com>
7 * Thanks to Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
24 #include <linux/bitops.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/gpio.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinctrl.h>
33 #include <linux/pinctrl/pinmux.h>
34 #include <linux/pinctrl/pinconf-generic.h>
35 #include <linux/irqchip/chained_irq.h>
36 #include <linux/clk.h>
37 #include <linux/syscore_ops.h>
38 #include <linux/highmem.h>
39 #include <dt-bindings/pinctrl/rockchip.h>
41 #include <linux/of_device.h>
42 #include <linux/pinctrl/consumer.h>
43 #include <linux/slab.h>
44 #include <linux/delay.h>
45 #include <linux/rockchip/grf.h>
46 #include <linux/of_gpio.h>
49 #ifdef CONFIG_DEBUG_FS
50 #include <linux/debugfs.h>
59 #define DBG_PINCTRL(x...) do { if((((atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)) && (atomic_read(&info->pin_debug_flag) == (pin + 1))) || ((atomic_read(&info->pin_debug_flag) == 0) && (atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1)))) && bank && info) printk(x); } while (0)
61 #define DBG_PINCTRL(x...)
65 /* GPIO control registers */
66 #define GPIO_SWPORT_DR 0x00
67 #define GPIO_SWPORT_DDR 0x04
68 #define GPIO_INTEN 0x30
69 #define GPIO_INTMASK 0x34
70 #define GPIO_INTTYPE_LEVEL 0x38
71 #define GPIO_INT_POLARITY 0x3c
72 #define GPIO_INT_STATUS 0x40
73 #define GPIO_INT_RAWSTATUS 0x44
74 #define GPIO_DEBOUNCE 0x48
75 #define GPIO_PORTS_EOI 0x4c
76 #define GPIO_EXT_PORT 0x50
77 #define GPIO_LS_SYNC 0x60
79 enum rockchip_pinctrl_type {
88 enum rockchip_pin_bank_type {
95 * @reg_base: register base of the gpio bank
96 * @reg_pull: optional separate register for additional pull settings
97 * @clk: clock of the gpio bank
98 * @irq: interrupt of the gpio bank
99 * @pin_base: first pin number
100 * @nr_pins: number of pins in this bank
101 * @name: name of the bank
102 * @bank_num: number of the bank, to account for holes
103 * @valid: are all necessary informations present
104 * @of_node: dt node of this bank
105 * @drvdata: common pinctrl basedata
106 * @domain: irqdomain of the gpio bank
107 * @gpio_chip: gpiolib chip
108 * @grange: gpio range
109 * @slock: spinlock for the gpio bank
111 struct rockchip_pin_bank {
112 void __iomem *reg_base;
113 void __iomem *reg_mux_bank0;
114 void __iomem *reg_pull_bank0;
115 void __iomem *reg_drv_bank0;
122 enum rockchip_pin_bank_type bank_type;
124 struct device_node *of_node;
125 struct rockchip_pinctrl *drvdata;
126 struct irq_domain *domain;
127 struct gpio_chip gpio_chip;
128 struct pinctrl_gpio_range grange;
130 u32 toggle_edge_mode;
135 #define PIN_BANK(id, pins, label) \
144 struct rockchip_pin_ctrl {
145 struct rockchip_pin_bank *pin_banks;
149 enum rockchip_pinctrl_type type;
151 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
152 void __iomem **reg, u8 *bit);
153 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
154 void __iomem **reg, u8 *bit);
157 struct rockchip_pin_config {
159 unsigned long *configs;
160 unsigned int nconfigs;
164 * struct rockchip_pin_group: represent group of pins of a pinmux function.
165 * @name: name of the pin group, used to lookup the group.
166 * @pins: the pins included in this group.
167 * @npins: number of pins included in this group.
168 * @func: the mux function number to be programmed when selected.
169 * @configs: the config values to be set for each pin
170 * @nconfigs: number of configs for each pin
172 struct rockchip_pin_group {
174 const char *func_name;
177 struct rockchip_pin_config *data;
178 unsigned long gconfigs;
182 * struct rockchip_pmx_func: represent a pin function.
183 * @name: name of the pin function, used to lookup the function.
184 * @groups: one or more names of pin groups that provide this function.
185 * @num_groups: number of groups included in @groups.
187 struct rockchip_pmx_func {
193 struct gpio_init_config {
199 struct rockchip_pinctrl {
200 void __iomem *reg_base;
202 void __iomem *reg_mux;
203 void __iomem *reg_pull;
204 void __iomem *reg_drv;
207 struct rockchip_pin_ctrl *ctrl;
208 struct pinctrl_desc pctl;
209 struct pinctrl_dev *pctl_dev;
210 struct rockchip_pin_group *groups;
211 unsigned int ngroups;
212 struct rockchip_pmx_func *functions;
213 unsigned int nfunctions;
215 atomic_t bank_debug_flag;
216 atomic_t pin_debug_flag;
217 #ifdef CONFIG_DEBUG_FS
218 struct dentry *debugfs;
220 struct gpio_init_config *config;
233 struct iomux_mode mux;
238 struct func_to_reg_offset {
239 unsigned int reg_type;
240 const char *vol_name;
241 const char *func_name;
242 const char *group_name;
243 unsigned int reg_offset;
244 unsigned int bit_offset;
245 unsigned int bit_mask;
248 #define FUNC_GROUP_TO_REG_OFFSET(type, vol, func, group, reg, bit, mask) \
253 .group_name = group, \
260 static struct rockchip_pinctrl *g_info;
263 #ifdef CONFIG_DEBUG_FS
264 #define PINCTRL_REGS_BUFSIZE (1024<<4)
265 static ssize_t pinctrl_write_proc_data(struct file *file, const char __user *buffer,
266 size_t count, loff_t *data)
268 struct rockchip_pinctrl *info;
271 int bank_value, pin_value;
273 info = file->private_data;
275 buf = kzalloc(32, GFP_KERNEL);
279 ret = copy_from_user(buf, buffer, count);
285 if((strstr(buf, "debug") != NULL) || (strstr(buf, "DEBUG") != NULL))
287 if(strstr(buf, "-") != NULL)
289 if(strstr(buf, "debug") != NULL)
290 sscanf(buf, "debug%d-%d", &bank_value, &pin_value);
291 else if(strstr(buf, "DEBUG") != NULL)
292 sscanf(buf, "DEBUG%d-%d", &bank_value, &pin_value);
294 if((bank_value < 0) || (pin_value < 0))
296 printk("%s:error:bank %d or pin %d is out of range %d-%d\n",__func__, bank_value, pin_value, info->ctrl->nr_banks-1, info->ctrl->nr_pins);
300 atomic_set(&info->bank_debug_flag, bank_value+1);
301 atomic_set(&info->pin_debug_flag, pin_value+1);
302 printk("%s:open debug for bank%d-%d\n",__func__,bank_value, pin_value);
307 if(strstr(buf, "debug") != NULL)
308 sscanf(buf, "debug%d", &bank_value);
309 else if(strstr(buf, "DEBUG") != NULL)
310 sscanf(buf, "DEBUG%d", &bank_value);
314 printk("%s:error:bank%d is out of range %d\n",__func__, bank_value,info->ctrl->nr_banks-1);
318 atomic_set(&info->bank_debug_flag, bank_value+1);
319 atomic_set(&info->pin_debug_flag, 0);
320 printk("%s:open debug for bank%d\n",__func__,bank_value);
325 else if((strstr(buf, "stop") != NULL) || (strstr(buf, "STOP") != NULL))
327 atomic_set(&info->bank_debug_flag, 0);
328 atomic_set(&info->pin_debug_flag, 0);
329 printk("%s:close debug\n",__func__);
337 static ssize_t pinctrl_show_regs(struct file *file, char __user *user_buf,
338 size_t count, loff_t *ppos)
340 struct rockchip_pinctrl *info;
341 struct rockchip_pin_ctrl *ctrl;
342 struct rockchip_pin_bank *bank, *bank0;
349 info = file->private_data;
351 bank = ctrl->pin_banks;
354 buf = kzalloc(PINCTRL_REGS_BUFSIZE, GFP_KERNEL);
358 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
359 "%s registers:\n",ctrl->label);
360 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
361 "=================================\n");
363 for(n=0; n<ctrl->nr_banks-1; n++)
365 for(i=GPIO_SWPORT_DR; i<GPIO_LS_SYNC; i=i+4)
367 value = readl_relaxed(bank->reg_base + i);
368 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "bank%d reg[0x%p+0x%x]=0x%08x\n",bank->bank_num, (int *)bank->reg_base, i, value);
373 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
374 "=================================\n\n");
376 if(bank0 && bank0->reg_mux_bank0 && bank0->reg_pull_bank0 && bank0->reg_drv_bank0)
378 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
379 "BANK0 GRF registers:\n");
380 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
381 "=================================\n");
383 for(i=0; i<0x0c; i=i+4)
385 value = readl_relaxed(bank0->reg_mux_bank0 + i);
386 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "MUX_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_mux_bank0, i, value);
389 for(i=0; i<0x0c; i=i+4)
391 value = readl_relaxed(bank0->reg_pull_bank0 + i);
392 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "PULL_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_pull_bank0, i, value);
395 for(i=0; i<0x0c; i=i+4)
397 value = readl_relaxed(bank0->reg_drv_bank0 + i);
398 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "DRV_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_drv_bank0, i, value);
401 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
402 "=================================\n\n");
406 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
407 "rockchip pinctrl GRF registers:\n");
408 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
409 "=================================\n");
412 for(i=0; i<0x400; i=i+4)
414 value = readl_relaxed(info->reg_base + i);
415 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "GRF[0x%p+0x%x]=0x%08x\n",(int *)info->reg_base, i, value);
418 len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
419 "=================================\n\n");
421 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
427 static const struct file_operations pinctrl_regs_ops = {
428 .owner = THIS_MODULE,
430 .read = pinctrl_show_regs,
431 .write = pinctrl_write_proc_data,
432 .llseek = default_llseek,
435 static int pinctrl_debugfs_init(struct rockchip_pinctrl *info)
437 info->debugfs = debugfs_create_dir("rockchip_pinctrl", NULL);
441 debugfs_create_file("registers", S_IFREG | S_IRUGO,
442 info->debugfs, (void *)info, &pinctrl_regs_ops);
447 static void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
450 debugfs_remove_recursive(info->debugfs);
455 static inline int pinctrl_debugfs_init(struct rockchip_pinctrl*info)
461 static inline void pinctrl_debugfs_remove(struct rockchip_pinctrl*info)
465 #endif /* CONFIG_DEBUG_FS */
468 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
470 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
473 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
474 const struct rockchip_pinctrl *info,
479 for (i = 0; i < info->ngroups; i++) {
480 if (!strcmp(info->groups[i].name, name))
481 return &info->groups[i];
488 * given a pin number that is local to a pin controller, find out the pin bank
489 * and the register base of the pin bank.
491 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
494 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
496 while (pin >= (b->pin_base + b->nr_pins))
502 static struct rockchip_pin_bank *bank_num_to_bank(
503 struct rockchip_pinctrl *info,
506 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
509 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
510 if (b->bank_num == num)
514 return ERR_PTR(-EINVAL);
518 * Pinctrl_ops handling
521 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
523 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
525 return info->ngroups;
528 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
531 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
533 return info->groups[selector].name;
536 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
537 unsigned selector, const unsigned **pins,
540 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
542 if (selector >= info->ngroups)
545 *pins = info->groups[selector].pins;
546 *npins = info->groups[selector].npins;
551 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
552 struct device_node *np,
553 struct pinctrl_map **map, unsigned *num_maps)
555 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
556 const struct rockchip_pin_group *grp;
557 struct pinctrl_map *new_map;
558 struct device_node *parent;
563 * first find the group of this node and check if we need to create
564 * config maps for pins
566 grp = pinctrl_name_to_group(info, np->name);
568 dev_err(info->dev, "unable to find group for node %s\n",
573 map_num += grp->npins;
574 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
583 parent = of_get_parent(np);
585 devm_kfree(pctldev->dev, new_map);
588 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
589 new_map[0].data.mux.function = parent->name;
590 new_map[0].data.mux.group = np->name;
593 /* create config map */
595 for (i = 0; i < grp->npins; i++) {
596 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
597 new_map[i].data.configs.group_or_pin = grp->name;
598 //pin_get_name(pctldev, grp->pins[i]);
599 new_map[i].data.configs.configs = grp->data[i].configs;
600 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
603 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
604 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
609 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
610 struct pinctrl_map *map, unsigned num_maps)
614 static const struct pinctrl_ops rockchip_pctrl_ops = {
615 .get_groups_count = rockchip_get_groups_count,
616 .get_group_name = rockchip_get_group_name,
617 .get_group_pins = rockchip_get_group_pins,
618 .dt_node_to_map = rockchip_dt_node_to_map,
619 .dt_free_map = rockchip_dt_free_map,
623 #define RK3288_GRF_GPIO1A_IOMUX 0x0000
624 #define RK3288_GRF_GPIO5A_IOMUX 0x004C
626 static int rk32_iomux_bit_op(struct rockchip_pin_bank *bank, int pin, int mux, void __iomem *reg, int bits)
631 struct rockchip_pinctrl *info = bank->drvdata;
635 reg += (pin / 8) * 4;
638 spin_lock_irqsave(&bank->slock, flags);
639 if(bank->bank_num == 0)
641 data = readl_relaxed(reg);
643 data |= (mux & 3) << bit;
648 data = (3 << (bit + 16));
649 data |= (mux & 3) << bit;
653 spin_unlock_irqrestore(&bank->slock, flags);
658 reg += (pin / 4) * 4;
661 spin_lock_irqsave(&bank->slock, flags);
662 if(bank->bank_num == 0)
664 data = readl_relaxed(reg);
665 data &= ~(0x0f<<bit);
666 data |= (mux & 0x0f) << bit;
671 data = (0x0f << (bit + 16));
672 data |= (mux & 0x0f) << bit;
676 spin_unlock_irqrestore(&bank->slock, flags);
680 printk("%s:unknow bits %d\n",__func__, bits);
684 result = readl_relaxed(reg);
685 if(bank->bank_num == 0)
686 DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - bank->reg_mux_bank0, data, result);
688 DBG_PINCTRL("%s:GPIO%d-%d,reg=0x%x,data=0x%x,result=0x%x\n",__func__, bank->bank_num, pin, reg - info->reg_base, data, result);
695 static int rockchip_set_rk32_mux(struct rockchip_pin_bank *bank, int pin, int mux)
697 struct rockchip_pinctrl *info = bank->drvdata;
698 void __iomem *reg = info->reg_mux;
704 if((m.mux.bank != bank->bank_num))
706 printk("%s:error:mux_bank(%d) != gpio_bank(%d)\n",__func__, m.mux.bank, bank->bank_num);
710 switch(bank->bank_num)
714 reg = bank->reg_mux_bank0;
715 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
719 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
723 reg += RK3288_GRF_GPIO1A_IOMUX;
724 if((m.mux.goff == 0x0d))
728 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
732 reg += RK3288_GRF_GPIO2A_IOMUX;
733 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
737 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
741 reg += RK3288_GRF_GPIO3A_IOMUX;
742 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
746 else if(m.mux.goff == 0x0d)
752 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
756 reg += RK3288_GRF_GPIO4AL_IOMUX;
757 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
761 else if((m.mux.goff == 0x0c) || (m.mux.goff == 0x0d))
767 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
772 reg += RK3288_GRF_GPIO5A_IOMUX;
773 if((m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
778 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
783 reg += RK3288_GRF_GPIO6A_IOMUX;
784 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
789 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
793 reg += RK3288_GRF_GPIO7A_IOMUX;
794 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
798 else if((m.mux.goff == 0x0c))
804 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
808 reg += RK3288_GRF_GPIO8A_IOMUX;
809 if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b))
814 rk32_iomux_bit_op(bank, pin, mux, reg, bits);
818 printk("%s:unknow bank num %d\n", __func__, bank->bank_num);
830 * Set a new mux function for a pin.
832 * The register is divided into the upper and lower 16 bit. When changing
833 * a value, the previous register value is not read and changed. Instead
834 * it seems the changed bits are marked in the upper 16 bit, while the
835 * changed value gets set in the same offset in the lower 16 bit.
836 * All pin settings seem to be 2 bit wide in both the upper and lower
838 * @bank: pin bank to change
839 * @pin: pin to change
840 * @mux: new mux function to set
842 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
844 struct rockchip_pinctrl *info = bank->drvdata;
845 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
852 /*GPIO0_C0 = 0x0c00, NAND_D8, */
853 /*GPIO0_C1 = 0x0c10, NAND_D9, */
855 if(bank->bank_num == 15)
857 printk("%s:warning ignore bank num %d\n",__func__, bank->bank_num);
861 if(info->ctrl->type == RK3288)
863 rockchip_set_rk32_mux(bank, pin, mux);
869 if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
871 printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
872 m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
876 if((info->ctrl->type == RK312X) && (bank->bank_num == 2) && (pin >= 20) && (pin <= 24))
878 /*RK321X GPIO2C_IOMUX2 and GPIO2D_IOMUX are special */
879 if((pin >= 20) && (pin <= 23))
881 reg -= info->ctrl->mux_offset;
887 reg -= info->ctrl->mux_offset;
891 spin_lock_irqsave(&bank->slock, flags);
893 data = (0x0f << (bit + 16));
894 data |= (mux & 0x0f) << bit;
897 spin_unlock_irqrestore(&bank->slock, flags);
903 /* get basic quadrupel of mux registers and the correct reg inside */
904 reg += bank->bank_num * 0x10;
905 reg += (pin / 8) * 4;
908 spin_lock_irqsave(&bank->slock, flags);
910 data = (3 << (bit + 16));
911 data |= (mux & 3) << bit;
914 spin_unlock_irqrestore(&bank->slock, flags);
917 DBG_PINCTRL("%s:setting GPIO%d-%d to mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
919 //DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
924 * Pinmux_ops handling
927 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
929 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
931 return info->nfunctions;
934 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
937 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
939 return info->functions[selector].name;
942 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
943 unsigned selector, const char * const **groups,
944 unsigned * const num_groups)
946 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
948 *groups = info->functions[selector].groups;
949 *num_groups = info->functions[selector].ngroups;
954 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
957 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
958 const unsigned int *pins = info->groups[group].pins;
959 const struct rockchip_pin_config *data = info->groups[group].data;
960 struct rockchip_pin_bank *bank;
965 * for each pin in the pin group selected, program the correspoding pin
966 * pin function number in the config register.
968 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
969 bank = pin_to_bank(info, pins[cnt]);
971 DBG_PINCTRL("%s:enable function %s group %s\n",
972 __func__, info->functions[selector].name, info->groups[group].name);
973 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
981 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
982 unsigned selector, unsigned group)
984 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
985 const unsigned int *pins = info->groups[group].pins;
986 const struct rockchip_pin_config *data = info->groups[group].data;
987 struct rockchip_pin_bank *bank;
991 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
992 bank = pin_to_bank(info, pins[cnt]);
994 DBG_PINCTRL("%s:disable function %s group %s\n",
995 __func__, info->functions[selector].name, info->groups[group].name);
996 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, FUNC_TO_GPIO(data[cnt].func));
1002 * The calls to gpio_direction_output() and gpio_direction_input()
1003 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1004 * function called from the gpiolib interface).
1006 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1007 struct pinctrl_gpio_range *range,
1008 unsigned offset, bool input)
1010 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1011 struct rockchip_pin_bank *bank;
1012 struct gpio_chip *chip;
1018 bank = gc_to_pin_bank(chip);
1019 pin = offset - chip->base;
1021 mux = (bank->bank_num << 12) | (((pin / 8) + 0x0A) << 8) | ((pin % 8)<< 4) | RK_FUNC_GPIO;
1023 rockchip_set_mux(bank, pin, mux);
1025 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1026 /* set bit to 1 for output, 0 for input */
1031 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1033 result = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1035 DBG_PINCTRL("%s:gpio_direction for pin %u as %s-%d to %s,data=0x%x,result=0x%x\n",
1036 __func__, offset, range->name, pin, input ? "input" : "output", data, result);
1040 static const struct pinmux_ops rockchip_pmx_ops = {
1041 .get_functions_count = rockchip_pmx_get_funcs_count,
1042 .get_function_name = rockchip_pmx_get_func_name,
1043 .get_function_groups = rockchip_pmx_get_groups,
1044 .enable = rockchip_pmx_enable,
1045 //.disable = rockchip_pmx_disable,
1046 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1055 static struct func_to_reg_offset rk3188_func_to_drv_reg_offset[] =
1057 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON0, 0 ,3),
1058 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 2, 3),
1059 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_flash" ,"NULL", RK3188_GRF_IO_CON0, 4 ,3),
1060 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "gpio0_d" ,"NULL", RK3188_GRF_IO_CON0, 6 ,3),
1061 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio1_uart0" ,"NULL", RK3188_GRF_IO_CON0, 8 ,3),
1062 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_uart1" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1063 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_spi0" ,"NULL", RK3188_GRF_IO_CON0, 10 ,3),
1064 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "gpio1_uart2" ,"NULL", RK3188_GRF_IO_CON0, 12 ,3),
1065 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_uart3" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1066 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_spi1" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1067 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio1_gps" ,"NULL", RK3188_GRF_IO_CON0, 14 ,3),
1069 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 0 ,3),
1070 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2s0" ,"NULL", RK3188_GRF_IO_CON1, 2 ,3),
1071 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_c" ,"NULL", RK3188_GRF_IO_CON1, 4 ,3),
1072 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c0" ,"NULL", RK3188_GRF_IO_CON1, 6 ,3),
1073 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c1" ,"NULL", RK3188_GRF_IO_CON1, 8 ,3),
1074 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio1-vcc", "gpio1_i2c2" ,"NULL", RK3188_GRF_IO_CON1, 10 ,3),
1075 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap1-vcc", "gpio1_i2c4" ,"NULL", RK3188_GRF_IO_CON1, 12 ,3),
1076 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON1, 14 ,3),
1078 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_lcdc1" ,"NULL", RK3188_GRF_IO_CON2, 0 ,3),
1079 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc1-vcc", "gpio2_smc" ,"NULL", RK3188_GRF_IO_CON2, 2 ,3),
1080 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON2, 4 ,3),
1081 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1082 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 6 ,3),
1083 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_sdmmc" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1084 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "ap0-vcc", "gpio3_rmii" ,"NULL", RK3188_GRF_IO_CON2, 8 ,3),
1085 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_b" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1086 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_i2c3" ,"NULL", RK3188_GRF_IO_CON2, 10 ,3),
1087 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 12 ,3),
1088 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "gpio3_cif" ,"NULL", RK3188_GRF_IO_CON2, 14 ,3),
1090 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 0 ,3),
1091 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_sdio" ,"NULL", RK3188_GRF_IO_CON3, 2 ,3),
1092 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_pwm" ,"NULL", RK3188_GRF_IO_CON3, 4 ,3),
1093 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "gpio3_d" ,"NULL", RK3188_GRF_IO_CON3, 6 ,3),
1094 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 8 ,3),
1095 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "flash-vcc", "flash" ,"NULL", RK3188_GRF_IO_CON3, 10 ,3),
1096 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "cif-vcc", "cif" ,"NULL", RK3188_GRF_IO_CON3, 12 ,3),
1097 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON3, 14 ,3),
1099 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "lcdc0-vcc", "lcdc0" ,"NULL", RK3188_GRF_IO_CON4, 0 ,3),
1100 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "vccio0-vcc", "jtag" ,"NULL", RK3188_GRF_IO_CON4, 2 ,3),
1101 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "misc" ,"NULL", RK3188_GRF_IO_CON4, 4 ,3),
1102 FUNC_GROUP_TO_REG_OFFSET(TYPE_DRV_REG, "NULL", "reserve" ,"NULL", RK3188_GRF_IO_CON4, 6 ,3),
1106 static struct func_to_reg_offset rk3188_func_to_vol_reg_offset[] =
1108 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap0-vcc", "vol_domain", "ap0-vcc", RK3188_GRF_IO_CON4, 8 ,1),
1109 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "ap1-vcc", "vol_domain", "ap1-vcc", RK3188_GRF_IO_CON4, 9 ,1),
1110 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "cif-vcc", "vol_domain", "cif-vcc", RK3188_GRF_IO_CON4, 10 ,1),
1111 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash-vcc", "vol_domain", "flash-vcc", RK3188_GRF_IO_CON4, 11 ,1),
1112 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio0-vcc", "vol_domain", "vccio0-vcc", RK3188_GRF_IO_CON4, 12 ,1),
1113 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "vccio1-vcc", "vol_domain", "vccio1-vcc", RK3188_GRF_IO_CON4, 13 ,1),
1114 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc0-vcc", "vol_domain", "lcdc0-vcc", RK3188_GRF_IO_CON4, 14 ,1),
1115 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1-vcc", "vol_domain", "lcdc1-vcc", RK3188_GRF_IO_CON4, 15 ,1),
1119 static struct func_to_reg_offset rk3288_func_to_vol_reg_offset[] =
1121 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc-vcc", "vol_domain", "lcdc-vcc", RK3288_GRF_IO_VSEL, 0 ,1),
1122 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "dvp-vcc", "vol_domain", "dvp-vcc", RK3288_GRF_IO_VSEL, 1 ,1),
1123 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash0-vcc", "vol_domain", "flash0-vcc", RK3288_GRF_IO_VSEL, 2 ,1),
1124 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash1-vcc", "vol_domain", "flash1-vcc", RK3288_GRF_IO_VSEL, 3 ,1),
1125 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "wifi-vcc", "vol_domain", "wifi-vcc", RK3288_GRF_IO_VSEL, 4 ,1),
1126 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "bb-vcc", "vol_domain", "bb-vcc", RK3288_GRF_IO_VSEL, 5 ,1),
1127 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "audio-vcc", "vol_domain", "audio-vcc", RK3288_GRF_IO_VSEL, 6 ,1),
1128 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "sdcard-vcc", "vol_domain", "sdcard-vcc", RK3288_GRF_IO_VSEL, 7 ,1),
1130 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio30-vcc", "vol_domain", "gpio30-vcc", RK3288_GRF_IO_VSEL, 8 ,1),
1131 FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio1830-vcc", "vol_domain", "gpio1830-vcc", RK3288_GRF_IO_VSEL, 9 ,1),
1135 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1136 int pin_num, void __iomem **reg, u8 *bit)
1138 struct rockchip_pinctrl *info = bank->drvdata;
1139 void __iomem *reg_base;
1142 *reg = info->reg_base + RK2928_PULL_OFFSET;
1143 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1144 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1146 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1148 reg_base = info->reg_base;
1150 DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1154 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1155 int pin_num, void __iomem **reg, u8 *bit)
1157 struct rockchip_pinctrl *info = bank->drvdata;
1158 void __iomem *reg_base;
1161 /* The first 12 pins of the first bank are located elsewhere */
1162 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
1163 *reg = bank->reg_pull_bank0 +
1164 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1165 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1166 *bit *= RK3188_PULL_BITS_PER_PIN;
1167 reg_base = bank->reg_pull_bank0;
1169 *reg = info->reg_pull - 4;
1170 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1171 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1174 * The bits in these registers have an inverse ordering
1175 * with the lowest pin being in bits 15:14 and the highest
1178 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1179 *bit *= RK3188_PULL_BITS_PER_PIN;
1180 reg_base = info->reg_pull - 4;
1183 DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1186 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1187 int pin_num, void __iomem **reg, u8 *bit)
1189 struct rockchip_pinctrl *info = bank->drvdata;
1190 void __iomem *reg_base;
1193 /* The first 24 pins of the first bank are located elsewhere */
1194 if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1195 *reg = bank->reg_pull_bank0 +
1196 ((pin_num / 8) * 4);
1199 reg_base = bank->reg_pull_bank0;
1201 *reg = info->reg_pull - 0x10;
1202 *reg += bank->bank_num * 0x10;
1203 *reg += ((pin_num / 8) * 4);
1205 *bit = (pin_num % 8);
1207 reg_base = info->reg_pull - 0x10;
1210 DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1214 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1215 int pin_num, void __iomem **reg, u8 *bit)
1217 struct rockchip_pinctrl *info = bank->drvdata;
1218 void __iomem *reg_base;
1221 /* The first 24 pins of the first bank are located elsewhere */
1222 if (bank->bank_type == RK3288_BANK0 && pin_num < 24) {
1223 *reg = bank->reg_drv_bank0 +
1224 ((pin_num / 8) * 4);
1228 reg_base = bank->reg_drv_bank0;
1230 *reg = info->reg_drv - 0x10;
1231 *reg += bank->bank_num * 0x10;
1232 *reg += ((pin_num / 8) * 4);
1234 *bit = (pin_num % 8);
1237 reg_base = info->reg_drv - 0x10;
1240 DBG_PINCTRL("%s:GPIO%d-%d, drv_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1244 static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1245 int pin_num, void __iomem **reg, u8 *bit)
1247 struct rockchip_pinctrl *info = bank->drvdata;
1248 void __iomem *reg_base;
1251 *reg = info->reg_pull;
1252 *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
1253 *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
1255 *bit = pin_num % RK3036_PULL_PINS_PER_REG;
1257 reg_base = info->reg_pull;
1259 DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1263 static void rk312x_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1264 int pin_num, void __iomem **reg, u8 *bit)
1266 struct rockchip_pinctrl *info = bank->drvdata;
1267 void __iomem *reg_base;
1270 *reg = info->reg_pull;
1271 *reg += bank->bank_num * RK312X_PULL_BANK_STRIDE;
1272 *reg += (pin_num / RK312X_PULL_PINS_PER_REG) * 4;
1274 *bit = pin_num % RK312X_PULL_PINS_PER_REG;
1276 reg_base = info->reg_pull;
1278 DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%x, bit=%d\n", __func__, bank->bank_num, pin_num, *reg - reg_base, *bit);
1285 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1287 struct rockchip_pinctrl *info = bank->drvdata;
1288 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1294 /* rk3066b does support any pulls */
1295 if (ctrl->type == RK3066B)
1296 return PIN_CONFIG_BIAS_DISABLE;
1298 ctrl->pull_calc_reg(bank, pin_num, ®, &bit);
1300 switch (ctrl->type) {
1302 return !(readl_relaxed(reg) & BIT(bit))
1303 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1304 : PIN_CONFIG_BIAS_DISABLE;
1307 data = readl_relaxed(reg) >> bit;
1308 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1312 return PIN_CONFIG_BIAS_DISABLE;
1314 return PIN_CONFIG_BIAS_PULL_UP;
1316 return PIN_CONFIG_BIAS_PULL_DOWN;
1318 return PIN_CONFIG_BIAS_BUS_HOLD;
1321 dev_err(info->dev, "unknown pull setting\n");
1324 dev_err(info->dev, "unsupported pinctrl type\n");
1328 DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1332 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1333 int pin_num, int pull)
1335 struct rockchip_pinctrl *info = bank->drvdata;
1336 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1338 unsigned long flags;
1344 /* rk3066b does support any pulls */
1345 if (ctrl->type == RK3066B)
1346 return pull ? -EINVAL : 0;
1348 ctrl->pull_calc_reg(bank, pin_num, ®, &bit);
1350 switch (ctrl->type) {
1354 spin_lock_irqsave(&bank->slock, flags);
1356 data = BIT(bit + 16);
1357 if (pull == PIN_CONFIG_BIAS_DISABLE)
1360 if(pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
1363 spin_unlock_irqrestore(&bank->slock, flags);
1367 spin_lock_irqsave(&bank->slock, flags);
1369 /* enable the write to the equivalent lower bits,
1370 * but gpio0 has not the write_enable bit.
1372 if (bank->bank_num == 0) {
1373 data = readl_relaxed(reg);
1374 data &= ~(3 << bit);
1376 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1379 case PIN_CONFIG_BIAS_DISABLE:
1381 case PIN_CONFIG_BIAS_PULL_UP:
1384 case PIN_CONFIG_BIAS_PULL_DOWN:
1387 case PIN_CONFIG_BIAS_BUS_HOLD:
1391 dev_err(info->dev, "unsupported pull setting %d\n",
1398 spin_unlock_irqrestore(&bank->slock, flags);
1401 dev_err(info->dev, "unsupported pinctrl type\n");
1406 DBG_PINCTRL("%s:GPIO%d-%d pull is 0x%x\n", __func__, bank->bank_num, pin_num, data);
1412 * Pinconf_ops handling
1415 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1416 enum pin_config_param pull)
1418 switch (ctrl->type) {
1422 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1423 pull == PIN_CONFIG_BIAS_DISABLE);
1425 return pull ? false : true;
1427 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1429 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1436 static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank,
1437 int pin_num, unsigned long *config, int config_type, unsigned group)
1439 struct rockchip_pinctrl *info = bank->drvdata;
1440 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1441 struct func_to_reg_offset reg_offset[4];//same name count should be less four
1442 struct func_to_reg_offset *func_to_reg;
1443 int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1446 unsigned long flags;
1454 DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1476 //compare group_name
1477 func_to_reg = rk3188_func_to_vol_reg_offset;
1478 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1479 for(i = 0; i < num; i++)
1481 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1482 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1484 reg_offset[j++] = func_to_reg[i];
1485 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1491 func_to_reg = rk3188_func_to_drv_reg_offset;
1492 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1493 for(i = 0; i < num; i++)
1495 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1498 func_to_reg = rk3188_func_to_vol_reg_offset;
1499 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1500 for(ii = 0; ii < num; ii++)
1502 if(!strcmp(func_to_reg[i].vol_name, func_to_reg[ii].group_name))
1504 reg_offset[jj++] = func_to_reg[ii];
1505 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1522 func_to_reg = rk3188_func_to_drv_reg_offset;
1523 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1524 for(i = 0; i < num; i++)
1526 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1528 reg_offset[j++] = func_to_reg[i];
1529 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1550 //compare group_name
1551 func_to_reg = rk3288_func_to_vol_reg_offset;
1552 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1553 for(i = 0; i < num; i++)
1555 //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1556 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1558 reg_offset[j++] = func_to_reg[i];
1559 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1567 ctrl->drv_calc_reg(bank, pin_num, ®, &bit);
1569 data = readl_relaxed(reg) >> bit;
1570 data &= (1 << 2) - 1;
1587 if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1591 printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1596 for(i=0; i < j; i++)
1598 reg = info->reg_base + reg_offset[i].reg_offset;
1599 spin_lock_irqsave(&bank->slock, flags);
1600 data = readl_relaxed(reg) >> reg_offset[i].bit_offset;
1601 data &= reg_offset[i].bit_mask;
1602 spin_unlock_irqrestore(&bank->slock, flags);
1606 DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data);
1610 else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1612 DBG_PINCTRL("%s:GPIO-%d %d drv=0x%x\n",__func__, bank->bank_num, pin_num, (u32)*config);
1620 static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank,
1621 int pin_num, int arg, int config_type, unsigned group)
1623 struct rockchip_pinctrl *info = bank->drvdata;
1624 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1625 struct func_to_reg_offset reg_offset[4];//same name count should be less four
1626 struct func_to_reg_offset *func_to_reg;
1627 int i = 0, ii = 0, j = 0, jj = 0, num = 0;
1628 int data = 0, value = 0;
1630 unsigned long flags;
1638 DBG_PINCTRL("%s:GPIO%d-%d,group=%s, function=%s, type=%d\n", __func__, bank->bank_num, pin_num, info->groups[group].name, info->groups[group].func_name, config_type);
1660 //compare group_name
1661 func_to_reg = rk3188_func_to_vol_reg_offset;
1662 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1663 for(i = 0; i < num; i++)
1665 //lcdc0-vcc-33 = lcdc0-vcc and lcdc0-vcc-18=lcdc0-vcc
1666 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1668 reg_offset[j++] = func_to_reg[i];
1669 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1675 func_to_reg = rk3188_func_to_drv_reg_offset;
1676 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1677 for(i = 0; i < num; i++)
1679 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1682 func_to_reg = rk3188_func_to_vol_reg_offset;
1683 num = ARRAY_SIZE(rk3188_func_to_vol_reg_offset);
1684 for(ii = 0; ii < num; ii++)
1686 if(!strcmp(rk3188_func_to_drv_reg_offset[i].vol_name, func_to_reg[ii].group_name))
1688 reg_offset[jj++] = func_to_reg[ii];
1689 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[ii].group_name);
1706 func_to_reg = rk3188_func_to_drv_reg_offset;
1707 num = ARRAY_SIZE(rk3188_func_to_drv_reg_offset);
1708 for(i = 0; i < num; i++)
1710 if(!strcmp(info->groups[group].func_name, func_to_reg[i].func_name))
1712 reg_offset[j++] = func_to_reg[i];
1713 DBG_PINCTRL("%s:select \"%s\"\n",__func__, func_to_reg[i].func_name);
1734 //compare group_name
1735 func_to_reg = rk3288_func_to_vol_reg_offset;
1736 num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset);
1737 for(i = 0; i < num; i++)
1739 //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc
1740 if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL)
1742 reg_offset[j++] = func_to_reg[i];
1743 DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name);
1751 ctrl->drv_calc_reg(bank, pin_num, ®, &bit);
1753 spin_lock_irqsave(&bank->slock, flags);
1755 if (bank->bank_num == 0) {
1756 data = readl_relaxed(reg);
1761 data |= (3<<(bit+16));
1764 writel_relaxed(data, reg);
1765 spin_unlock_irqrestore(&bank->slock, flags);
1781 if((bank->bank_num == 1) && (pin_num >= 0) && (pin_num <= 3))
1783 bit = pin_num*2 + 4;
1784 reg = info->reg_drv;
1785 spin_lock_irqsave(&bank->slock, flags);
1789 data |= (3<<(bit+16));
1791 writel_relaxed(data, reg);
1792 spin_unlock_irqrestore(&bank->slock, flags);
1796 printk("%s:RK3036 GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1812 if((bank->bank_num == 0)&&((pin_num == GPIO_A6)|| (pin_num == GPIO_A7)||(pin_num == GPIO_B7)||(pin_num == GPIO_C4)))
1814 if(pin_num == GPIO_A6)
1816 else if(pin_num == GPIO_A7)
1818 else if(pin_num == GPIO_B7)
1820 else if(pin_num == GPIO_C4)
1823 reg = info->reg_drv;
1824 spin_lock_irqsave(&bank->slock, flags);
1828 data |= (3<<(bit+16));
1830 writel_relaxed(data, reg);
1831 spin_unlock_irqrestore(&bank->slock, flags);
1835 printk("%s:RK312X GPIO%d-%d could not support driver setting\n",__func__, bank->bank_num, pin_num);
1850 if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG)))
1854 printk("%s:could not find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num);
1858 for(i=0; i < j; i++)
1860 reg = info->reg_base + reg_offset[i].reg_offset;
1861 data |= ((reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset));
1862 data |= ((arg & reg_offset[i].bit_mask) << reg_offset[i].bit_offset);
1863 spin_lock_irqsave(&bank->slock, flags);
1864 writel_relaxed(data, reg);
1865 value = readl_relaxed(reg);
1866 spin_unlock_irqrestore(&bank->slock, flags);
1867 DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=%d,data[%d]=0x%08x,result=0x%08x,arg=%d\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data, value, arg);
1872 else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG))
1874 DBG_PINCTRL("%s:GPIO-%d %d data=0x%x,type=%d\n",__func__, bank->bank_num, pin_num, data,TYPE_DRV_REG);
1881 /* set the pin config settings for a specified pin */
1882 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1883 unsigned long configs, unsigned group)
1885 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1886 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1887 struct rockchip_pin_group *grp = &info->groups[group];
1888 enum pin_config_param param;
1893 param = pinconf_to_config_param(configs);
1894 arg = pinconf_to_config_argument(configs);
1897 case PIN_CONFIG_BIAS_DISABLE:
1898 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1903 case PIN_CONFIG_BIAS_PULL_UP:
1904 case PIN_CONFIG_BIAS_PULL_DOWN:
1905 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1906 case PIN_CONFIG_BIAS_BUS_HOLD:
1907 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1913 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1919 case PIN_CONFIG_POWER_SOURCE:
1920 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_VOL_REG, group);
1925 case PIN_CONFIG_DRIVE_STRENGTH:
1926 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_DRV_REG, group);
1930 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1931 rc = _rockchip_pinconf_set(bank, pin - bank->pin_base, arg, TYPE_TRI_REG, group);
1940 /* cache the config value for rockchip_pinconf_get() */
1941 grp->gconfigs = configs;
1943 DBG_PINCTRL("%s,bank_num=%d,pin=%d,param=%d, arg=%d\n",__func__,bank->bank_num, pin, param, arg);
1949 /* get the pin config settings for a specified pin */
1950 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1951 unsigned long *config, unsigned group)
1953 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1954 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1955 enum pin_config_param param = pinconf_to_config_param(*config);
1959 case PIN_CONFIG_BIAS_DISABLE:
1960 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1965 case PIN_CONFIG_BIAS_PULL_UP:
1966 case PIN_CONFIG_BIAS_PULL_DOWN:
1967 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1968 case PIN_CONFIG_BIAS_BUS_HOLD:
1969 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1972 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1978 case PIN_CONFIG_POWER_SOURCE:
1979 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_VOL_REG, group);
1984 case PIN_CONFIG_DRIVE_STRENGTH:
1985 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_DRV_REG, group);
1989 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1990 rc = _rockchip_pinconf_get(bank, pin - bank->pin_base, config, TYPE_TRI_REG, group);
2001 DBG_PINCTRL("%s:bank_num=%d, pin=%d, param=%d\n",__func__, bank->bank_num, pin, param);
2007 /* set the pin config settings for a specified pin group */
2008 static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev,
2009 unsigned group, unsigned long config)
2011 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2012 const unsigned int *pins;
2014 struct rockchip_pin_bank *bank;
2017 pins = info->groups[group].pins;
2019 for (cnt = 0; cnt < info->groups[group].npins; cnt++)
2021 bank = pin_to_bank(info, pins[cnt]);
2023 DBG_PINCTRL("%s:group[%d]:%s, pins[%d]=%d\n",__func__, group, info->groups[group].name, cnt, pins[cnt]);
2024 rockchip_pinconf_set(pctldev, pins[cnt], config, group);
2030 /* get the pin config settings for a specified pin group */
2031 static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev,
2032 unsigned int group, unsigned long *config)
2034 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2035 const unsigned int *pins;
2036 struct rockchip_pin_bank *bank;
2038 pins = info->groups[group].pins;
2039 bank = pin_to_bank(info, pins[0]);
2041 //rockchip_pinconf_get(pctldev, pins[0], config, group);
2042 *config = info->groups[group].gconfigs;
2043 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2044 printk("%s:group[%d]:%s,config=0x%lx\n",__func__, group, info->groups[group].name, *config);
2048 static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev,
2049 struct seq_file *s, unsigned pin)
2054 static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
2055 struct seq_file *s, unsigned group)
2061 static const struct pinconf_ops rockchip_pinconf_ops = {
2062 .pin_config_group_get = rockchip_pinconf_group_get,
2063 .pin_config_group_set = rockchip_pinconf_group_set,
2064 .pin_config_dbg_show = rockchip_pinconf_dbg_show,
2065 .pin_config_group_dbg_show = rockchip_pinconf_group_dbg_show,
2068 static const struct of_device_id rockchip_bank_match[] = {
2069 { .compatible = "rockchip,gpio-bank" },
2070 { .compatible = "rockchip,rk3188-gpio-bank0" },
2071 { .compatible = "rockchip,rk3288-gpio-bank0" },
2075 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2076 struct device_node *np)
2078 struct device_node *child;
2080 for_each_child_of_node(np, child) {
2081 if (of_match_node(rockchip_bank_match, child))
2085 info->ngroups += of_get_child_count(child);
2089 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2090 struct rockchip_pin_group *grp,
2091 struct rockchip_pinctrl *info,
2094 struct rockchip_pin_bank *bank;
2098 struct union_mode m;
2100 unsigned long *pinconfig;
2103 //printk("%s:group(%d): %s\n", __func__, index, np->name);
2105 /* Initialise group */
2106 grp->name = np->name;
2109 * the binding format is rockchip,pins = <mux>,
2110 * do sanity check and calculate pins number
2112 list = of_get_property(np, "rockchip,pins", &size);
2113 /* we do not check return since it's safe node passed down */
2114 size /= sizeof(*list);
2115 if (!size || size % 1) {
2116 dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n");
2120 grp->npins = size / 1;
2122 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2124 grp->data = devm_kzalloc(info->dev, grp->npins *
2125 sizeof(struct rockchip_pin_config),
2127 if (!grp->pins || !grp->data)
2130 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2132 for (i = 0; i < size; i++) {
2133 m.mode = be32_to_cpu(*list++);
2135 bank = bank_num_to_bank(info, m.mux.bank);
2137 return PTR_ERR(bank);
2139 grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
2140 grp->data[i].func = m.mode;
2146 if (of_find_property(np, "rockchip,pull", NULL))
2148 if (of_find_property(np, "rockchip,voltage", NULL))
2150 if (of_find_property(np, "rockchip,drive", NULL))
2152 if (of_find_property(np, "rockchip,tristate", NULL))
2155 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
2157 if (!of_property_read_u32(np, "rockchip,pull", &val)) {
2158 enum pin_config_param pull = PIN_CONFIG_END;
2160 pull = PIN_CONFIG_BIAS_DISABLE;
2162 pull = PIN_CONFIG_BIAS_PULL_UP;
2164 pull = PIN_CONFIG_BIAS_PULL_DOWN;
2166 pull = PIN_CONFIG_BIAS_BUS_HOLD;
2168 pull = PIN_CONFIG_BIAS_PULL_PIN_DEFAULT;
2170 pinconfig[j++] = pinconf_to_config_packed(pull, val);
2173 if (!of_property_read_u32(np, "rockchip,voltage", &val)) {
2175 pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
2179 if (!of_property_read_u32(np, "rockchip,drive", &val)) {
2181 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
2185 if (!of_property_read_u32(np, "rockchip,tristate", &val)) {
2187 pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
2191 grp->data[i].configs = pinconfig;
2192 grp->data[i].nconfigs = configlen;
2200 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2201 struct rockchip_pinctrl *info,
2204 struct device_node *child;
2205 struct rockchip_pmx_func *func;
2206 struct rockchip_pin_group *grp;
2208 static u32 grp_index;
2211 //printk("%s:parse function(%d): %s\n", __func__, index, np->name);
2213 func = &info->functions[index];
2215 /* Initialise function */
2216 func->name = np->name;
2217 func->ngroups = of_get_child_count(np);
2218 if (func->ngroups <= 0)
2221 func->groups = devm_kzalloc(info->dev,
2222 func->ngroups * sizeof(char *), GFP_KERNEL);
2226 for_each_child_of_node(np, child) {
2227 func->groups[i] = child->name;
2228 grp = &info->groups[grp_index++];
2229 grp->func_name = np->name;
2230 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2234 //printk("%s:grp->func_name(%d): %s\n", __func__, grp_index, grp->func_name);
2240 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2241 struct rockchip_pinctrl *info)
2243 struct device *dev = &pdev->dev;
2244 struct device_node *np = dev->of_node;
2245 struct device_node *child;
2249 rockchip_pinctrl_child_count(info, np);
2251 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2252 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2254 info->functions = devm_kzalloc(dev, info->nfunctions *
2255 sizeof(struct rockchip_pmx_func),
2257 if (!info->functions) {
2258 dev_err(dev, "failed to allocate memory for function list\n");
2262 info->groups = devm_kzalloc(dev, info->ngroups *
2263 sizeof(struct rockchip_pin_group),
2265 if (!info->groups) {
2266 dev_err(dev, "failed allocate memory for ping group list\n");
2272 for_each_child_of_node(np, child) {
2273 if (of_match_node(rockchip_bank_match, child))
2276 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2278 dev_err(&pdev->dev, "failed to parse function\n");
2286 static int rockchip_pinctrl_register(struct platform_device *pdev,
2287 struct rockchip_pinctrl *info)
2289 struct pinctrl_desc *ctrldesc = &info->pctl;
2290 struct pinctrl_pin_desc *pindesc, *pdesc;
2291 struct rockchip_pin_bank *pin_bank;
2295 ctrldesc->name = "rockchip-pinctrl";
2296 ctrldesc->owner = THIS_MODULE;
2297 ctrldesc->pctlops = &rockchip_pctrl_ops;
2298 ctrldesc->pmxops = &rockchip_pmx_ops;
2299 ctrldesc->confops = &rockchip_pinconf_ops;
2301 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2302 info->ctrl->nr_pins, GFP_KERNEL);
2304 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2307 ctrldesc->pins = pindesc;
2308 ctrldesc->npins = info->ctrl->nr_pins;
2311 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2312 pin_bank = &info->ctrl->pin_banks[bank];
2313 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2315 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2316 pin_bank->name, pin);
2321 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
2322 if (!info->pctl_dev) {
2323 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2327 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2328 pin_bank = &info->ctrl->pin_banks[bank];
2329 pin_bank->grange.name = pin_bank->name;
2330 pin_bank->grange.id = bank;
2331 pin_bank->grange.pin_base = pin_bank->pin_base;
2332 pin_bank->grange.base = pin_bank->gpio_chip.base;
2333 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2334 pin_bank->grange.gc = &pin_bank->gpio_chip;
2335 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2338 ret = rockchip_pinctrl_parse_dt(pdev, info);
2340 pinctrl_unregister(info->pctl_dev);
2351 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
2353 struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2354 struct rockchip_pinctrl *info = bank->drvdata;
2357 if(bank->bank_num == 15)
2359 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2364 DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2365 return pinctrl_request_gpio(chip->base + offset);
2368 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
2370 struct rockchip_pin_bank *bank = gc_to_pin_bank(chip);
2371 struct rockchip_pinctrl *info = bank->drvdata;
2374 if(bank->bank_num == 15)
2376 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2379 DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2380 pinctrl_free_gpio(chip->base + offset);
2383 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2385 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2386 struct rockchip_pinctrl *info = bank->drvdata;
2387 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2388 unsigned long flags;
2392 spin_lock_irqsave(&bank->slock, flags);
2395 data &= ~BIT(offset);
2397 data |= BIT(offset);
2400 spin_unlock_irqrestore(&bank->slock, flags);
2402 DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, value);
2406 * Returns the level of the pin for input direction and setting of the DR
2407 * register for output gpios.
2409 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2411 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2412 struct rockchip_pinctrl *info = bank->drvdata;
2416 data = readl(bank->reg_base + GPIO_EXT_PORT);
2420 DBG_PINCTRL("%s:GPIO%d-%d level = %d\n", __func__, bank->bank_num, offset, data);
2425 * gpiolib gpio_direction_input callback function. The setting of the pin
2426 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2429 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2431 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2432 struct rockchip_pinctrl *info = bank->drvdata;
2435 if(bank->bank_num == 15)
2437 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2441 DBG_PINCTRL("%s:GPIO%d-%d\n", __func__, bank->bank_num, offset);
2442 return pinctrl_gpio_direction_input(gc->base + offset);
2446 * gpiolib gpio_direction_output callback function. The setting of the pin
2447 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2450 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2451 unsigned offset, int value)
2453 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2454 struct rockchip_pinctrl *info = bank->drvdata;
2457 if(bank->bank_num == 15)
2459 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2463 rockchip_gpio_set(gc, offset, value);
2465 DBG_PINCTRL("%s:set GPIO%d-%d level %d\n", __func__, bank->bank_num, offset, value);
2466 return pinctrl_gpio_direction_output(gc->base + offset);
2470 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2471 * and a virtual IRQ, if not already present.
2473 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2475 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
2476 struct rockchip_pinctrl *info = bank->drvdata;
2481 if(bank->bank_num == 15)
2483 printk("%s:error bank num %d is out of range\n",__func__, bank->bank_num);
2490 virq = irq_create_mapping(bank->domain, offset);
2492 DBG_PINCTRL("%s:virq=%d, GPIO%d-%d\n", __func__, virq, bank->bank_num, offset);
2494 return (virq) ? : -ENXIO;
2497 static const struct gpio_chip rockchip_gpiolib_chip = {
2498 .request = rockchip_gpio_request,
2499 .free = rockchip_gpio_free,
2500 .set = rockchip_gpio_set,
2501 .get = rockchip_gpio_get,
2502 .direction_input = rockchip_gpio_direction_input,
2503 .direction_output = rockchip_gpio_direction_output,
2504 .to_irq = rockchip_gpio_to_irq,
2505 .owner = THIS_MODULE,
2509 * Interrupt handling
2512 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
2514 struct irq_chip *chip = irq_get_chip(irq);
2515 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
2516 struct rockchip_pinctrl *info = bank->drvdata;
2519 u32 polarity = 0, data = 0;
2521 bool edge_changed = false;
2523 chained_irq_enter(chip, desc);
2525 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2527 if (bank->toggle_edge_mode) {
2528 polarity = readl_relaxed(bank->reg_base +
2530 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2538 virq = irq_linear_revmap(bank->domain, irq);
2541 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2545 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2548 * Triggering IRQ on both rising and falling edge
2549 * needs manual intervention.
2551 if (bank->toggle_edge_mode & BIT(irq)) {
2552 if (data & BIT(irq))
2553 polarity &= ~BIT(irq);
2555 polarity |= BIT(irq);
2557 edge_changed = true;
2560 generic_handle_irq(virq);
2563 DBG_PINCTRL("%s:irq=%d,%s\n",__func__, irq, bank->name);
2566 if (bank->toggle_edge_mode && edge_changed) {
2567 /* Interrupt params should only be set with ints disabled */
2568 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
2569 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
2570 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
2571 writel(data, bank->reg_base + GPIO_INTEN);
2574 chained_irq_exit(chip, desc);
2577 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2579 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2580 struct rockchip_pinctrl *info = bank->drvdata;
2581 u32 mask = BIT(d->hwirq);
2586 unsigned long flags;
2589 /* make sure the pin is configured as gpio input */
2590 mux = (bank->bank_num << 12) | (((d->hwirq / 8) + 0x0A) << 8) | ((d->hwirq % 8)<< 4) | RK_FUNC_GPIO;
2591 rockchip_set_mux(bank, d->hwirq, mux);
2593 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2595 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2597 if (type & IRQ_TYPE_EDGE_BOTH)
2598 __irq_set_handler_locked(d->irq, handle_edge_irq);
2600 __irq_set_handler_locked(d->irq, handle_level_irq);
2602 spin_lock_irqsave(&bank->slock, flags);
2604 level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
2605 polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
2608 case IRQ_TYPE_EDGE_BOTH:
2609 bank->toggle_edge_mode |= mask;
2613 * Determine gpio state. If 1 next interrupt should be falling
2616 data = readl(bank->reg_base + GPIO_EXT_PORT);
2622 case IRQ_TYPE_EDGE_RISING:
2623 bank->toggle_edge_mode &= ~mask;
2627 case IRQ_TYPE_EDGE_FALLING:
2628 bank->toggle_edge_mode &= ~mask;
2632 case IRQ_TYPE_LEVEL_HIGH:
2633 bank->toggle_edge_mode &= ~mask;
2637 case IRQ_TYPE_LEVEL_LOW:
2638 bank->toggle_edge_mode &= ~mask;
2643 //spin_unlock_irqrestore(&bank->slock, flags);
2647 writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
2648 writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
2650 spin_unlock_irqrestore(&bank->slock, flags);
2652 DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
2657 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
2659 u32 val = __raw_readl(reg_base + offset);
2666 __raw_writel(val, reg_base + offset);
2669 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank, unsigned gpio)
2671 while (gpio >= (bank->pin_base + bank->nr_pins))
2674 return gpio - bank->pin_base;
2677 static inline unsigned offset_to_bit(unsigned offset)
2679 return 1u << offset;
2682 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
2684 rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
2687 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
2689 rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
2692 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
2694 rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
2697 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
2699 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2700 struct rockchip_pinctrl *info = bank->drvdata;
2703 unsigned long flags;
2706 spin_lock_irqsave(&bank->slock, flags);
2710 bank->suspend_wakeup |= BIT(bit);
2714 bank->suspend_wakeup &= ~BIT(bit);
2716 spin_unlock_irqrestore(&bank->slock, flags);
2718 DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2722 static void rockchip_gpio_irq_unmask(struct irq_data *d)
2724 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2725 struct rockchip_pinctrl *info = bank->drvdata;
2727 unsigned long flags;
2730 spin_lock_irqsave(&bank->slock, flags);
2731 GPIOEnableIntr(bank->reg_base, bit);
2732 spin_unlock_irqrestore(&bank->slock, flags);
2734 DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2737 static void rockchip_gpio_irq_mask(struct irq_data *d)
2739 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2740 struct rockchip_pinctrl *info = bank->drvdata;
2741 //u32 bit = gpio_to_bit(bank, d->irq);
2743 unsigned long flags;
2746 spin_lock_irqsave(&bank->slock, flags);
2747 GPIODisableIntr(bank->reg_base, bit);
2748 spin_unlock_irqrestore(&bank->slock, flags);
2750 DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2753 static void rockchip_gpio_irq_ack(struct irq_data *d)
2755 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
2756 struct rockchip_pinctrl *info = bank->drvdata;
2757 //u32 bit = gpio_to_bit(bank, d->irq);
2761 GPIOAckIntr(bank->reg_base, bit);
2763 DBG_PINCTRL("%s:irq=%d,hwirq=%d,bank->reg_base=0x%x,bit=%d\n",__func__,d->irq, (int)d->hwirq, (int)bank->reg_base,bit);
2767 static struct irq_chip rockchip_gpio_irq_chip = {
2769 .irq_ack = rockchip_gpio_irq_ack,
2770 .irq_disable = rockchip_gpio_irq_mask,
2771 .irq_mask = rockchip_gpio_irq_mask,
2772 .irq_unmask = rockchip_gpio_irq_unmask,
2773 .irq_set_type = rockchip_gpio_irq_set_type,
2774 .irq_set_wake = rockchip_gpio_irq_set_wake,
2778 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
2779 irq_hw_number_t hwirq)
2781 struct rockchip_pin_bank *bank = d->host_data;
2782 struct rockchip_pinctrl *info = bank->drvdata;
2783 struct irq_data *irq_data = irq_get_irq_data(irq);
2788 printk("%s:bank=0x%p,irq=%d\n",__func__,bank, irq);
2792 irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip, handle_level_irq);
2793 irq_set_chip_data(irq, bank);
2794 set_irq_flags(irq, IRQF_VALID);
2796 irq_data->hwirq = hwirq;
2797 irq_data->irq = irq;
2799 DBG_PINCTRL("%s:irq=%d\n",__func__,irq);
2803 const struct irq_domain_ops rockchip_gpio_irq_ops = {
2804 .map = rockchip_gpio_irq_map,
2805 .xlate = irq_domain_xlate_twocell,
2809 static int rockchip_interrupts_register(struct platform_device *pdev,
2810 struct rockchip_pinctrl *info)
2812 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2813 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2814 //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2817 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2819 dev_warn(&pdev->dev, "bank %s is not valid\n",
2824 __raw_writel(0, bank->reg_base + GPIO_INTEN);
2826 bank->drvdata = info;
2827 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2828 &rockchip_gpio_irq_ops, bank);
2829 if (!bank->domain) {
2830 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2835 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
2836 printk("%s:bank_num=%d\n",__func__,bank->bank_num);
2838 irq_set_handler_data(bank->irq, bank);
2839 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
2847 static int rockchip_gpiolib_register(struct platform_device *pdev,
2848 struct rockchip_pinctrl *info)
2850 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2851 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2852 struct gpio_chip *gc;
2856 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2858 dev_warn(&pdev->dev, "bank %s is not valid\n",
2863 bank->gpio_chip = rockchip_gpiolib_chip;
2865 gc = &bank->gpio_chip;
2866 gc->base = bank->pin_base;
2867 gc->ngpio = bank->nr_pins;
2868 gc->dev = &pdev->dev;
2869 gc->of_node = bank->of_node;
2870 gc->label = bank->name;
2872 ret = gpiochip_add(gc);
2874 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2880 rockchip_interrupts_register(pdev, info);
2885 for (--i, --bank; i >= 0; --i, --bank) {
2889 if (gpiochip_remove(&bank->gpio_chip))
2890 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
2891 bank->gpio_chip.label);
2896 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2897 struct rockchip_pinctrl *info)
2899 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2900 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2904 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
2908 ret = gpiochip_remove(&bank->gpio_chip);
2912 dev_err(&pdev->dev, "gpio chip remove failed\n");
2917 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2920 struct resource res;
2921 int rk3188 = 0, rk3288 = 0;
2923 //"base", "mux_bank0", "pull_bank0", "drv_bank0"
2924 if (of_address_to_resource(bank->of_node, 0, &res)) {
2925 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2928 bank->reg_base = devm_ioremap_resource(dev, &res);
2929 if (IS_ERR(bank->reg_base))
2930 return PTR_ERR(bank->reg_base);
2932 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2935 * special case, where parts of the pull setting-registers are
2936 * part of the PMU register space
2938 rk3188 = of_device_is_compatible(bank->of_node, "rockchip,rk3188-gpio-bank0");
2940 rk3288 = of_device_is_compatible(bank->of_node, "rockchip,rk3288-gpio-bank0");
2944 bank->bank_type = RK3188_BANK0;
2946 if (of_address_to_resource(bank->of_node, 1, &res)) {
2947 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2950 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2951 if (IS_ERR(bank->reg_pull_bank0))
2952 return PTR_ERR(bank->reg_pull_bank0);
2954 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2959 bank->bank_type = RK3288_BANK0;
2960 if (of_address_to_resource(bank->of_node, 1, &res)) {
2961 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2964 bank->reg_mux_bank0 = devm_ioremap_resource(dev, &res);
2965 if (IS_ERR(bank->reg_mux_bank0))
2966 return PTR_ERR(bank->reg_mux_bank0);
2968 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2970 if (of_address_to_resource(bank->of_node, 2, &res)) {
2971 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2974 bank->reg_pull_bank0 = devm_ioremap_resource(dev, &res);
2975 if (IS_ERR(bank->reg_pull_bank0))
2976 return PTR_ERR(bank->reg_pull_bank0);
2978 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2980 if (of_address_to_resource(bank->of_node, 3, &res)) {
2981 dev_err(dev, "cannot find IO resource for bank %s\n", bank->name);
2984 bank->reg_drv_bank0 = devm_ioremap_resource(dev, &res);
2985 if (IS_ERR(bank->reg_drv_bank0))
2986 return PTR_ERR(bank->reg_drv_bank0);
2988 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res.name, res.start, res.end);
2993 bank->bank_type = COMMON_BANK;
2996 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2998 bank->clk = of_clk_get(bank->of_node, 0);
2999 if (IS_ERR(bank->clk)) {
3000 dev_warn(dev, "failed to get clk for bank %s\n", bank->name);
3003 clk_prepare_enable(bank->clk);
3007 static const struct of_device_id rockchip_pinctrl_dt_match[];
3009 /* retrieve the soc specific data */
3010 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3011 struct rockchip_pinctrl *d,
3012 struct platform_device *pdev)
3014 const struct of_device_id *match;
3015 struct device_node *node = pdev->dev.of_node;
3016 struct device_node *np;
3017 struct rockchip_pin_ctrl *ctrl;
3018 struct rockchip_pin_bank *bank;
3021 match = of_match_node(rockchip_pinctrl_dt_match, node);
3022 ctrl = (struct rockchip_pin_ctrl *)match->data;
3024 for_each_child_of_node(node, np) {
3025 if (!of_find_property(np, "gpio-controller", NULL))
3028 bank = ctrl->pin_banks;
3029 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3030 if (!strcmp(bank->name, np->name)) {
3033 if (!rockchip_get_bank_data(bank, &pdev->dev))
3040 bank = ctrl->pin_banks;
3041 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3042 spin_lock_init(&bank->slock);
3044 bank->pin_base = ctrl->nr_pins;
3045 ctrl->nr_pins += bank->nr_pins;
3053 static int rockchip_pinctrl_suspend(void)
3055 struct rockchip_pinctrl *info = g_info;
3056 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3057 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3061 for(n=0; n<ctrl->nr_banks-1; n++)
3065 for(i=0; i<0x60; i=i+4)
3067 value = readl_relaxed(bank->reg_base + i);
3068 printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3071 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
3072 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
3074 if (!bank->suspend_wakeup)
3075 clk_disable_unprepare(bank->clk);
3077 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3078 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->suspend_wakeup);
3085 static void rockchip_pinctrl_resume(void)
3087 struct rockchip_pinctrl *info = g_info;
3088 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3089 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3093 for(n=0; n<ctrl->nr_banks-1; n++)
3097 for(i=0; i<0x60; i=i+4)
3099 u32 value = readl_relaxed(bank->reg_base + i);
3100 printk("%s:bank_num=%d,reg[0x%x+0x%x]=0x%x,bank_name=%s\n",__func__,bank->bank_num, bank->reg_base, i, value, bank->name);
3103 if (!bank->suspend_wakeup)
3104 clk_prepare_enable(bank->clk);
3106 /* keep enable for resume irq */
3107 isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
3108 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->reg_base + GPIO_INTEN);
3110 if(atomic_read(&info->bank_debug_flag) == (bank->bank_num + 1))
3111 printk("%s:bank_num=%d, suspend_wakeup=0x%x\n",__func__, bank->bank_num, bank->saved_wakeup | (bank->suspend_wakeup & isr));
3118 static struct syscore_ops rockchip_gpio_syscore_ops = {
3119 .suspend = rockchip_pinctrl_suspend,
3120 .resume = rockchip_pinctrl_resume,
3125 static struct gpio_init_config *
3126 of_get_gpio_init_config(struct device *dev, struct device_node *np)
3128 struct gpio_init_config *config;
3130 enum of_gpio_flags flags;
3132 config = devm_kzalloc(dev,
3133 sizeof(struct gpio_init_config),
3136 return ERR_PTR(-ENOMEM);
3139 config->nr_gpios = of_gpio_named_count(np, "init-gpios");
3141 config->gpios = devm_kzalloc(dev,
3142 sizeof(struct gpio) * config->nr_gpios,
3145 return ERR_PTR(-ENOMEM);
3147 for (i = 0; i < config->nr_gpios; i++) {
3148 //gpio = of_get_named_gpio(np, "gpios", i);
3149 gpio = of_get_named_gpio_flags(np, "init-gpios", i, &flags);
3152 config->gpios[i].gpio = gpio;
3153 config->gpios[i].flags = flags & OF_GPIO_ACTIVE_LOW;
3155 printk("%s:gpio[%d] = %d, value = %lu\n",__func__, i, gpio, config->gpios[i].flags);
3162 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3164 struct rockchip_pinctrl *info;
3165 struct device *dev = &pdev->dev;
3166 struct rockchip_pin_ctrl *ctrl;
3167 struct resource *res;
3169 struct device_node *np;
3172 if (!dev->of_node) {
3173 dev_err(dev, "device tree node not found\n");
3177 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3181 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3183 dev_err(dev, "driver data not available\n");
3191 /*if debug GPIO0 then
3192 *atomic_set(&info->bank_debug_flag, 1);
3193 *atomic_set(&info->pin_debug_flag, 0);
3194 *if debug GPIO0-10 then
3195 *atomic_set(&info->bank_debug_flag, 1);
3196 *atomic_set(&info->pin_debug_flag, 11);
3198 atomic_set(&info->bank_debug_flag, 8);
3199 atomic_set(&info->pin_debug_flag, 14);
3201 printk("%s:name=%s,type=%d\n",__func__, ctrl->label, (int)ctrl->type);
3203 //"base", "mux", "pull", "drv";
3208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3209 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3210 if (IS_ERR(info->reg_base))
3211 return PTR_ERR(info->reg_base);
3212 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3218 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3219 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3220 if (IS_ERR(info->reg_base))
3221 return PTR_ERR(info->reg_base);
3222 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3224 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3225 info->reg_mux = devm_ioremap_resource(&pdev->dev, res);
3226 if (IS_ERR(info->reg_mux))
3227 return PTR_ERR(info->reg_mux);
3228 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3230 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3231 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3232 if (IS_ERR(info->reg_pull))
3233 return PTR_ERR(info->reg_pull);
3234 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3236 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
3237 info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3238 if (IS_ERR(info->reg_drv))
3239 return PTR_ERR(info->reg_drv);
3240 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3246 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
3247 if (IS_ERR(info->reg_base))
3248 return PTR_ERR(info->reg_base);
3249 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3251 info->reg_mux = info->reg_base;
3253 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3254 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
3255 if (IS_ERR(info->reg_pull))
3256 return PTR_ERR(info->reg_pull);
3257 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3259 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
3260 info->reg_drv = devm_ioremap_resource(&pdev->dev, res);
3261 if (IS_ERR(info->reg_drv))
3262 return PTR_ERR(info->reg_drv);
3263 printk("%s:name=%s start=0x%x,end=0x%x\n",__func__,res->name, res->start, res->end);
3268 printk("%s:unknown chip type %d\n",__func__, (int)ctrl->type);
3274 ret = rockchip_gpiolib_register(pdev, info);
3278 ret = rockchip_pinctrl_register(pdev, info);
3280 rockchip_gpiolib_unregister(pdev, info);
3285 if (of_find_property(np, "init-gpios", NULL))
3287 info->config = of_get_gpio_init_config(&pdev->dev, np);
3288 if (IS_ERR(info->config))
3289 return PTR_ERR(info->config);
3291 ret = gpio_request_array(info->config->gpios, info->config->nr_gpios);
3293 dev_err(&pdev->dev, "Could not obtain init GPIOs: %d\n", ret);
3297 for(i=0; i<info->config->nr_gpios; i++)
3299 gpio_direction_output(info->config->gpios[i].gpio, info->config->gpios[i].flags);
3303 pinctrl_debugfs_init(info);
3305 platform_set_drvdata(pdev, info);
3307 register_syscore_ops(&rockchip_gpio_syscore_ops);
3309 printk("%s:init ok\n",__func__);
3314 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3315 PIN_BANK(0, 32, "gpio0"),
3316 PIN_BANK(1, 32, "gpio1"),
3317 PIN_BANK(2, 32, "gpio2"),
3318 PIN_BANK(3, 32, "gpio3"),
3320 PIN_BANK(15, 32, "gpio15"),//virtual bank
3323 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3324 .pin_banks = rk2928_pin_banks,
3325 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3326 .label = "RK2928-GPIO",
3329 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3332 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3333 PIN_BANK(0, 32, "gpio0"),
3334 PIN_BANK(1, 32, "gpio1"),
3335 PIN_BANK(2, 32, "gpio2"),
3336 PIN_BANK(3, 32, "gpio3"),
3337 PIN_BANK(4, 32, "gpio4"),
3338 PIN_BANK(6, 16, "gpio6"),
3339 PIN_BANK(15, 32, "gpio15"),//virtual bank
3342 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3343 .pin_banks = rk3066a_pin_banks,
3344 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3345 .label = "RK3066a-GPIO",
3348 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3351 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3352 PIN_BANK(0, 32, "gpio0"),
3353 PIN_BANK(1, 32, "gpio1"),
3354 PIN_BANK(2, 32, "gpio2"),
3355 PIN_BANK(3, 32, "gpio3"),
3357 PIN_BANK(15, 32, "gpio15"),//virtual bank
3360 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3361 .pin_banks = rk3066b_pin_banks,
3362 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3363 .label = "RK3066b-GPIO",
3368 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3369 PIN_BANK(0, 32, "gpio0"),
3370 PIN_BANK(1, 32, "gpio1"),
3371 PIN_BANK(2, 32, "gpio2"),
3372 PIN_BANK(3, 32, "gpio3"),
3374 PIN_BANK(15, 32, "gpio15"),//virtual bank
3377 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3378 .pin_banks = rk3188_pin_banks,
3379 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3380 .label = "RK3188-GPIO",
3383 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3387 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3388 PIN_BANK(0, 24, "gpio0"),
3389 PIN_BANK(1, 32, "gpio1"),
3390 PIN_BANK(2, 32, "gpio2"),
3391 PIN_BANK(3, 32, "gpio3"),
3392 PIN_BANK(4, 32, "gpio4"),
3393 PIN_BANK(5, 32, "gpio5"),
3394 PIN_BANK(6, 32, "gpio6"),
3395 PIN_BANK(7, 32, "gpio7"),
3396 PIN_BANK(8, 32, "gpio8"),
3399 PIN_BANK(15, 32, "gpio15"),//virtual bank
3402 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3403 .pin_banks = rk3288_pin_banks,
3404 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3405 .label = "RK3288-GPIO",
3408 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3409 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3413 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3414 PIN_BANK(0, 32, "gpio0"),
3415 PIN_BANK(1, 32, "gpio1"),
3416 PIN_BANK(2, 32, "gpio2"),
3418 PIN_BANK(15, 32, "gpio15"),//virtual bank
3421 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3422 .pin_banks = rk3036_pin_banks,
3423 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3424 .label = "rk3036-GPIO",
3427 .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
3431 static struct rockchip_pin_bank rk312x_pin_banks[] = {
3432 PIN_BANK(0, 32, "gpio0"),
3433 PIN_BANK(1, 32, "gpio1"),
3434 PIN_BANK(2, 32, "gpio2"),
3435 PIN_BANK(3, 32, "gpio3"),
3437 PIN_BANK(15, 32, "gpio15"),//virtual bank
3440 static struct rockchip_pin_ctrl rk312x_pin_ctrl = {
3441 .pin_banks = rk312x_pin_banks,
3442 .nr_banks = ARRAY_SIZE(rk312x_pin_banks),
3443 .label = "rk312x-GPIO",
3446 .pull_calc_reg = rk312x_calc_pull_reg_and_bit,
3451 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3452 { .compatible = "rockchip,rk2928-pinctrl",
3453 .data = (void *)&rk2928_pin_ctrl },
3454 { .compatible = "rockchip,rk3066a-pinctrl",
3455 .data = (void *)&rk3066a_pin_ctrl },
3456 { .compatible = "rockchip,rk3066b-pinctrl",
3457 .data = (void *)&rk3066b_pin_ctrl },
3458 { .compatible = "rockchip,rk3188-pinctrl",
3459 .data = (void *)&rk3188_pin_ctrl },
3460 { .compatible = "rockchip,rk3288-pinctrl",
3461 .data = (void *)&rk3288_pin_ctrl },
3462 { .compatible = "rockchip,rk3036-pinctrl",
3463 .data = (void *)&rk3036_pin_ctrl },
3464 { .compatible = "rockchip,rk312x-pinctrl",
3465 .data = (void *)&rk312x_pin_ctrl },
3468 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3470 static struct platform_driver rockchip_pinctrl_driver = {
3471 .probe = rockchip_pinctrl_probe,
3473 .name = "rockchip-pinctrl",
3474 .owner = THIS_MODULE,
3475 .of_match_table = rockchip_pinctrl_dt_match,
3479 static int __init rockchip_pinctrl_drv_register(void)
3481 return platform_driver_register(&rockchip_pinctrl_driver);
3483 postcore_initcall(rockchip_pinctrl_drv_register);
3485 MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
3486 MODULE_DESCRIPTION("Rockchip pinctrl driver");
3487 MODULE_LICENSE("GPL v2");