2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/interrupt.h>
30 #include <linux/bitops.h>
31 #include <linux/gpio.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/machine.h>
35 #include <linux/pinctrl/pinconf.h>
36 #include <linux/pinctrl/pinctrl.h>
37 #include <linux/pinctrl/pinmux.h>
38 #include <linux/pinctrl/pinconf-generic.h>
39 #include <linux/irqchip/chained_irq.h>
40 #include <linux/clk.h>
41 #include <linux/regmap.h>
42 #include <linux/mfd/syscon.h>
43 #include <linux/syscore_ops.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
51 #define pinctrl_dbg(dev, format, arg...) \
52 dev_printk(KERN_INFO , dev , format , ## arg)
54 #define pinctrl_dbg(dev, format, arg...)
58 /* GPIO control registers */
59 #define GPIO_SWPORT_DR 0x00
60 #define GPIO_SWPORT_DDR 0x04
61 #define GPIO_INTEN 0x30
62 #define GPIO_INTMASK 0x34
63 #define GPIO_INTTYPE_LEVEL 0x38
64 #define GPIO_INT_POLARITY 0x3c
65 #define GPIO_INT_STATUS 0x40
66 #define GPIO_INT_RAWSTATUS 0x44
67 #define GPIO_DEBOUNCE 0x48
68 #define GPIO_PORTS_EOI 0x4c
69 #define GPIO_EXT_PORT 0x50
70 #define GPIO_LS_SYNC 0x60
72 enum rockchip_pinctrl_type {
82 * Encode variants of iomux registers into a type variable
84 #define IOMUX_GPIO_ONLY BIT(0)
85 #define IOMUX_WIDTH_4BIT BIT(1)
86 #define IOMUX_SOURCE_PMU BIT(2)
87 #define IOMUX_UNROUTED BIT(3)
90 * @type: iomux variant using IOMUX_* constants
91 * @offset: if initialized to -1 it will be autocalculated, by specifying
92 * an initial offset value the relevant source offset can be reset
93 * to a new value for autocalculating the following iomux registers.
95 struct rockchip_iomux {
101 * @reg_base: register base of the gpio bank
102 * @reg_pull: optional separate register for additional pull settings
103 * @clk: clock of the gpio bank
104 * @irq: interrupt of the gpio bank
105 * @pin_base: first pin number
106 * @nr_pins: number of pins in this bank
107 * @name: name of the bank
108 * @bank_num: number of the bank, to account for holes
109 * @iomux: array describing the 4 iomux sources of the bank
110 * @valid: are all necessary informations present
111 * @of_node: dt node of this bank
112 * @drvdata: common pinctrl basedata
113 * @domain: irqdomain of the gpio bank
114 * @gpio_chip: gpiolib chip
115 * @grange: gpio range
116 * @slock: spinlock for the gpio bank
118 struct rockchip_pin_bank {
119 void __iomem *reg_base;
120 struct regmap *regmap_pull;
127 struct rockchip_iomux iomux[4];
129 struct device_node *of_node;
130 struct rockchip_pinctrl *drvdata;
131 struct irq_domain *domain;
132 struct gpio_chip gpio_chip;
133 struct pinctrl_gpio_range grange;
134 /*spinlock for the gpio bank*/
136 u32 toggle_edge_mode;
141 #define PIN_BANK(id, pins, label) \
154 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
160 { .type = iom0, .offset = -1 }, \
161 { .type = iom1, .offset = -1 }, \
162 { .type = iom2, .offset = -1 }, \
163 { .type = iom3, .offset = -1 }, \
169 struct rockchip_pin_ctrl {
170 struct rockchip_pin_bank *pin_banks;
174 enum rockchip_pinctrl_type type;
178 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
179 int pin_num, struct regmap **regmap,
183 struct rockchip_pin_config {
185 unsigned long *configs;
186 unsigned int nconfigs;
190 * struct rockchip_pin_group: represent group of pins of a pinmux function.
191 * @name: name of the pin group, used to lookup the group.
192 * @pins: the pins included in this group.
193 * @npins: number of pins included in this group.
194 * @func: the mux function number to be programmed when selected.
195 * @configs: the config values to be set for each pin
196 * @nconfigs: number of configs for each pin
198 struct rockchip_pin_group {
202 struct rockchip_pin_config *data;
206 * struct rockchip_pmx_func: represent a pin function.
207 * @name: name of the pin function, used to lookup the function.
208 * @groups: one or more names of pin groups that provide this function.
209 * @num_groups: number of groups included in @groups.
211 struct rockchip_pmx_func {
217 struct rockchip_pinctrl {
218 struct regmap *regmap_base;
220 struct regmap *regmap_pull;
221 struct regmap *regmap_pmu;
223 struct rockchip_pin_ctrl *ctrl;
224 struct pinctrl_desc pctl;
225 struct pinctrl_dev *pctl_dev;
226 struct rockchip_pin_group *groups;
227 unsigned int ngroups;
228 struct rockchip_pmx_func *functions;
229 unsigned int nfunctions;
232 static struct regmap_config rockchip_regmap_config = {
237 static struct rockchip_pinctrl *g_info;
239 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
241 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
244 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
245 const struct rockchip_pinctrl *info,
250 for (i = 0; i < info->ngroups; i++) {
251 if (!strcmp(info->groups[i].name, name))
252 return &info->groups[i];
259 * given a pin number that is local to a pin controller, find out the pin bank
260 * and the register base of the pin bank.
262 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
265 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
267 while (pin >= (b->pin_base + b->nr_pins))
273 static struct rockchip_pin_bank *bank_num_to_bank(
274 struct rockchip_pinctrl *info,
277 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
280 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
281 if (b->bank_num == num)
285 return ERR_PTR(-EINVAL);
289 * Pinctrl_ops handling
292 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
294 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
296 return info->ngroups;
299 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
302 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
304 return info->groups[selector].name;
307 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
308 unsigned selector, const unsigned **pins,
311 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
313 if (selector >= info->ngroups)
316 *pins = info->groups[selector].pins;
317 *npins = info->groups[selector].npins;
322 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
323 struct device_node *np,
324 struct pinctrl_map **map, unsigned *num_maps)
326 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
327 const struct rockchip_pin_group *grp;
328 struct pinctrl_map *new_map;
329 struct device_node *parent;
334 * first find the group of this node and check if we need to create
335 * config maps for pins
337 grp = pinctrl_name_to_group(info, np->name);
339 dev_err(info->dev, "unable to find group for node %s\n",
344 map_num += grp->npins;
345 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
354 parent = of_get_parent(np);
356 devm_kfree(pctldev->dev, new_map);
359 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
360 new_map[0].data.mux.function = parent->name;
361 new_map[0].data.mux.group = np->name;
364 /* create config map */
366 for (i = 0; i < grp->npins; i++) {
367 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
368 new_map[i].data.configs.group_or_pin =
369 pin_get_name(pctldev, grp->pins[i]);
370 new_map[i].data.configs.configs = grp->data[i].configs;
371 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
374 pinctrl_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
375 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
380 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
381 struct pinctrl_map *map, unsigned num_maps)
385 static const struct pinctrl_ops rockchip_pctrl_ops = {
386 .get_groups_count = rockchip_get_groups_count,
387 .get_group_name = rockchip_get_group_name,
388 .get_group_pins = rockchip_get_group_pins,
389 .dt_node_to_map = rockchip_dt_node_to_map,
390 .dt_free_map = rockchip_dt_free_map,
397 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
399 struct rockchip_pinctrl *info = bank->drvdata;
400 int iomux_num = (pin / 8);
401 struct regmap *regmap;
409 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
410 dev_err(info->dev, "pin %d is unrouted\n", pin);
414 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
417 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
418 ? info->regmap_pmu : info->regmap_base;
420 /* get basic quadrupel of mux registers and the correct reg inside */
421 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
422 reg = bank->iomux[iomux_num].offset;
423 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
431 ret = regmap_read(regmap, reg, &val);
435 return ((val >> bit) & mask);
439 * Set a new mux function for a pin.
441 * The register is divided into the upper and lower 16 bit. When changing
442 * a value, the previous register value is not read and changed. Instead
443 * it seems the changed bits are marked in the upper 16 bit, while the
444 * changed value gets set in the same offset in the lower 16 bit.
445 * All pin settings seem to be 2 bit wide in both the upper and lower
447 * @bank: pin bank to change
448 * @pin: pin to change
449 * @mux: new mux function to set
451 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
453 struct rockchip_pinctrl *info = bank->drvdata;
454 int iomux_num = (pin / 8);
455 struct regmap *regmap;
464 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
465 dev_err(info->dev, "pin %d is unrouted\n", pin);
469 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
470 if (mux != RK_FUNC_GPIO) {
472 "pin %d only supports a gpio mux\n", pin);
479 pinctrl_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
480 bank->bank_num, pin, mux);
482 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
483 ? info->regmap_pmu : info->regmap_base;
485 /* get basic quadrupel of mux registers and the correct reg inside */
486 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
487 reg = bank->iomux[iomux_num].offset;
488 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
496 spin_lock_irqsave(&bank->slock, flags);
498 data = (mask << (bit + 16));
499 rmask = data | (data >> 16);
500 data |= (mux & mask) << bit;
501 ret = regmap_update_bits(regmap, reg, rmask, data);
503 spin_unlock_irqrestore(&bank->slock, flags);
508 #define RK3188_PULL_BITS_PER_PIN 2
509 #define RK3188_PULL_PINS_PER_REG 8
510 #define RK3188_PULL_BANK_STRIDE 16
511 #define RK3188_PULL_PMU_OFFSET 0x64
513 #define RK3228_PULL_PMU_OFFSET 0x100
514 #define RK3228_PULL_OFFSET 0x110
516 #define RK3288_PULL_OFFSET 0x140
517 #define RK3368_PULL_PMU_OFFSET 0x10
518 #define RK3368_PULL_OFFSET 0x100
520 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
521 int pin_num, struct regmap **regmap,
524 struct rockchip_pinctrl *info = bank->drvdata;
525 struct rockchip_pin_ctrl *ctrl = info->ctrl;
527 /* The first 24 pins of the first bank are located in PMU */
528 if (bank->bank_num == 0) {
529 if (ctrl->type == RK3228) {
530 *regmap = info->regmap_base;
531 *reg = RK3228_PULL_PMU_OFFSET;
532 } else if (ctrl->type == RK3288) {
533 *regmap = info->regmap_pmu;
534 *reg = RK3188_PULL_PMU_OFFSET;
535 } else if (ctrl->type == RK3368) {
536 *regmap = info->regmap_pmu;
537 *reg = RK3368_PULL_PMU_OFFSET;
540 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
541 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
542 *bit *= RK3188_PULL_BITS_PER_PIN;
544 *regmap = info->regmap_base;
545 if (ctrl->type == RK3228)
546 *reg = RK3228_PULL_OFFSET;
547 else if (ctrl->type == RK3288)
548 *reg = RK3288_PULL_OFFSET;
549 else if (ctrl->type == RK3368)
550 *reg = RK3368_PULL_OFFSET;
552 /* correct the offset, as we're starting with the 2nd bank */
554 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
555 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
557 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
558 *bit *= RK3188_PULL_BITS_PER_PIN;
562 #define RK3228_DRV_PMU_OFFSET 0x200
563 #define RK3228_DRV_GRF_OFFSET 0x210
565 #define RK3288_DRV_PMU_OFFSET 0x70
566 #define RK3288_DRV_GRF_OFFSET 0x1c0
567 #define RK3288_DRV_BITS_PER_PIN 2
568 #define RK3288_DRV_PINS_PER_REG 8
569 #define RK3288_DRV_BANK_STRIDE 16
570 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
572 #define RK3368_DRV_PMU_OFFSET 0x20
573 #define RK3368_DRV_GRF_OFFSET 0x200
575 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
576 int pin_num, struct regmap **regmap,
579 struct rockchip_pinctrl *info = bank->drvdata;
580 struct rockchip_pin_ctrl *ctrl = info->ctrl;
582 /* The first 24 pins of the first bank are located in PMU */
583 if (bank->bank_num == 0) {
584 if (ctrl->type == RK3228) {
585 *regmap = info->regmap_base;
586 *reg = RK3228_DRV_PMU_OFFSET;
587 } else if (ctrl->type == RK3288) {
588 *regmap = info->regmap_pmu;
589 *reg = RK3288_DRV_PMU_OFFSET;
590 } else if (ctrl->type == RK3368) {
591 *regmap = info->regmap_pmu;
592 *reg = RK3368_DRV_PMU_OFFSET;
595 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
596 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
597 *bit *= RK3288_DRV_BITS_PER_PIN;
599 *regmap = info->regmap_base;
600 if (ctrl->type == RK3228)
601 *reg = RK3228_DRV_GRF_OFFSET;
602 else if (ctrl->type == RK3288)
603 *reg = RK3288_DRV_GRF_OFFSET;
604 else if (ctrl->type == RK3368)
605 *reg = RK3368_DRV_GRF_OFFSET;
607 /* correct the offset, as we're starting with the 2nd bank */
609 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
610 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
612 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
613 *bit *= RK3288_DRV_BITS_PER_PIN;
617 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
619 struct regmap *regmap;
624 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
626 ret = regmap_read(regmap, reg, &data);
631 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
633 return rk3288_drv_list[data];
636 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
639 struct rockchip_pinctrl *info = bank->drvdata;
640 struct regmap *regmap;
646 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
649 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
650 if (rk3288_drv_list[i] == strength) {
657 dev_err(info->dev, "unsupported driver strength %d\n",
662 spin_lock_irqsave(&bank->slock, flags);
664 /* enable the write to the equivalent lower bits */
665 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
666 rmask = data | (data >> 16);
667 data |= (ret << bit);
669 ret = regmap_update_bits(regmap, reg, rmask, data);
670 spin_unlock_irqrestore(&bank->slock, flags);
675 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
677 struct rockchip_pinctrl *info = bank->drvdata;
678 struct rockchip_pin_ctrl *ctrl = info->ctrl;
679 struct regmap *regmap;
684 /* rk3066b does support any pulls */
685 if (ctrl->type == RK3066B)
686 return PIN_CONFIG_BIAS_DISABLE;
688 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
690 ret = regmap_read(regmap, reg, &data);
694 switch (ctrl->type) {
696 return !(data & BIT(bit))
697 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
698 : PIN_CONFIG_BIAS_DISABLE;
704 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
708 return PIN_CONFIG_BIAS_DISABLE;
710 return PIN_CONFIG_BIAS_PULL_UP;
712 return PIN_CONFIG_BIAS_PULL_DOWN;
714 return PIN_CONFIG_BIAS_BUS_HOLD;
717 dev_err(info->dev, "unknown pull setting\n");
720 dev_err(info->dev, "unsupported pinctrl type\n");
725 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
726 int pin_num, int pull)
728 struct rockchip_pinctrl *info = bank->drvdata;
729 struct rockchip_pin_ctrl *ctrl = info->ctrl;
730 struct regmap *regmap;
736 pinctrl_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
737 bank->bank_num, pin_num, pull);
739 /* rk3066b does support any pulls */
740 if (ctrl->type == RK3066B)
741 return pull ? -EINVAL : 0;
743 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
745 switch (ctrl->type) {
747 spin_lock_irqsave(&bank->slock, flags);
749 data = BIT(bit + 16);
750 if (pull == PIN_CONFIG_BIAS_DISABLE)
752 ret = regmap_write(regmap, reg, data);
754 spin_unlock_irqrestore(&bank->slock, flags);
760 spin_lock_irqsave(&bank->slock, flags);
762 /* enable the write to the equivalent lower bits */
763 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
764 rmask = data | (data >> 16);
767 case PIN_CONFIG_BIAS_DISABLE:
769 case PIN_CONFIG_BIAS_PULL_UP:
772 case PIN_CONFIG_BIAS_PULL_DOWN:
775 case PIN_CONFIG_BIAS_BUS_HOLD:
779 spin_unlock_irqrestore(&bank->slock, flags);
780 dev_err(info->dev, "unsupported pull setting %d\n",
785 ret = regmap_update_bits(regmap, reg, rmask, data);
787 spin_unlock_irqrestore(&bank->slock, flags);
790 dev_err(info->dev, "unsupported pinctrl type\n");
798 * Pinmux_ops handling
801 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
803 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
805 return info->nfunctions;
808 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
811 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
813 return info->functions[selector].name;
816 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
818 const char * const **groups,
819 unsigned * const num_groups)
821 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
823 *groups = info->functions[selector].groups;
824 *num_groups = info->functions[selector].ngroups;
829 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
832 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
833 const unsigned int *pins = info->groups[group].pins;
834 const struct rockchip_pin_config *data = info->groups[group].data;
835 struct rockchip_pin_bank *bank;
838 pinctrl_dbg(info->dev, "enable function %s group %s\n",
839 info->functions[selector].name, info->groups[group].name);
842 * for each pin in the pin group selected, program the correspoding pin
843 * pin function number in the config register.
845 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
846 bank = pin_to_bank(info, pins[cnt]);
847 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
854 /* revert the already done pin settings */
855 for (cnt--; cnt >= 0; cnt--)
856 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
864 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
865 unsigned selector, unsigned group)
867 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
868 const unsigned int *pins = info->groups[group].pins;
869 struct rockchip_pin_bank *bank;
872 pinctrl_dbg(info->dev, "disable function %s group %s\n",
873 info->functions[selector].name, info->groups[group].name);
875 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
876 bank = pin_to_bank(info, pins[cnt]);
877 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
882 * The calls to gpio_direction_output() and gpio_direction_input()
883 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
884 * function called from the gpiolib interface).
886 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
887 struct pinctrl_gpio_range *range,
888 unsigned offset, bool input)
890 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
891 struct rockchip_pin_bank *bank;
892 struct gpio_chip *chip;
897 bank = gc_to_pin_bank(chip);
898 pin = offset - chip->base;
900 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
901 offset, range->name, pin, input ? "input" : "output");
903 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
907 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
908 /* set bit to 1 for output, 0 for input */
913 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
918 static const struct pinmux_ops rockchip_pmx_ops = {
919 .get_functions_count = rockchip_pmx_get_funcs_count,
920 .get_function_name = rockchip_pmx_get_func_name,
921 .get_function_groups = rockchip_pmx_get_groups,
922 .enable = rockchip_pmx_enable,
923 .disable = rockchip_pmx_disable,
924 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
928 * Pinconf_ops handling
931 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
932 enum pin_config_param pull)
934 switch (ctrl->type) {
936 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
937 pull == PIN_CONFIG_BIAS_DISABLE);
939 return pull ? false : true;
944 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
950 static int rockchip_gpio_direction_output(
951 struct gpio_chip *gc, unsigned offset, int value);
952 static int rockchip_gpio_direction_input(
953 struct gpio_chip *gc, unsigned offset);
954 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
956 /* set the pin config settings for a specified pin */
957 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
958 unsigned long configs)
960 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
961 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
962 enum pin_config_param param;
966 param = pinconf_to_config_param(configs);
967 arg = pinconf_to_config_argument(configs);
970 case PIN_CONFIG_BIAS_DISABLE:
971 rc = rockchip_set_pull(bank, pin - bank->pin_base,
976 case PIN_CONFIG_BIAS_PULL_UP:
977 case PIN_CONFIG_BIAS_PULL_DOWN:
978 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
979 case PIN_CONFIG_BIAS_BUS_HOLD:
980 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
986 rc = rockchip_set_pull(bank, pin - bank->pin_base,
991 case PIN_CONFIG_OUTPUT:
992 rc = rockchip_gpio_direction_output(
994 pin - bank->pin_base,
1000 case PIN_CONFIG_INPUT_ENABLE:
1002 rc = rockchip_gpio_direction_input(
1003 &bank->gpio_chip, pin - bank->pin_base);
1009 case PIN_CONFIG_DRIVE_STRENGTH:
1010 /* rk3228 rk3288 rk3368 is the first
1011 with per-pin drive-strength */
1012 if ((RK3228 != info->ctrl->type) &&
1013 (RK3288 != info->ctrl->type) &&
1014 (RK3368 != info->ctrl->type))
1017 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
1029 /* get the pin config settings for a specified pin */
1030 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1031 unsigned long *config)
1033 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1034 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1035 enum pin_config_param param = pinconf_to_config_param(*config);
1040 case PIN_CONFIG_BIAS_DISABLE:
1041 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1046 case PIN_CONFIG_BIAS_PULL_UP:
1047 case PIN_CONFIG_BIAS_PULL_DOWN:
1048 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1049 case PIN_CONFIG_BIAS_BUS_HOLD:
1050 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1053 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1058 case PIN_CONFIG_OUTPUT:
1059 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1060 if (rc != RK_FUNC_GPIO)
1063 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1069 case PIN_CONFIG_DRIVE_STRENGTH:
1070 /* rk3228 rk3288 RK3368 is the first with per-pin
1073 if ((RK3228 != info->ctrl->type) &&
1074 (RK3288 != info->ctrl->type) &&
1075 (RK3368 != info->ctrl->type))
1078 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1089 *config = pinconf_to_config_packed(param, arg);
1094 static const struct pinconf_ops rockchip_pinconf_ops = {
1095 .pin_config_get = rockchip_pinconf_get,
1096 .pin_config_set = rockchip_pinconf_set,
1100 static const struct of_device_id rockchip_bank_match[] = {
1101 { .compatible = "rockchip,gpio-bank" },
1102 { .compatible = "rockchip,rk3188-gpio-bank0" },
1106 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1107 struct device_node *np)
1109 struct device_node *child;
1111 for_each_child_of_node(np, child) {
1112 if (of_match_node(rockchip_bank_match, child))
1116 info->ngroups += of_get_child_count(child);
1120 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1121 struct rockchip_pin_group *grp,
1122 struct rockchip_pinctrl *info,
1125 struct rockchip_pin_bank *bank;
1132 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1134 /* Initialise group */
1135 grp->name = np->name;
1138 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1139 * do sanity check and calculate pins number
1141 list = of_get_property(np, "rockchip,pins", &size);
1142 /* we do not check return since it's safe node passed down */
1143 size /= sizeof(*list);
1144 if (!size || size % 4) {
1146 "wrong pins number or pins and configs should be by 4\n");
1150 grp->npins = size / 4;
1152 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1154 grp->data = devm_kzalloc(info->dev, grp->npins *
1155 sizeof(struct rockchip_pin_config),
1157 if (!grp->pins || !grp->data)
1160 for (i = 0, j = 0; i < size; i += 4, j++) {
1161 const __be32 *phandle;
1162 struct device_node *np_config;
1164 num = be32_to_cpu(*list++);
1165 bank = bank_num_to_bank(info, num);
1167 return PTR_ERR(bank);
1169 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1170 grp->data[j].func = be32_to_cpu(*list++);
1176 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1177 ret = pinconf_generic_parse_dt_config(np_config,
1178 &grp->data[j].configs,
1179 &grp->data[j].nconfigs);
1187 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1188 struct rockchip_pinctrl *info,
1191 struct device_node *child;
1192 struct rockchip_pmx_func *func;
1193 struct rockchip_pin_group *grp;
1195 static u32 grp_index;
1198 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1200 func = &info->functions[index];
1202 /* Initialise function */
1203 func->name = np->name;
1204 func->ngroups = of_get_child_count(np);
1205 if (func->ngroups <= 0)
1208 func->groups = devm_kzalloc(info->dev,
1209 func->ngroups * sizeof(char *), GFP_KERNEL);
1213 for_each_child_of_node(np, child) {
1214 func->groups[i] = child->name;
1215 grp = &info->groups[grp_index++];
1216 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1224 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1225 struct rockchip_pinctrl *info)
1227 struct device *dev = &pdev->dev;
1228 struct device_node *np = dev->of_node;
1229 struct device_node *child;
1233 rockchip_pinctrl_child_count(info, np);
1235 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1236 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1238 info->functions = devm_kzalloc(dev, info->nfunctions *
1239 sizeof(struct rockchip_pmx_func),
1241 if (!info->functions) {
1242 dev_err(dev, "failed to allocate memory for function list\n");
1246 info->groups = devm_kzalloc(dev, info->ngroups *
1247 sizeof(struct rockchip_pin_group),
1249 if (!info->groups) {
1250 dev_err(dev, "failed allocate memory for ping group list\n");
1256 for_each_child_of_node(np, child) {
1257 if (of_match_node(rockchip_bank_match, child))
1260 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1262 dev_err(&pdev->dev, "failed to parse function\n");
1270 static int rockchip_pinctrl_register(struct platform_device *pdev,
1271 struct rockchip_pinctrl *info)
1273 struct pinctrl_desc *ctrldesc = &info->pctl;
1274 struct pinctrl_pin_desc *pindesc, *pdesc;
1275 struct rockchip_pin_bank *pin_bank;
1279 ctrldesc->name = "rockchip-pinctrl";
1280 ctrldesc->owner = THIS_MODULE;
1281 ctrldesc->pctlops = &rockchip_pctrl_ops;
1282 ctrldesc->pmxops = &rockchip_pmx_ops;
1283 ctrldesc->confops = &rockchip_pinconf_ops;
1285 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1286 info->ctrl->nr_pins, GFP_KERNEL);
1288 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1291 ctrldesc->pins = pindesc;
1292 ctrldesc->npins = info->ctrl->nr_pins;
1295 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1296 pin_bank = &info->ctrl->pin_banks[bank];
1297 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1299 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1300 pin_bank->name, pin);
1305 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1306 if (!info->pctl_dev) {
1307 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1311 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1312 pin_bank = &info->ctrl->pin_banks[bank];
1313 pin_bank->grange.name = pin_bank->name;
1314 pin_bank->grange.id = bank;
1315 pin_bank->grange.pin_base = pin_bank->pin_base;
1316 pin_bank->grange.base = pin_bank->gpio_chip.base;
1317 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1318 pin_bank->grange.gc = &pin_bank->gpio_chip;
1319 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1322 ret = rockchip_pinctrl_parse_dt(pdev, info);
1324 pinctrl_unregister(info->pctl_dev);
1335 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1337 return pinctrl_request_gpio(chip->base + offset);
1340 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1342 pinctrl_free_gpio(chip->base + offset);
1345 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1347 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1348 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1349 unsigned long flags;
1352 spin_lock_irqsave(&bank->slock, flags);
1355 data &= ~BIT(offset);
1357 data |= BIT(offset);
1360 spin_unlock_irqrestore(&bank->slock, flags);
1364 * Returns the level of the pin for input direction and setting of the DR
1365 * register for output gpios.
1367 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1369 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1372 data = readl(bank->reg_base + GPIO_EXT_PORT);
1379 * gpiolib gpio_direction_input callback function. The setting of the pin
1380 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1383 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1385 return pinctrl_gpio_direction_input(gc->base + offset);
1389 * gpiolib gpio_direction_output callback function. The setting of the pin
1390 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1393 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1394 unsigned offset, int value)
1396 rockchip_gpio_set(gc, offset, value);
1397 return pinctrl_gpio_direction_output(gc->base + offset);
1401 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1402 * and a virtual IRQ, if not already present.
1404 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1406 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1412 virq = irq_create_mapping(bank->domain, offset);
1414 return (virq) ? : -ENXIO;
1417 static const struct gpio_chip rockchip_gpiolib_chip = {
1418 .request = rockchip_gpio_request,
1419 .free = rockchip_gpio_free,
1420 .set = rockchip_gpio_set,
1421 .get = rockchip_gpio_get,
1422 .direction_input = rockchip_gpio_direction_input,
1423 .direction_output = rockchip_gpio_direction_output,
1424 .to_irq = rockchip_gpio_to_irq,
1425 .owner = THIS_MODULE,
1429 * Interrupt handling
1432 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1434 struct irq_chip *chip = irq_get_chip(irq);
1435 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1436 u32 polarity = 0, data = 0;
1438 bool edge_changed = false;
1440 pinctrl_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1442 chained_irq_enter(chip, desc);
1444 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1446 if (bank->toggle_edge_mode) {
1447 polarity = readl_relaxed(bank->reg_base +
1449 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1457 virq = irq_linear_revmap(bank->domain, irq);
1460 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1464 pinctrl_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1467 * Triggering IRQ on both rising and falling edge
1468 * needs manual intervention.
1470 if (bank->toggle_edge_mode & BIT(irq)) {
1471 if (data & BIT(irq))
1472 polarity &= ~BIT(irq);
1474 polarity |= BIT(irq);
1476 edge_changed = true;
1479 generic_handle_irq(virq);
1482 if (bank->toggle_edge_mode && edge_changed) {
1483 /* Interrupt params should only be set with ints disabled */
1484 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1485 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1486 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1487 writel(data, bank->reg_base + GPIO_INTEN);
1490 chained_irq_exit(chip, desc);
1493 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1495 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1496 u32 mask = BIT(d->hwirq);
1501 unsigned long flags;
1503 /* make sure the pin is configured as gpio input */
1504 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1508 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1510 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1512 if (type & IRQ_TYPE_EDGE_BOTH)
1513 __irq_set_handler_locked(d->irq, handle_edge_irq);
1515 __irq_set_handler_locked(d->irq, handle_level_irq);
1517 spin_lock_irqsave(&bank->slock, flags);
1519 level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
1520 polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
1523 case IRQ_TYPE_EDGE_BOTH:
1524 bank->toggle_edge_mode |= mask;
1528 * Determine gpio state. If 1 next interrupt should be falling
1531 data = readl(bank->reg_base + GPIO_EXT_PORT);
1537 case IRQ_TYPE_EDGE_RISING:
1538 bank->toggle_edge_mode &= ~mask;
1542 case IRQ_TYPE_EDGE_FALLING:
1543 bank->toggle_edge_mode &= ~mask;
1547 case IRQ_TYPE_LEVEL_HIGH:
1548 bank->toggle_edge_mode &= ~mask;
1552 case IRQ_TYPE_LEVEL_LOW:
1553 bank->toggle_edge_mode &= ~mask;
1561 writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
1562 writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
1564 spin_unlock_irqrestore(&bank->slock, flags);
1569 static inline void rockchip_gpio_bit_op(void __iomem *reg_base
1570 , unsigned int offset, u32 bit, unsigned char flag)
1572 u32 val = __raw_readl(reg_base + offset);
1579 __raw_writel(val, reg_base + offset);
1582 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank,
1585 while (gpio >= (bank->pin_base + bank->nr_pins))
1588 return gpio - bank->pin_base;
1591 static inline unsigned offset_to_bit(unsigned offset)
1593 return 1u << offset;
1596 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
1598 rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
1601 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
1603 rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
1606 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
1608 rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
1611 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1613 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1615 unsigned long flags;
1617 spin_lock_irqsave(&bank->slock, flags);
1620 bank->suspend_wakeup |= BIT(bit);
1622 bank->suspend_wakeup &= ~BIT(bit);
1623 spin_unlock_irqrestore(&bank->slock, flags);
1628 static void rockchip_gpio_irq_unmask(struct irq_data *d)
1630 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1632 unsigned long flags;
1634 spin_lock_irqsave(&bank->slock, flags);
1635 GPIOEnableIntr(bank->reg_base, bit);
1636 spin_unlock_irqrestore(&bank->slock, flags);
1639 static void rockchip_gpio_irq_mask(struct irq_data *d)
1641 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1643 unsigned long flags;
1645 spin_lock_irqsave(&bank->slock, flags);
1646 GPIODisableIntr(bank->reg_base, bit);
1647 spin_unlock_irqrestore(&bank->slock, flags);
1650 static void rockchip_gpio_irq_ack(struct irq_data *d)
1652 struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1655 GPIOAckIntr(bank->reg_base, bit);
1658 static struct irq_chip rockchip_gpio_irq_chip = {
1659 .name = "ROCKCHIP_GPIO_CHIP",
1660 .irq_ack = rockchip_gpio_irq_ack,
1661 .irq_disable = rockchip_gpio_irq_mask,
1662 .irq_mask = rockchip_gpio_irq_mask,
1663 .irq_unmask = rockchip_gpio_irq_unmask,
1664 .irq_set_type = rockchip_gpio_irq_set_type,
1665 .irq_set_wake = rockchip_gpio_irq_set_wake,
1668 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1669 irq_hw_number_t hwirq)
1671 struct rockchip_pin_bank *bank = d->host_data;
1672 struct irq_data *irq_data = irq_get_irq_data(irq);
1675 dev_err(bank->drvdata->dev, "%s:bank=0x%p,irq=%d\n",
1676 __func__, bank, irq);
1680 irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip,
1682 irq_set_chip_data(irq, bank);
1683 set_irq_flags(irq, IRQF_VALID);
1685 irq_data->hwirq = hwirq;
1686 irq_data->irq = irq;
1688 pinctrl_dbg(bank->drvdata->dev, "%s:irq = %d, hwirq =%ld\n",
1689 __func__, irq, hwirq);
1693 static const struct irq_domain_ops rockchip_gpio_irq_ops = {
1694 .map = rockchip_gpio_irq_map,
1695 .xlate = irq_domain_xlate_twocell,
1698 static int rockchip_interrupts_register(struct platform_device *pdev,
1699 struct rockchip_pinctrl *info)
1701 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1702 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1705 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1707 dev_warn(&pdev->dev, "bank %s is not valid\n",
1712 __raw_writel(0, bank->reg_base + GPIO_INTEN);
1714 bank->drvdata = info;
1715 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1716 &rockchip_gpio_irq_ops, bank);
1717 if (!bank->domain) {
1718 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1723 irq_set_handler_data(bank->irq, bank);
1724 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1730 static int rockchip_gpiolib_register(struct platform_device *pdev,
1731 struct rockchip_pinctrl *info)
1733 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1734 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1735 struct gpio_chip *gc;
1739 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1741 dev_warn(&pdev->dev, "bank %s is not valid\n",
1746 bank->gpio_chip = rockchip_gpiolib_chip;
1748 gc = &bank->gpio_chip;
1749 gc->base = bank->pin_base;
1750 gc->ngpio = bank->nr_pins;
1751 gc->dev = &pdev->dev;
1752 gc->of_node = bank->of_node;
1753 gc->label = bank->name;
1755 ret = gpiochip_add(gc);
1757 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1763 rockchip_interrupts_register(pdev, info);
1768 for (--i, --bank; i >= 0; --i, --bank) {
1772 if (gpiochip_remove(&bank->gpio_chip))
1773 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1774 bank->gpio_chip.label);
1779 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1780 struct rockchip_pinctrl *info)
1782 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1783 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1787 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1791 ret = gpiochip_remove(&bank->gpio_chip);
1795 dev_err(&pdev->dev, "gpio chip remove failed\n");
1800 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1801 struct rockchip_pinctrl *info)
1803 struct resource res;
1806 if (of_address_to_resource(bank->of_node, 0, &res)) {
1807 dev_err(info->dev, "cannot find IO resource for bank\n");
1811 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1812 if (IS_ERR(bank->reg_base))
1813 return PTR_ERR(bank->reg_base);
1816 * special case, where parts of the pull setting-registers are
1817 * part of the PMU register space
1819 if (of_device_is_compatible(bank->of_node,
1820 "rockchip,rk3188-gpio-bank0")) {
1821 struct device_node *node;
1823 node = of_parse_phandle(bank->of_node->parent,
1824 "rockchip,pmugrf", 0);
1826 if (of_address_to_resource(bank->of_node, 1, &res)) {
1827 dev_err(info->dev, "cannot find IO resource for bank\n");
1831 base = devm_ioremap_resource(info->dev, &res);
1833 return PTR_ERR(base);
1834 rockchip_regmap_config.max_register =
1835 resource_size(&res) - 4;
1836 rockchip_regmap_config.name =
1837 "rockchip,rk3188-gpio-bank0-pull";
1838 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1840 &rockchip_regmap_config);
1844 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1846 bank->clk = of_clk_get(bank->of_node, 0);
1847 if (IS_ERR(bank->clk))
1848 return PTR_ERR(bank->clk);
1850 return clk_prepare_enable(bank->clk);
1853 static const struct of_device_id rockchip_pinctrl_dt_match[];
1855 /* retrieve the soc specific data */
1856 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1857 struct rockchip_pinctrl *d,
1858 struct platform_device *pdev)
1860 const struct of_device_id *match;
1861 struct device_node *node = pdev->dev.of_node;
1862 struct device_node *np;
1863 struct rockchip_pin_ctrl *ctrl;
1864 struct rockchip_pin_bank *bank;
1865 int grf_offs, pmu_offs, i, j;
1867 match = of_match_node(rockchip_pinctrl_dt_match, node);
1868 ctrl = (struct rockchip_pin_ctrl *)match->data;
1870 for_each_child_of_node(node, np) {
1871 if (!of_find_property(np, "gpio-controller", NULL))
1874 bank = ctrl->pin_banks;
1875 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1876 if (!strcmp(bank->name, np->name)) {
1879 if (!rockchip_get_bank_data(bank, d))
1887 grf_offs = ctrl->grf_mux_offset;
1888 pmu_offs = ctrl->pmu_mux_offset;
1889 bank = ctrl->pin_banks;
1890 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1893 spin_lock_init(&bank->slock);
1895 bank->pin_base = ctrl->nr_pins;
1896 ctrl->nr_pins += bank->nr_pins;
1898 /* calculate iomux offsets */
1899 for (j = 0; j < 4; j++) {
1900 struct rockchip_iomux *iom = &bank->iomux[j];
1903 if (bank_pins >= bank->nr_pins)
1906 /* preset offset value, set new start value */
1907 if (iom->offset >= 0) {
1908 if (iom->type & IOMUX_SOURCE_PMU)
1909 pmu_offs = iom->offset;
1911 grf_offs = iom->offset;
1912 } else { /* set current offset */
1913 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1914 pmu_offs : grf_offs;
1917 pinctrl_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1921 * Increase offset according to iomux width.
1922 * 4bit iomux'es are spread over two registers.
1924 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1925 if (iom->type & IOMUX_SOURCE_PMU)
1938 static int rockchip_pinctrl_suspend(void)
1940 struct rockchip_pinctrl *info = g_info;
1941 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1942 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1945 for (n = 0; n < ctrl->nr_banks; n++) {
1946 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
1947 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
1949 if (!bank->suspend_wakeup)
1950 clk_disable_unprepare(bank->clk);
1957 static void rockchip_pinctrl_resume(void)
1959 struct rockchip_pinctrl *info = g_info;
1960 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1961 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1965 for (n = 0; n < ctrl->nr_banks; n++) {
1966 if (!bank->suspend_wakeup)
1967 clk_prepare_enable(bank->clk);
1969 /* keep enable for resume irq */
1970 isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
1971 __raw_writel(bank->saved_wakeup
1972 | (bank->suspend_wakeup & isr)
1973 , bank->reg_base + GPIO_INTEN);
1978 static struct syscore_ops rockchip_gpio_syscore_ops = {
1979 .suspend = rockchip_pinctrl_suspend,
1980 .resume = rockchip_pinctrl_resume,
1984 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1986 struct rockchip_pinctrl *info;
1987 struct device *dev = &pdev->dev;
1988 struct rockchip_pin_ctrl *ctrl;
1989 struct device_node *np = pdev->dev.of_node, *node;
1990 struct resource *res;
1994 if (!dev->of_node) {
1995 dev_err(dev, "device tree node not found\n");
1999 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2005 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2007 dev_err(dev, "driver data not available\n");
2013 node = of_parse_phandle(np, "rockchip,grf", 0);
2015 info->regmap_base = syscon_node_to_regmap(node);
2016 if (IS_ERR(info->regmap_base))
2017 return PTR_ERR(info->regmap_base);
2019 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2020 base = devm_ioremap_resource(&pdev->dev, res);
2022 return PTR_ERR(base);
2024 rockchip_regmap_config.max_register = resource_size(res) - 4;
2025 rockchip_regmap_config.name = "rockchip,pinctrl";
2026 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2027 &rockchip_regmap_config);
2029 /* to check for the old dt-bindings */
2030 info->reg_size = resource_size(res);
2032 /* Honor the old binding, with pull registers as 2nd resource */
2033 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2034 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2035 base = devm_ioremap_resource(&pdev->dev, res);
2037 return PTR_ERR(base);
2039 rockchip_regmap_config.max_register =
2040 resource_size(res) - 4;
2041 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2042 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2044 &rockchip_regmap_config);
2048 /* try to find the optional reference to the pmu syscon */
2049 node = of_parse_phandle(np, "rockchip,pmugrf", 0);
2051 info->regmap_pmu = syscon_node_to_regmap(node);
2052 if (IS_ERR(info->regmap_pmu))
2053 return PTR_ERR(info->regmap_pmu);
2056 ret = rockchip_gpiolib_register(pdev, info);
2060 ret = rockchip_pinctrl_register(pdev, info);
2062 rockchip_gpiolib_unregister(pdev, info);
2066 platform_set_drvdata(pdev, info);
2068 register_syscore_ops(&rockchip_gpio_syscore_ops);
2074 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2075 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
2076 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2077 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2078 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2081 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2082 .pin_banks = rk3228_pin_banks,
2083 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2084 .label = "RK3228-GPIO",
2086 .grf_mux_offset = 0x0,
2087 .pmu_mux_offset = 0x0,
2088 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2090 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2091 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2095 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2096 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2097 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2100 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2101 .pin_banks = rk3368_pin_banks,
2102 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2103 .label = "RK3368-GPIO",
2105 .grf_mux_offset = 0x0,
2106 .pmu_mux_offset = 0x0,
2107 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2110 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2111 { .compatible = "rockchip,rk3228-pinctrl",
2112 .data = (void *)&rk3228_pin_ctrl },
2113 { .compatible = "rockchip,rk3368-pinctrl",
2114 .data = (void *)&rk3368_pin_ctrl },
2117 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2119 static struct platform_driver rockchip_pinctrl_driver = {
2120 .probe = rockchip_pinctrl_probe,
2122 .name = "rk3368-pinctrl",
2123 .owner = THIS_MODULE,
2124 .of_match_table = rockchip_pinctrl_dt_match,
2128 static int __init rockchip_pinctrl_drv_register(void)
2130 return platform_driver_register(&rockchip_pinctrl_driver);
2132 postcore_initcall(rockchip_pinctrl_drv_register);
2134 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2135 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2136 MODULE_LICENSE("GPL v2");