drivers/pinctrl/pinctrl-rk.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/bitops.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/pinctrl/machine.h>
  35 #include <linux/pinctrl/pinconf.h>
  36 #include <linux/pinctrl/pinctrl.h>
  37 #include <linux/pinctrl/pinmux.h>
  38 #include <linux/pinctrl/pinconf-generic.h>
  39 #include <linux/irqchip/chained_irq.h>
  40 #include <linux/clk.h>
  41 #include <linux/regmap.h>
  42 #include <linux/mfd/syscon.h>
  43 #include <linux/syscore_ops.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45
  46 #include "core.h"
  47 #include "pinconf.h"
  48
  49
  50 #if 0
  51 #define pinctrl_dbg(dev, format, arg...)            \
  52         dev_printk(KERN_INFO , dev , format , ## arg)
  53 #else
  54         #define pinctrl_dbg(dev, format, arg...)
  55 #endif
  56
  57
  58 /* GPIO control registers */
  59 #define GPIO_SWPORT_DR          0x00
  60 #define GPIO_SWPORT_DDR         0x04
  61 #define GPIO_INTEN              0x30
  62 #define GPIO_INTMASK            0x34
  63 #define GPIO_INTTYPE_LEVEL      0x38
  64 #define GPIO_INT_POLARITY       0x3c
  65 #define GPIO_INT_STATUS         0x40
  66 #define GPIO_INT_RAWSTATUS      0x44
  67 #define GPIO_DEBOUNCE           0x48
  68 #define GPIO_PORTS_EOI          0x4c
  69 #define GPIO_EXT_PORT           0x50
  70 #define GPIO_LS_SYNC            0x60
  71
  72 enum rockchip_pinctrl_type {
  73         RK2928,
  74         RK3066B,
  75         RK3188,
  76         RK3228,
  77         RK3288,
  78         RK3368,
  79 };
  80
  81 /**
  82  * Encode variants of iomux registers into a type variable
  83  */
  84 #define IOMUX_GPIO_ONLY         BIT(0)
  85 #define IOMUX_WIDTH_4BIT        BIT(1)
  86 #define IOMUX_SOURCE_PMU        BIT(2)
  87 #define IOMUX_UNROUTED          BIT(3)
  88
  89 /**
  90  * @type: iomux variant using IOMUX_* constants
  91  * @offset: if initialized to -1 it will be autocalculated, by specifying
  92  *          an initial offset value the relevant source offset can be reset
  93  *          to a new value for autocalculating the following iomux registers.
  94  */
  95 struct rockchip_iomux {
  96         int                             type;
  97         int                             offset;
  98 };
  99
 100 /**
 101  * @reg_base: register base of the gpio bank
 102  * @reg_pull: optional separate register for additional pull settings
 103  * @clk: clock of the gpio bank
 104  * @irq: interrupt of the gpio bank
 105  * @pin_base: first pin number
 106  * @nr_pins: number of pins in this bank
 107  * @name: name of the bank
 108  * @bank_num: number of the bank, to account for holes
 109  * @iomux: array describing the 4 iomux sources of the bank
 110  * @valid: are all necessary informations present
 111  * @of_node: dt node of this bank
 112  * @drvdata: common pinctrl basedata
 113  * @domain: irqdomain of the gpio bank
 114  * @gpio_chip: gpiolib chip
 115  * @grange: gpio range
 116  * @slock: spinlock for the gpio bank
 117  */
 118 struct rockchip_pin_bank {
 119         void __iomem                    *reg_base;
 120         struct regmap                   *regmap_pull;
 121         struct clk                      *clk;
 122         int                             irq;
 123         u32                             pin_base;
 124         u8                              nr_pins;
 125         char                            *name;
 126         u8                              bank_num;
 127         struct rockchip_iomux           iomux[4];
 128         bool                            valid;
 129         struct device_node              *of_node;
 130         struct rockchip_pinctrl         *drvdata;
 131         struct irq_domain               *domain;
 132         struct gpio_chip                gpio_chip;
 133         struct pinctrl_gpio_range       grange;
 134         /*spinlock for the gpio bank*/
 135         spinlock_t                      slock;
 136         u32                             toggle_edge_mode;
 137         u32                             suspend_wakeup;
 138         u32                             saved_wakeup;
 139 };
 140
 141 #define PIN_BANK(id, pins, label)                       \
 142         {                                               \
 143                 .bank_num       = id,                   \
 144                 .nr_pins        = pins,                 \
 145                 .name           = label,                \
 146                 .iomux          = {                     \
 147                         { .offset = -1 },               \
 148                         { .offset = -1 },               \
 149                         { .offset = -1 },               \
 150                         { .offset = -1 },               \
 151                 },                                      \
 152         }
 153
 154 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 155         {                                                               \
 156                 .bank_num       = id,                                   \
 157                 .nr_pins        = pins,                                 \
 158                 .name           = label,                                \
 159                 .iomux          = {                                     \
 160                         { .type = iom0, .offset = -1 },                 \
 161                         { .type = iom1, .offset = -1 },                 \
 162                         { .type = iom2, .offset = -1 },                 \
 163                         { .type = iom3, .offset = -1 },                 \
 164                 },                                                      \
 165         }
 166
 167 /**
 168  */
 169 struct rockchip_pin_ctrl {
 170         struct rockchip_pin_bank        *pin_banks;
 171         u32                             nr_banks;
 172         u32                             nr_pins;
 173         char                            *label;
 174         enum rockchip_pinctrl_type      type;
 175         int                             grf_mux_offset;
 176         int                             pmu_mux_offset;
 177
 178         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 179                                  int pin_num, struct regmap **regmap,
 180                                  int *reg, u8 *bit);
 181 };
 182
 183 struct rockchip_pin_config {
 184         unsigned int            func;
 185         unsigned long           *configs;
 186         unsigned int            nconfigs;
 187 };
 188
 189 /**
 190  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 191  * @name: name of the pin group, used to lookup the group.
 192  * @pins: the pins included in this group.
 193  * @npins: number of pins included in this group.
 194  * @func: the mux function number to be programmed when selected.
 195  * @configs: the config values to be set for each pin
 196  * @nconfigs: number of configs for each pin
 197  */
 198 struct rockchip_pin_group {
 199         const char                      *name;
 200         unsigned int                    npins;
 201         unsigned int                    *pins;
 202         struct rockchip_pin_config      *data;
 203 };
 204
 205 /**
 206  * struct rockchip_pmx_func: represent a pin function.
 207  * @name: name of the pin function, used to lookup the function.
 208  * @groups: one or more names of pin groups that provide this function.
 209  * @num_groups: number of groups included in @groups.
 210  */
 211 struct rockchip_pmx_func {
 212         const char              *name;
 213         const char              **groups;
 214         u8                      ngroups;
 215 };
 216
 217 struct rockchip_pinctrl {
 218         struct regmap                   *regmap_base;
 219         int                             reg_size;
 220         struct regmap                   *regmap_pull;
 221         struct regmap                   *regmap_pmu;
 222         struct device                   *dev;
 223         struct rockchip_pin_ctrl        *ctrl;
 224         struct pinctrl_desc             pctl;
 225         struct pinctrl_dev              *pctl_dev;
 226         struct rockchip_pin_group       *groups;
 227         unsigned int                    ngroups;
 228         struct rockchip_pmx_func        *functions;
 229         unsigned int                    nfunctions;
 230 };
 231
 232 static struct regmap_config rockchip_regmap_config = {
 233         .reg_bits = 32,
 234         .val_bits = 32,
 235         .reg_stride = 4,
 236 };
 237 static struct rockchip_pinctrl *g_info;
 238
 239 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 240 {
 241         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 242 }
 243
 244 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 245                                         const struct rockchip_pinctrl *info,
 246                                         const char *name)
 247 {
 248         int i;
 249
 250         for (i = 0; i < info->ngroups; i++) {
 251                 if (!strcmp(info->groups[i].name, name))
 252                         return &info->groups[i];
 253         }
 254
 255         return NULL;
 256 }
 257
 258 /*
 259  * given a pin number that is local to a pin controller, find out the pin bank
 260  * and the register base of the pin bank.
 261  */
 262 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 263                                              unsigned pin)
 264 {
 265         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 266
 267         while (pin >= (b->pin_base + b->nr_pins))
 268                 b++;
 269
 270         return b;
 271 }
 272
 273 static struct rockchip_pin_bank *bank_num_to_bank(
 274                                         struct rockchip_pinctrl *info,
 275                                         unsigned num)
 276 {
 277         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 278         int i;
 279
 280         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 281                 if (b->bank_num == num)
 282                         return b;
 283         }
 284
 285         return ERR_PTR(-EINVAL);
 286 }
 287
 288 /*
 289  * Pinctrl_ops handling
 290  */
 291
 292 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 293 {
 294         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 295
 296         return info->ngroups;
 297 }
 298
 299 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 300                                            unsigned selector)
 301 {
 302         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 303
 304         return info->groups[selector].name;
 305 }
 306
 307 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 308                                    unsigned selector, const unsigned **pins,
 309                                    unsigned *npins)
 310 {
 311         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 312
 313         if (selector >= info->ngroups)
 314                 return -EINVAL;
 315
 316         *pins = info->groups[selector].pins;
 317         *npins = info->groups[selector].npins;
 318
 319         return 0;
 320 }
 321
 322 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 323                                    struct device_node *np,
 324                                    struct pinctrl_map **map, unsigned *num_maps)
 325 {
 326         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 327         const struct rockchip_pin_group *grp;
 328         struct pinctrl_map *new_map;
 329         struct device_node *parent;
 330         int map_num = 1;
 331         int i;
 332
 333         /*
 334          * first find the group of this node and check if we need to create
 335          * config maps for pins
 336          */
 337         grp = pinctrl_name_to_group(info, np->name);
 338         if (!grp) {
 339                 dev_err(info->dev, "unable to find group for node %s\n",
 340                         np->name);
 341                 return -EINVAL;
 342         }
 343
 344         map_num += grp->npins;
 345         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 346                                GFP_KERNEL);
 347         if (!new_map)
 348                 return -ENOMEM;
 349
 350         *map = new_map;
 351         *num_maps = map_num;
 352
 353         /* create mux map */
 354         parent = of_get_parent(np);
 355         if (!parent) {
 356                 devm_kfree(pctldev->dev, new_map);
 357                 return -EINVAL;
 358         }
 359         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 360         new_map[0].data.mux.function = parent->name;
 361         new_map[0].data.mux.group = np->name;
 362         of_node_put(parent);
 363
 364         /* create config map */
 365         new_map++;
 366         for (i = 0; i < grp->npins; i++) {
 367                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 368                 new_map[i].data.configs.group_or_pin =
 369                                 pin_get_name(pctldev, grp->pins[i]);
 370                 new_map[i].data.configs.configs = grp->data[i].configs;
 371                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 372         }
 373
 374         pinctrl_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 375                     (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 376
 377         return 0;
 378 }
 379
 380 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 381                                  struct pinctrl_map *map, unsigned num_maps)
 382 {
 383 }
 384
 385 static const struct pinctrl_ops rockchip_pctrl_ops = {
 386         .get_groups_count       = rockchip_get_groups_count,
 387         .get_group_name         = rockchip_get_group_name,
 388         .get_group_pins         = rockchip_get_group_pins,
 389         .dt_node_to_map         = rockchip_dt_node_to_map,
 390         .dt_free_map            = rockchip_dt_free_map,
 391 };
 392
 393 /*
 394  * Hardware access
 395  */
 396
 397 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 398 {
 399         struct rockchip_pinctrl *info = bank->drvdata;
 400         int iomux_num = (pin / 8);
 401         struct regmap *regmap;
 402         unsigned int val;
 403         int reg, ret, mask;
 404         u8 bit;
 405
 406         if (iomux_num > 3)
 407                 return -EINVAL;
 408
 409         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 410                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 411                 return -EINVAL;
 412         }
 413
 414         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 415                 return RK_FUNC_GPIO;
 416
 417         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 418                                 ? info->regmap_pmu : info->regmap_base;
 419
 420         /* get basic quadrupel of mux registers and the correct reg inside */
 421         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 422         reg = bank->iomux[iomux_num].offset;
 423         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 424                 if ((pin % 8) >= 4)
 425                         reg += 0x4;
 426                 bit = (pin % 4) * 4;
 427         } else {
 428                 bit = (pin % 8) * 2;
 429         }
 430
 431         ret = regmap_read(regmap, reg, &val);
 432         if (ret)
 433                 return ret;
 434
 435         return ((val >> bit) & mask);
 436 }
 437
 438 /*
 439  * Set a new mux function for a pin.
 440  *
 441  * The register is divided into the upper and lower 16 bit. When changing
 442  * a value, the previous register value is not read and changed. Instead
 443  * it seems the changed bits are marked in the upper 16 bit, while the
 444  * changed value gets set in the same offset in the lower 16 bit.
 445  * All pin settings seem to be 2 bit wide in both the upper and lower
 446  * parts.
 447  * @bank: pin bank to change
 448  * @pin: pin to change
 449  * @mux: new mux function to set
 450  */
 451 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 452 {
 453         struct rockchip_pinctrl *info = bank->drvdata;
 454         int iomux_num = (pin / 8);
 455         struct regmap *regmap;
 456         int reg, ret, mask;
 457         unsigned long flags;
 458         u8 bit;
 459         u32 data, rmask;
 460
 461         if (iomux_num > 3)
 462                 return -EINVAL;
 463
 464         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 465                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 466                 return -EINVAL;
 467         }
 468
 469         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 470                 if (mux != RK_FUNC_GPIO) {
 471                         dev_err(info->dev,
 472                                 "pin %d only supports a gpio mux\n", pin);
 473                         return -ENOTSUPP;
 474                 } else {
 475                         return 0;
 476                 }
 477         }
 478
 479         pinctrl_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 480                     bank->bank_num, pin, mux);
 481
 482         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 483                                 ? info->regmap_pmu : info->regmap_base;
 484
 485         /* get basic quadrupel of mux registers and the correct reg inside */
 486         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 487         reg = bank->iomux[iomux_num].offset;
 488         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 489                 if ((pin % 8) >= 4)
 490                         reg += 0x4;
 491                 bit = (pin % 4) * 4;
 492         } else {
 493                 bit = (pin % 8) * 2;
 494         }
 495
 496         spin_lock_irqsave(&bank->slock, flags);
 497
 498         data = (mask << (bit + 16));
 499         rmask = data | (data >> 16);
 500         data |= (mux & mask) << bit;
 501         ret = regmap_update_bits(regmap, reg, rmask, data);
 502
 503         spin_unlock_irqrestore(&bank->slock, flags);
 504
 505         return ret;
 506 }
 507
 508 #define RK3188_PULL_BITS_PER_PIN        2
 509 #define RK3188_PULL_PINS_PER_REG        8
 510 #define RK3188_PULL_BANK_STRIDE         16
 511 #define RK3188_PULL_PMU_OFFSET          0x64
 512
 513 #define RK3228_PULL_PMU_OFFSET          0x100
 514 #define RK3228_PULL_OFFSET              0x110
 515
 516 #define RK3288_PULL_OFFSET              0x140
 517 #define RK3368_PULL_PMU_OFFSET          0x10
 518 #define RK3368_PULL_OFFSET              0x100
 519
 520 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 521                                          int pin_num, struct regmap **regmap,
 522                                          int *reg, u8 *bit)
 523 {
 524         struct rockchip_pinctrl *info = bank->drvdata;
 525         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 526
 527         /* The first 24 pins of the first bank are located in PMU */
 528         if (bank->bank_num == 0) {
 529                 if (ctrl->type == RK3228) {
 530                         *regmap = info->regmap_base;
 531                         *reg = RK3228_PULL_PMU_OFFSET;
 532                 } else if (ctrl->type == RK3288) {
 533                         *regmap = info->regmap_pmu;
 534                         *reg = RK3188_PULL_PMU_OFFSET;
 535                 } else if (ctrl->type == RK3368) {
 536                         *regmap = info->regmap_pmu;
 537                         *reg = RK3368_PULL_PMU_OFFSET;
 538                 }
 539
 540                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 541                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 542                 *bit *= RK3188_PULL_BITS_PER_PIN;
 543         } else {
 544                 *regmap = info->regmap_base;
 545                 if (ctrl->type == RK3228)
 546                         *reg = RK3228_PULL_OFFSET;
 547                 else if (ctrl->type == RK3288)
 548                         *reg = RK3288_PULL_OFFSET;
 549                 else if (ctrl->type == RK3368)
 550                         *reg = RK3368_PULL_OFFSET;
 551
 552                 /* correct the offset, as we're starting with the 2nd bank */
 553                 *reg -= 0x10;
 554                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 555                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 556
 557                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 558                 *bit *= RK3188_PULL_BITS_PER_PIN;
 559         }
 560 }
 561
 562 #define RK3228_DRV_PMU_OFFSET           0x200
 563 #define RK3228_DRV_GRF_OFFSET           0x210
 564
 565 #define RK3288_DRV_PMU_OFFSET           0x70
 566 #define RK3288_DRV_GRF_OFFSET           0x1c0
 567 #define RK3288_DRV_BITS_PER_PIN         2
 568 #define RK3288_DRV_PINS_PER_REG         8
 569 #define RK3288_DRV_BANK_STRIDE          16
 570 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
 571
 572 #define RK3368_DRV_PMU_OFFSET           0x20
 573 #define RK3368_DRV_GRF_OFFSET           0x200
 574
 575 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 576                                         int pin_num, struct regmap **regmap,
 577                                         int *reg, u8 *bit)
 578 {
 579         struct rockchip_pinctrl *info = bank->drvdata;
 580         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 581
 582         /* The first 24 pins of the first bank are located in PMU */
 583         if (bank->bank_num == 0) {
 584                 if (ctrl->type == RK3228) {
 585                         *regmap = info->regmap_base;
 586                         *reg = RK3228_DRV_PMU_OFFSET;
 587                 } else if (ctrl->type == RK3288) {
 588                         *regmap = info->regmap_pmu;
 589                         *reg = RK3288_DRV_PMU_OFFSET;
 590                 } else if (ctrl->type == RK3368) {
 591                         *regmap = info->regmap_pmu;
 592                         *reg = RK3368_DRV_PMU_OFFSET;
 593                 }
 594
 595                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 596                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 597                 *bit *= RK3288_DRV_BITS_PER_PIN;
 598         } else {
 599                 *regmap = info->regmap_base;
 600                 if (ctrl->type == RK3228)
 601                         *reg = RK3228_DRV_GRF_OFFSET;
 602                 else if (ctrl->type == RK3288)
 603                         *reg = RK3288_DRV_GRF_OFFSET;
 604                 else if (ctrl->type == RK3368)
 605                         *reg = RK3368_DRV_GRF_OFFSET;
 606
 607                 /* correct the offset, as we're starting with the 2nd bank */
 608                 *reg -= 0x10;
 609                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 610                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 611
 612                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 613                 *bit *= RK3288_DRV_BITS_PER_PIN;
 614         }
 615 }
 616
 617 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
 618 {
 619         struct regmap *regmap;
 620         int reg, ret;
 621         u32 data;
 622         u8 bit;
 623
 624         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 625
 626         ret = regmap_read(regmap, reg, &data);
 627         if (ret)
 628                 return ret;
 629
 630         data >>= bit;
 631         data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 632
 633         return rk3288_drv_list[data];
 634 }
 635
 636 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
 637                             int strength)
 638 {
 639         struct rockchip_pinctrl *info = bank->drvdata;
 640         struct regmap *regmap;
 641         unsigned long flags;
 642         int reg, ret, i;
 643         u32 data, rmask;
 644         u8 bit;
 645
 646         rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 647
 648         ret = -EINVAL;
 649         for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
 650                 if (rk3288_drv_list[i] == strength) {
 651                         ret = i;
 652                         break;
 653                 }
 654         }
 655
 656         if (ret < 0) {
 657                 dev_err(info->dev, "unsupported driver strength %d\n",
 658                         strength);
 659                 return ret;
 660         }
 661
 662         spin_lock_irqsave(&bank->slock, flags);
 663
 664         /* enable the write to the equivalent lower bits */
 665         data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 666         rmask = data | (data >> 16);
 667         data |= (ret << bit);
 668
 669         ret = regmap_update_bits(regmap, reg, rmask, data);
 670         spin_unlock_irqrestore(&bank->slock, flags);
 671
 672         return ret;
 673 }
 674
 675 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 676 {
 677         struct rockchip_pinctrl *info = bank->drvdata;
 678         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 679         struct regmap *regmap;
 680         int reg, ret;
 681         u8 bit;
 682         u32 data;
 683
 684         /* rk3066b does support any pulls */
 685         if (ctrl->type == RK3066B)
 686                 return PIN_CONFIG_BIAS_DISABLE;
 687
 688         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 689
 690         ret = regmap_read(regmap, reg, &data);
 691         if (ret)
 692                 return ret;
 693
 694         switch (ctrl->type) {
 695         case RK2928:
 696                 return !(data & BIT(bit))
 697                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 698                                 : PIN_CONFIG_BIAS_DISABLE;
 699         case RK3188:
 700         case RK3228:
 701         case RK3288:
 702         case RK3368:
 703                 data >>= bit;
 704                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 705
 706                 switch (data) {
 707                 case 0:
 708                         return PIN_CONFIG_BIAS_DISABLE;
 709                 case 1:
 710                         return PIN_CONFIG_BIAS_PULL_UP;
 711                 case 2:
 712                         return PIN_CONFIG_BIAS_PULL_DOWN;
 713                 case 3:
 714                         return PIN_CONFIG_BIAS_BUS_HOLD;
 715                 }
 716
 717                 dev_err(info->dev, "unknown pull setting\n");
 718                 return -EIO;
 719         default:
 720                 dev_err(info->dev, "unsupported pinctrl type\n");
 721                 return -EINVAL;
 722         };
 723 }
 724
 725 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 726                              int pin_num, int pull)
 727 {
 728         struct rockchip_pinctrl *info = bank->drvdata;
 729         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 730         struct regmap *regmap;
 731         int reg, ret;
 732         unsigned long flags;
 733         u8 bit;
 734         u32 data, rmask;
 735
 736         pinctrl_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 737                     bank->bank_num, pin_num, pull);
 738
 739         /* rk3066b does support any pulls */
 740         if (ctrl->type == RK3066B)
 741                 return pull ? -EINVAL : 0;
 742
 743         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 744
 745         switch (ctrl->type) {
 746         case RK2928:
 747                 spin_lock_irqsave(&bank->slock, flags);
 748
 749                 data = BIT(bit + 16);
 750                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 751                         data |= BIT(bit);
 752                 ret = regmap_write(regmap, reg, data);
 753
 754                 spin_unlock_irqrestore(&bank->slock, flags);
 755                 break;
 756         case RK3188:
 757         case RK3228:
 758         case RK3288:
 759         case RK3368:
 760                 spin_lock_irqsave(&bank->slock, flags);
 761
 762                 /* enable the write to the equivalent lower bits */
 763                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 764                 rmask = data | (data >> 16);
 765
 766                 switch (pull) {
 767                 case PIN_CONFIG_BIAS_DISABLE:
 768                         break;
 769                 case PIN_CONFIG_BIAS_PULL_UP:
 770                         data |= (1 << bit);
 771                         break;
 772                 case PIN_CONFIG_BIAS_PULL_DOWN:
 773                         data |= (2 << bit);
 774                         break;
 775                 case PIN_CONFIG_BIAS_BUS_HOLD:
 776                         data |= (3 << bit);
 777                         break;
 778                 default:
 779                         spin_unlock_irqrestore(&bank->slock, flags);
 780                         dev_err(info->dev, "unsupported pull setting %d\n",
 781                                 pull);
 782                         return -EINVAL;
 783                 }
 784
 785                 ret = regmap_update_bits(regmap, reg, rmask, data);
 786
 787                 spin_unlock_irqrestore(&bank->slock, flags);
 788                 break;
 789         default:
 790                 dev_err(info->dev, "unsupported pinctrl type\n");
 791                 return -EINVAL;
 792         }
 793
 794         return ret;
 795 }
 796
 797 /*
 798  * Pinmux_ops handling
 799  */
 800
 801 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 802 {
 803         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 804
 805         return info->nfunctions;
 806 }
 807
 808 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 809                                               unsigned selector)
 810 {
 811         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 812
 813         return info->functions[selector].name;
 814 }
 815
 816 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 817                                    unsigned selector,
 818                                    const char * const **groups,
 819                                    unsigned * const num_groups)
 820 {
 821         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 822
 823         *groups = info->functions[selector].groups;
 824         *num_groups = info->functions[selector].ngroups;
 825
 826         return 0;
 827 }
 828
 829 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 830                                unsigned group)
 831 {
 832         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 833         const unsigned int *pins = info->groups[group].pins;
 834         const struct rockchip_pin_config *data = info->groups[group].data;
 835         struct rockchip_pin_bank *bank;
 836         int cnt, ret = 0;
 837
 838         pinctrl_dbg(info->dev, "enable function %s group %s\n",
 839                     info->functions[selector].name, info->groups[group].name);
 840
 841         /*
 842          * for each pin in the pin group selected, program the correspoding pin
 843          * pin function number in the config register.
 844          */
 845         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 846                 bank = pin_to_bank(info, pins[cnt]);
 847                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 848                                        data[cnt].func);
 849                 if (ret)
 850                         break;
 851         }
 852
 853         if (ret) {
 854                 /* revert the already done pin settings */
 855                 for (cnt--; cnt >= 0; cnt--)
 856                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 857
 858                 return ret;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 865                                  unsigned selector, unsigned group)
 866 {
 867         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 868         const unsigned int *pins = info->groups[group].pins;
 869         struct rockchip_pin_bank *bank;
 870         int cnt;
 871
 872         pinctrl_dbg(info->dev, "disable function %s group %s\n",
 873                     info->functions[selector].name, info->groups[group].name);
 874
 875         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 876                 bank = pin_to_bank(info, pins[cnt]);
 877                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 878         }
 879 }
 880
 881 /*
 882  * The calls to gpio_direction_output() and gpio_direction_input()
 883  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 884  * function called from the gpiolib interface).
 885  */
 886 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 887                                            struct pinctrl_gpio_range *range,
 888                                            unsigned offset, bool input)
 889 {
 890         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 891         struct rockchip_pin_bank *bank;
 892         struct gpio_chip *chip;
 893         int pin, ret;
 894         u32 data;
 895
 896         chip = range->gc;
 897         bank = gc_to_pin_bank(chip);
 898         pin = offset - chip->base;
 899
 900         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 901                 offset, range->name, pin, input ? "input" : "output");
 902
 903         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 904         if (ret < 0)
 905                 return ret;
 906
 907         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 908         /* set bit to 1 for output, 0 for input */
 909         if (!input)
 910                 data |= BIT(pin);
 911         else
 912                 data &= ~BIT(pin);
 913         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 914
 915         return 0;
 916 }
 917
 918 static const struct pinmux_ops rockchip_pmx_ops = {
 919         .get_functions_count    = rockchip_pmx_get_funcs_count,
 920         .get_function_name      = rockchip_pmx_get_func_name,
 921         .get_function_groups    = rockchip_pmx_get_groups,
 922         .enable                 = rockchip_pmx_enable,
 923         .disable                = rockchip_pmx_disable,
 924         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 925 };
 926
 927 /*
 928  * Pinconf_ops handling
 929  */
 930
 931 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 932                                         enum pin_config_param pull)
 933 {
 934         switch (ctrl->type) {
 935         case RK2928:
 936                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 937                         pull == PIN_CONFIG_BIAS_DISABLE);
 938         case RK3066B:
 939                 return pull ? false : true;
 940         case RK3188:
 941         case RK3228:
 942         case RK3288:
 943         case RK3368:
 944                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 945         }
 946
 947         return false;
 948 }
 949
 950 static int rockchip_gpio_direction_output(
 951         struct gpio_chip *gc, unsigned offset, int value);
 952 static int rockchip_gpio_direction_input(
 953         struct gpio_chip *gc, unsigned offset);
 954 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 955
 956 /* set the pin config settings for a specified pin */
 957 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 958                                 unsigned long configs)
 959 {
 960         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 961         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 962         enum pin_config_param param;
 963         u16 arg;
 964         int rc;
 965
 966                 param = pinconf_to_config_param(configs);
 967                 arg = pinconf_to_config_argument(configs);
 968
 969                 switch (param) {
 970                 case PIN_CONFIG_BIAS_DISABLE:
 971                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 972                                                 param);
 973                         if (rc)
 974                                 return rc;
 975                         break;
 976                 case PIN_CONFIG_BIAS_PULL_UP:
 977                 case PIN_CONFIG_BIAS_PULL_DOWN:
 978                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 979                 case PIN_CONFIG_BIAS_BUS_HOLD:
 980                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 981                                 return -ENOTSUPP;
 982
 983                         if (!arg)
 984                                 return -EINVAL;
 985
 986                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 987                                                param);
 988                         if (rc)
 989                                 return rc;
 990                         break;
 991                 case PIN_CONFIG_OUTPUT:
 992                         rc = rockchip_gpio_direction_output(
 993                                 &bank->gpio_chip,
 994                                 pin - bank->pin_base,
 995                                 arg);
 996                         if (rc)
 997                                 return rc;
 998                         break;
 999
1000                 case PIN_CONFIG_INPUT_ENABLE:
1001                         if (arg == 1) {
1002                                 rc = rockchip_gpio_direction_input(
1003                                         &bank->gpio_chip, pin - bank->pin_base);
1004                                 if (rc)
1005                                         return rc;
1006                         }
1007                         break;
1008
1009                 case PIN_CONFIG_DRIVE_STRENGTH:
1010                         /* rk3228 rk3288 rk3368 is the first
1011                                 with per-pin drive-strength */
1012                         if ((RK3228 != info->ctrl->type) &&
1013                             (RK3288 != info->ctrl->type) &&
1014                             (RK3368 != info->ctrl->type))
1015                                 return -ENOTSUPP;
1016
1017                         rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
1018                         if (rc < 0)
1019                                 return rc;
1020                         break;
1021                 default:
1022                         return -ENOTSUPP;
1023                         break;
1024                 }
1025
1026         return 0;
1027 }
1028
1029 /* get the pin config settings for a specified pin */
1030 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1031                                 unsigned long *config)
1032 {
1033         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1034         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1035         enum pin_config_param param = pinconf_to_config_param(*config);
1036         u16 arg;
1037         int rc;
1038
1039         switch (param) {
1040         case PIN_CONFIG_BIAS_DISABLE:
1041                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1042                         return -EINVAL;
1043
1044                 arg = 0;
1045                 break;
1046         case PIN_CONFIG_BIAS_PULL_UP:
1047         case PIN_CONFIG_BIAS_PULL_DOWN:
1048         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1049         case PIN_CONFIG_BIAS_BUS_HOLD:
1050                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1051                         return -ENOTSUPP;
1052
1053                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1054                         return -EINVAL;
1055
1056                 arg = 1;
1057                 break;
1058         case PIN_CONFIG_OUTPUT:
1059                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1060                 if (rc != RK_FUNC_GPIO)
1061                         return -EINVAL;
1062
1063                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1064                 if (rc < 0)
1065                         return rc;
1066
1067                 arg = rc ? 1 : 0;
1068                 break;
1069         case PIN_CONFIG_DRIVE_STRENGTH:
1070                 /* rk3228 rk3288 RK3368 is the first with per-pin
1071                 * drive-strength
1072                 */
1073                 if ((RK3228 != info->ctrl->type) &&
1074                     (RK3288 != info->ctrl->type) &&
1075                     (RK3368 != info->ctrl->type))
1076                         return -ENOTSUPP;
1077
1078                 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1079                 if (rc < 0)
1080                         return rc;
1081
1082                 arg = rc;
1083                 break;
1084         default:
1085                 return -ENOTSUPP;
1086                 break;
1087         }
1088
1089         *config = pinconf_to_config_packed(param, arg);
1090
1091         return 0;
1092 }
1093
1094 static const struct pinconf_ops rockchip_pinconf_ops = {
1095         .pin_config_get                 = rockchip_pinconf_get,
1096         .pin_config_set                 = rockchip_pinconf_set,
1097         .is_generic                     = true,
1098 };
1099
1100 static const struct of_device_id rockchip_bank_match[] = {
1101         { .compatible = "rockchip,gpio-bank" },
1102         { .compatible = "rockchip,rk3188-gpio-bank0" },
1103         {},
1104 };
1105
1106 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1107                                          struct device_node *np)
1108 {
1109         struct device_node *child;
1110
1111         for_each_child_of_node(np, child) {
1112                 if (of_match_node(rockchip_bank_match, child))
1113                         continue;
1114
1115                 info->nfunctions++;
1116                 info->ngroups += of_get_child_count(child);
1117         }
1118 }
1119
1120 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1121                                          struct rockchip_pin_group *grp,
1122                                          struct rockchip_pinctrl *info,
1123                                          u32 index)
1124 {
1125         struct rockchip_pin_bank *bank;
1126         int size;
1127         const __be32 *list;
1128         int num;
1129         int i, j;
1130         int ret;
1131
1132         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1133
1134         /* Initialise group */
1135         grp->name = np->name;
1136
1137         /*
1138          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1139          * do sanity check and calculate pins number
1140          */
1141         list = of_get_property(np, "rockchip,pins", &size);
1142         /* we do not check return since it's safe node passed down */
1143         size /= sizeof(*list);
1144         if (!size || size % 4) {
1145                 dev_err(info->dev,
1146                         "wrong pins number or pins and configs should be by 4\n");
1147                 return -EINVAL;
1148         }
1149
1150         grp->npins = size / 4;
1151
1152         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1153                                  GFP_KERNEL);
1154         grp->data = devm_kzalloc(info->dev, grp->npins *
1155                                  sizeof(struct rockchip_pin_config),
1156                                  GFP_KERNEL);
1157         if (!grp->pins || !grp->data)
1158                 return -ENOMEM;
1159
1160         for (i = 0, j = 0; i < size; i += 4, j++) {
1161                 const __be32 *phandle;
1162                 struct device_node *np_config;
1163
1164                 num = be32_to_cpu(*list++);
1165                 bank = bank_num_to_bank(info, num);
1166                 if (IS_ERR(bank))
1167                         return PTR_ERR(bank);
1168
1169                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1170                 grp->data[j].func = be32_to_cpu(*list++);
1171
1172                 phandle = list++;
1173                 if (!phandle)
1174                         return -EINVAL;
1175
1176                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1177                 ret = pinconf_generic_parse_dt_config(np_config,
1178                                                       &grp->data[j].configs,
1179                                                       &grp->data[j].nconfigs);
1180                 if (ret)
1181                         return ret;
1182         }
1183
1184         return 0;
1185 }
1186
1187 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1188                                             struct rockchip_pinctrl *info,
1189                                             u32 index)
1190 {
1191         struct device_node *child;
1192         struct rockchip_pmx_func *func;
1193         struct rockchip_pin_group *grp;
1194         int ret;
1195         static u32 grp_index;
1196         u32 i = 0;
1197
1198         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1199
1200         func = &info->functions[index];
1201
1202         /* Initialise function */
1203         func->name = np->name;
1204         func->ngroups = of_get_child_count(np);
1205         if (func->ngroups <= 0)
1206                 return 0;
1207
1208         func->groups = devm_kzalloc(info->dev,
1209                                     func->ngroups * sizeof(char *), GFP_KERNEL);
1210         if (!func->groups)
1211                 return -ENOMEM;
1212
1213         for_each_child_of_node(np, child) {
1214                 func->groups[i] = child->name;
1215                 grp = &info->groups[grp_index++];
1216                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1217                 if (ret)
1218                         return ret;
1219         }
1220
1221         return 0;
1222 }
1223
1224 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1225                                      struct rockchip_pinctrl *info)
1226 {
1227         struct device *dev = &pdev->dev;
1228         struct device_node *np = dev->of_node;
1229         struct device_node *child;
1230         int ret;
1231         int i;
1232
1233         rockchip_pinctrl_child_count(info, np);
1234
1235         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1236         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1237
1238         info->functions = devm_kzalloc(dev, info->nfunctions *
1239                                               sizeof(struct rockchip_pmx_func),
1240                                               GFP_KERNEL);
1241         if (!info->functions) {
1242                 dev_err(dev, "failed to allocate memory for function list\n");
1243                 return -EINVAL;
1244         }
1245
1246         info->groups = devm_kzalloc(dev, info->ngroups *
1247                                             sizeof(struct rockchip_pin_group),
1248                                             GFP_KERNEL);
1249         if (!info->groups) {
1250                 dev_err(dev, "failed allocate memory for ping group list\n");
1251                 return -EINVAL;
1252         }
1253
1254         i = 0;
1255
1256         for_each_child_of_node(np, child) {
1257                 if (of_match_node(rockchip_bank_match, child))
1258                         continue;
1259
1260                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1261                 if (ret) {
1262                         dev_err(&pdev->dev, "failed to parse function\n");
1263                         return ret;
1264                 }
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int rockchip_pinctrl_register(struct platform_device *pdev,
1271                                      struct rockchip_pinctrl *info)
1272 {
1273         struct pinctrl_desc *ctrldesc = &info->pctl;
1274         struct pinctrl_pin_desc *pindesc, *pdesc;
1275         struct rockchip_pin_bank *pin_bank;
1276         int pin, bank, ret;
1277         int k;
1278
1279         ctrldesc->name = "rockchip-pinctrl";
1280         ctrldesc->owner = THIS_MODULE;
1281         ctrldesc->pctlops = &rockchip_pctrl_ops;
1282         ctrldesc->pmxops = &rockchip_pmx_ops;
1283         ctrldesc->confops = &rockchip_pinconf_ops;
1284
1285         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1286                         info->ctrl->nr_pins, GFP_KERNEL);
1287         if (!pindesc) {
1288                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1289                 return -ENOMEM;
1290         }
1291         ctrldesc->pins = pindesc;
1292         ctrldesc->npins = info->ctrl->nr_pins;
1293
1294         pdesc = pindesc;
1295         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1296                 pin_bank = &info->ctrl->pin_banks[bank];
1297                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1298                         pdesc->number = k;
1299                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1300                                                 pin_bank->name, pin);
1301                         pdesc++;
1302                 }
1303         }
1304
1305         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1306         if (!info->pctl_dev) {
1307                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1308                 return -EINVAL;
1309         }
1310
1311         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1312                 pin_bank = &info->ctrl->pin_banks[bank];
1313                 pin_bank->grange.name = pin_bank->name;
1314                 pin_bank->grange.id = bank;
1315                 pin_bank->grange.pin_base = pin_bank->pin_base;
1316                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1317                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1318                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1319                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1320         }
1321
1322         ret = rockchip_pinctrl_parse_dt(pdev, info);
1323         if (ret) {
1324                 pinctrl_unregister(info->pctl_dev);
1325                 return ret;
1326         }
1327
1328         return 0;
1329 }
1330
1331 /*
1332  * GPIO handling
1333  */
1334
1335 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1336 {
1337         return pinctrl_request_gpio(chip->base + offset);
1338 }
1339
1340 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1341 {
1342         pinctrl_free_gpio(chip->base + offset);
1343 }
1344
1345 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1346 {
1347         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1348         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1349         unsigned long flags;
1350         u32 data;
1351
1352         spin_lock_irqsave(&bank->slock, flags);
1353
1354         data = readl(reg);
1355         data &= ~BIT(offset);
1356         if (value)
1357                 data |= BIT(offset);
1358         writel(data, reg);
1359
1360         spin_unlock_irqrestore(&bank->slock, flags);
1361 }
1362
1363 /*
1364  * Returns the level of the pin for input direction and setting of the DR
1365  * register for output gpios.
1366  */
1367 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1368 {
1369         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1370         u32 data;
1371
1372         data = readl(bank->reg_base + GPIO_EXT_PORT);
1373         data >>= offset;
1374         data &= 1;
1375         return data;
1376 }
1377
1378 /*
1379  * gpiolib gpio_direction_input callback function. The setting of the pin
1380  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1381  * interface.
1382  */
1383 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1384 {
1385         return pinctrl_gpio_direction_input(gc->base + offset);
1386 }
1387
1388 /*
1389  * gpiolib gpio_direction_output callback function. The setting of the pin
1390  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1391  * interface.
1392  */
1393 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1394                                           unsigned offset, int value)
1395 {
1396         rockchip_gpio_set(gc, offset, value);
1397         return pinctrl_gpio_direction_output(gc->base + offset);
1398 }
1399
1400 /*
1401  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1402  * and a virtual IRQ, if not already present.
1403  */
1404 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1405 {
1406         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1407         unsigned int virq;
1408
1409         if (!bank->domain)
1410                 return -ENXIO;
1411
1412         virq = irq_create_mapping(bank->domain, offset);
1413
1414         return (virq) ? : -ENXIO;
1415 }
1416
1417 static const struct gpio_chip rockchip_gpiolib_chip = {
1418         .request = rockchip_gpio_request,
1419         .free = rockchip_gpio_free,
1420         .set = rockchip_gpio_set,
1421         .get = rockchip_gpio_get,
1422         .direction_input = rockchip_gpio_direction_input,
1423         .direction_output = rockchip_gpio_direction_output,
1424         .to_irq = rockchip_gpio_to_irq,
1425         .owner = THIS_MODULE,
1426 };
1427
1428 /*
1429  * Interrupt handling
1430  */
1431
1432 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1433 {
1434         struct irq_chip *chip = irq_get_chip(irq);
1435         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1436         u32 polarity = 0, data = 0;
1437         u32 pend;
1438         bool edge_changed = false;
1439
1440         pinctrl_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1441
1442         chained_irq_enter(chip, desc);
1443
1444         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1445
1446         if (bank->toggle_edge_mode) {
1447                 polarity = readl_relaxed(bank->reg_base +
1448                                          GPIO_INT_POLARITY);
1449                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1450         }
1451
1452         while (pend) {
1453                 unsigned int virq;
1454
1455                 irq = __ffs(pend);
1456                 pend &= ~BIT(irq);
1457                 virq = irq_linear_revmap(bank->domain, irq);
1458
1459                 if (!virq) {
1460                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1461                         continue;
1462                 }
1463
1464                 pinctrl_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1465
1466                 /*
1467                  * Triggering IRQ on both rising and falling edge
1468                  * needs manual intervention.
1469                  */
1470                 if (bank->toggle_edge_mode & BIT(irq)) {
1471                         if (data & BIT(irq))
1472                                 polarity &= ~BIT(irq);
1473                         else
1474                                 polarity |= BIT(irq);
1475
1476                         edge_changed = true;
1477                 }
1478
1479                 generic_handle_irq(virq);
1480         }
1481
1482         if (bank->toggle_edge_mode && edge_changed) {
1483                 /* Interrupt params should only be set with ints disabled */
1484                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1485                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1486                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1487                 writel(data, bank->reg_base + GPIO_INTEN);
1488         }
1489
1490         chained_irq_exit(chip, desc);
1491 }
1492
1493 static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1494 {
1495         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1496         u32 mask = BIT(d->hwirq);
1497         u32 polarity;
1498         u32 level;
1499         u32 data;
1500         int ret;
1501         unsigned long flags;
1502
1503         /* make sure the pin is configured as gpio input */
1504         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1505         if (ret < 0)
1506                 return ret;
1507
1508         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1509         data &= ~mask;
1510         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1511
1512         if (type & IRQ_TYPE_EDGE_BOTH)
1513                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1514         else
1515                 __irq_set_handler_locked(d->irq, handle_level_irq);
1516
1517         spin_lock_irqsave(&bank->slock, flags);
1518
1519         level = readl_relaxed(bank->reg_base + GPIO_INTTYPE_LEVEL);
1520         polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY);
1521
1522         switch (type) {
1523         case IRQ_TYPE_EDGE_BOTH:
1524                 bank->toggle_edge_mode |= mask;
1525                 level |= mask;
1526
1527                 /*
1528                  * Determine gpio state. If 1 next interrupt should be falling
1529                  * otherwise rising.
1530                  */
1531                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1532                 if (data & mask)
1533                         polarity &= ~mask;
1534                 else
1535                         polarity |= mask;
1536                 break;
1537         case IRQ_TYPE_EDGE_RISING:
1538                 bank->toggle_edge_mode &= ~mask;
1539                 level |= mask;
1540                 polarity |= mask;
1541                 break;
1542         case IRQ_TYPE_EDGE_FALLING:
1543                 bank->toggle_edge_mode &= ~mask;
1544                 level |= mask;
1545                 polarity &= ~mask;
1546                 break;
1547         case IRQ_TYPE_LEVEL_HIGH:
1548                 bank->toggle_edge_mode &= ~mask;
1549                 level &= ~mask;
1550                 polarity |= mask;
1551                 break;
1552         case IRQ_TYPE_LEVEL_LOW:
1553                 bank->toggle_edge_mode &= ~mask;
1554                 level &= ~mask;
1555                 polarity &= ~mask;
1556                 break;
1557         default:
1558                 return -EINVAL;
1559         }
1560
1561         writel_relaxed(level, bank->reg_base + GPIO_INTTYPE_LEVEL);
1562         writel_relaxed(polarity, bank->reg_base + GPIO_INT_POLARITY);
1563
1564         spin_unlock_irqrestore(&bank->slock, flags);
1565
1566         return 0;
1567 }
1568
1569 static inline void rockchip_gpio_bit_op(void __iomem *reg_base
1570         , unsigned int offset, u32 bit, unsigned char flag)
1571 {
1572         u32 val = __raw_readl(reg_base + offset);
1573
1574         if (flag)
1575                 val |= BIT(bit);
1576         else
1577                 val &= ~BIT(bit);
1578
1579         __raw_writel(val, reg_base + offset);
1580 }
1581
1582 static inline unsigned gpio_to_bit(struct rockchip_pin_bank *bank,
1583                                    unsigned gpio)
1584 {
1585         while (gpio >= (bank->pin_base + bank->nr_pins))
1586                 bank++;
1587
1588         return gpio - bank->pin_base;
1589 }
1590
1591 static inline unsigned offset_to_bit(unsigned offset)
1592 {
1593         return 1u << offset;
1594 }
1595
1596 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
1597 {
1598         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
1599 }
1600
1601 static void GPIODisableIntr(void __iomem *reg_base, unsigned int bit)
1602 {
1603         rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 0);
1604 }
1605
1606 static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
1607 {
1608         rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
1609 }
1610
1611 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1612 {
1613         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1614         u32 bit = d->hwirq;
1615         unsigned long flags;
1616
1617         spin_lock_irqsave(&bank->slock, flags);
1618
1619         if (on)
1620                 bank->suspend_wakeup |= BIT(bit);
1621         else
1622                 bank->suspend_wakeup &= ~BIT(bit);
1623         spin_unlock_irqrestore(&bank->slock, flags);
1624
1625         return 0;
1626 }
1627
1628 static void rockchip_gpio_irq_unmask(struct irq_data *d)
1629 {
1630         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1631         u32 bit = d->hwirq;
1632         unsigned long flags;
1633
1634         spin_lock_irqsave(&bank->slock, flags);
1635         GPIOEnableIntr(bank->reg_base, bit);
1636         spin_unlock_irqrestore(&bank->slock, flags);
1637 }
1638
1639 static void rockchip_gpio_irq_mask(struct irq_data *d)
1640 {
1641         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1642         u32 bit = d->hwirq;
1643         unsigned long flags;
1644
1645         spin_lock_irqsave(&bank->slock, flags);
1646         GPIODisableIntr(bank->reg_base, bit);
1647         spin_unlock_irqrestore(&bank->slock, flags);
1648 }
1649
1650 static void rockchip_gpio_irq_ack(struct irq_data *d)
1651 {
1652         struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
1653         u32 bit = d->hwirq;
1654
1655         GPIOAckIntr(bank->reg_base, bit);
1656 }
1657
1658 static struct irq_chip rockchip_gpio_irq_chip = {
1659         .name           = "ROCKCHIP_GPIO_CHIP",
1660         .irq_ack        = rockchip_gpio_irq_ack,
1661         .irq_disable    = rockchip_gpio_irq_mask,
1662         .irq_mask       = rockchip_gpio_irq_mask,
1663         .irq_unmask     = rockchip_gpio_irq_unmask,
1664         .irq_set_type   = rockchip_gpio_irq_set_type,
1665         .irq_set_wake   = rockchip_gpio_irq_set_wake,
1666 };
1667
1668 static int rockchip_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1669                                  irq_hw_number_t hwirq)
1670 {
1671         struct rockchip_pin_bank *bank = d->host_data;
1672         struct irq_data *irq_data = irq_get_irq_data(irq);
1673
1674         if (!bank) {
1675                 dev_err(bank->drvdata->dev, "%s:bank=0x%p,irq=%d\n",
1676                         __func__, bank, irq);
1677                 return -EINVAL;
1678         }
1679
1680         irq_set_chip_and_handler(irq, &rockchip_gpio_irq_chip,
1681                                  handle_level_irq);
1682         irq_set_chip_data(irq, bank);
1683         set_irq_flags(irq, IRQF_VALID);
1684
1685         irq_data->hwirq = hwirq;
1686         irq_data->irq = irq;
1687
1688         pinctrl_dbg(bank->drvdata->dev, "%s:irq = %d, hwirq =%ld\n",
1689                     __func__, irq, hwirq);
1690         return 0;
1691 }
1692
1693 static const struct irq_domain_ops rockchip_gpio_irq_ops = {
1694         .map = rockchip_gpio_irq_map,
1695         .xlate = irq_domain_xlate_twocell,
1696 };
1697
1698 static int rockchip_interrupts_register(struct platform_device *pdev,
1699                                         struct rockchip_pinctrl *info)
1700 {
1701         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1702         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1703         int i;
1704
1705         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1706                 if (!bank->valid) {
1707                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1708                                  bank->name);
1709                         continue;
1710                 }
1711
1712                 __raw_writel(0, bank->reg_base + GPIO_INTEN);
1713
1714                 bank->drvdata = info;
1715                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1716                                 &rockchip_gpio_irq_ops, bank);
1717                 if (!bank->domain) {
1718                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1719                                  bank->name);
1720                         continue;
1721                 }
1722
1723                 irq_set_handler_data(bank->irq, bank);
1724                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1725         }
1726
1727         return 0;
1728 }
1729
1730 static int rockchip_gpiolib_register(struct platform_device *pdev,
1731                                      struct rockchip_pinctrl *info)
1732 {
1733         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1734         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1735         struct gpio_chip *gc;
1736         int ret;
1737         int i;
1738
1739         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1740                 if (!bank->valid) {
1741                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1742                                  bank->name);
1743                         continue;
1744                 }
1745
1746                 bank->gpio_chip = rockchip_gpiolib_chip;
1747
1748                 gc = &bank->gpio_chip;
1749                 gc->base = bank->pin_base;
1750                 gc->ngpio = bank->nr_pins;
1751                 gc->dev = &pdev->dev;
1752                 gc->of_node = bank->of_node;
1753                 gc->label = bank->name;
1754
1755                 ret = gpiochip_add(gc);
1756                 if (ret) {
1757                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1758                                 gc->label, ret);
1759                         goto fail;
1760                 }
1761         }
1762
1763         rockchip_interrupts_register(pdev, info);
1764
1765         return 0;
1766
1767 fail:
1768         for (--i, --bank; i >= 0; --i, --bank) {
1769                 if (!bank->valid)
1770                         continue;
1771
1772                 if (gpiochip_remove(&bank->gpio_chip))
1773                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1774                                 bank->gpio_chip.label);
1775         }
1776         return ret;
1777 }
1778
1779 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1780                                        struct rockchip_pinctrl *info)
1781 {
1782         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1783         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1784         int ret = 0;
1785         int i;
1786
1787         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1788                 if (!bank->valid)
1789                         continue;
1790
1791                 ret = gpiochip_remove(&bank->gpio_chip);
1792         }
1793
1794         if (ret)
1795                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1796
1797         return ret;
1798 }
1799
1800 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1801                                   struct rockchip_pinctrl *info)
1802 {
1803         struct resource res;
1804         void __iomem *base;
1805
1806         if (of_address_to_resource(bank->of_node, 0, &res)) {
1807                 dev_err(info->dev, "cannot find IO resource for bank\n");
1808                 return -ENOENT;
1809         }
1810
1811         bank->reg_base = devm_ioremap_resource(info->dev, &res);
1812         if (IS_ERR(bank->reg_base))
1813                 return PTR_ERR(bank->reg_base);
1814
1815         /*
1816          * special case, where parts of the pull setting-registers are
1817          * part of the PMU register space
1818          */
1819         if (of_device_is_compatible(bank->of_node,
1820                                     "rockchip,rk3188-gpio-bank0")) {
1821                 struct device_node *node;
1822
1823                 node = of_parse_phandle(bank->of_node->parent,
1824                                         "rockchip,pmugrf", 0);
1825                 if (!node) {
1826                         if (of_address_to_resource(bank->of_node, 1, &res)) {
1827                                 dev_err(info->dev, "cannot find IO resource for bank\n");
1828                                 return -ENOENT;
1829                         }
1830
1831                         base = devm_ioremap_resource(info->dev, &res);
1832                         if (IS_ERR(base))
1833                                 return PTR_ERR(base);
1834                         rockchip_regmap_config.max_register =
1835                                                     resource_size(&res) - 4;
1836                         rockchip_regmap_config.name =
1837                                             "rockchip,rk3188-gpio-bank0-pull";
1838                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1839                                                     base,
1840                                                     &rockchip_regmap_config);
1841                 }
1842         }
1843
1844         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1845
1846         bank->clk = of_clk_get(bank->of_node, 0);
1847         if (IS_ERR(bank->clk))
1848                 return PTR_ERR(bank->clk);
1849
1850         return clk_prepare_enable(bank->clk);
1851 }
1852
1853 static const struct of_device_id rockchip_pinctrl_dt_match[];
1854
1855 /* retrieve the soc specific data */
1856 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1857                                                 struct rockchip_pinctrl *d,
1858                                                 struct platform_device *pdev)
1859 {
1860         const struct of_device_id *match;
1861         struct device_node *node = pdev->dev.of_node;
1862         struct device_node *np;
1863         struct rockchip_pin_ctrl *ctrl;
1864         struct rockchip_pin_bank *bank;
1865         int grf_offs, pmu_offs, i, j;
1866
1867         match = of_match_node(rockchip_pinctrl_dt_match, node);
1868         ctrl = (struct rockchip_pin_ctrl *)match->data;
1869
1870         for_each_child_of_node(node, np) {
1871                 if (!of_find_property(np, "gpio-controller", NULL))
1872                         continue;
1873
1874                 bank = ctrl->pin_banks;
1875                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1876                         if (!strcmp(bank->name, np->name)) {
1877                                 bank->of_node = np;
1878
1879                                 if (!rockchip_get_bank_data(bank, d))
1880                                         bank->valid = true;
1881
1882                                 break;
1883                         }
1884                 }
1885         }
1886
1887         grf_offs = ctrl->grf_mux_offset;
1888         pmu_offs = ctrl->pmu_mux_offset;
1889         bank = ctrl->pin_banks;
1890         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1891                 int bank_pins = 0;
1892
1893                 spin_lock_init(&bank->slock);
1894                 bank->drvdata = d;
1895                 bank->pin_base = ctrl->nr_pins;
1896                 ctrl->nr_pins += bank->nr_pins;
1897
1898                 /* calculate iomux offsets */
1899                 for (j = 0; j < 4; j++) {
1900                         struct rockchip_iomux *iom = &bank->iomux[j];
1901                         int inc;
1902
1903                         if (bank_pins >= bank->nr_pins)
1904                                 break;
1905
1906                         /* preset offset value, set new start value */
1907                         if (iom->offset >= 0) {
1908                                 if (iom->type & IOMUX_SOURCE_PMU)
1909                                         pmu_offs = iom->offset;
1910                                 else
1911                                         grf_offs = iom->offset;
1912                         } else { /* set current offset */
1913                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1914                                                         pmu_offs : grf_offs;
1915                         }
1916
1917                         pinctrl_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1918                                     i, j, iom->offset);
1919
1920                         /*
1921                          * Increase offset according to iomux width.
1922                          * 4bit iomux'es are spread over two registers.
1923                          */
1924                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1925                         if (iom->type & IOMUX_SOURCE_PMU)
1926                                 pmu_offs += inc;
1927                         else
1928                                 grf_offs += inc;
1929
1930                         bank_pins += 8;
1931                 }
1932         }
1933
1934         return ctrl;
1935 }
1936
1937 #ifdef CONFIG_PM
1938 static int rockchip_pinctrl_suspend(void)
1939 {
1940         struct rockchip_pinctrl *info = g_info;
1941         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1942         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1943         int n;
1944
1945         for (n = 0; n < ctrl->nr_banks; n++) {
1946                 bank->saved_wakeup = __raw_readl(bank->reg_base + GPIO_INTEN);
1947                 __raw_writel(bank->suspend_wakeup, bank->reg_base + GPIO_INTEN);
1948
1949                 if (!bank->suspend_wakeup)
1950                         clk_disable_unprepare(bank->clk);
1951                 bank++;
1952         }
1953
1954         return 0;
1955 }
1956
1957 static void rockchip_pinctrl_resume(void)
1958 {
1959         struct rockchip_pinctrl *info = g_info;
1960         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1961         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1962         int n;
1963         u32 isr;
1964
1965         for (n = 0; n < ctrl->nr_banks; n++) {
1966                 if (!bank->suspend_wakeup)
1967                         clk_prepare_enable(bank->clk);
1968
1969                 /* keep enable for resume irq */
1970                  isr = __raw_readl(bank->reg_base + GPIO_INT_STATUS);
1971                         __raw_writel(bank->saved_wakeup
1972                                 | (bank->suspend_wakeup & isr)
1973                                         , bank->reg_base + GPIO_INTEN);
1974                 bank++;
1975         }
1976 }
1977
1978 static struct syscore_ops rockchip_gpio_syscore_ops = {
1979         .suspend        = rockchip_pinctrl_suspend,
1980         .resume         = rockchip_pinctrl_resume,
1981 };
1982 #endif
1983
1984 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1985 {
1986         struct rockchip_pinctrl *info;
1987         struct device *dev = &pdev->dev;
1988         struct rockchip_pin_ctrl *ctrl;
1989         struct device_node *np = pdev->dev.of_node, *node;
1990         struct resource *res;
1991         void __iomem *base;
1992         int ret;
1993
1994         if (!dev->of_node) {
1995                 dev_err(dev, "device tree node not found\n");
1996                 return -ENODEV;
1997         }
1998
1999         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2000         if (!info)
2001                 return -ENOMEM;
2002
2003         info->dev = dev;
2004
2005         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2006         if (!ctrl) {
2007                 dev_err(dev, "driver data not available\n");
2008                 return -EINVAL;
2009         }
2010         info->ctrl = ctrl;
2011         g_info = info;
2012
2013         node = of_parse_phandle(np, "rockchip,grf", 0);
2014         if (node) {
2015                 info->regmap_base = syscon_node_to_regmap(node);
2016                 if (IS_ERR(info->regmap_base))
2017                         return PTR_ERR(info->regmap_base);
2018         } else {
2019                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2020                 base = devm_ioremap_resource(&pdev->dev, res);
2021                 if (IS_ERR(base))
2022                         return PTR_ERR(base);
2023
2024                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2025                 rockchip_regmap_config.name = "rockchip,pinctrl";
2026                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2027                                                     &rockchip_regmap_config);
2028
2029                 /* to check for the old dt-bindings */
2030                 info->reg_size = resource_size(res);
2031
2032                 /* Honor the old binding, with pull registers as 2nd resource */
2033                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2034                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2035                         base = devm_ioremap_resource(&pdev->dev, res);
2036                         if (IS_ERR(base))
2037                                 return PTR_ERR(base);
2038
2039                         rockchip_regmap_config.max_register =
2040                                                         resource_size(res) - 4;
2041                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2042                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2043                                                     base,
2044                                                     &rockchip_regmap_config);
2045                 }
2046         }
2047
2048         /* try to find the optional reference to the pmu syscon */
2049         node = of_parse_phandle(np, "rockchip,pmugrf", 0);
2050         if (node) {
2051                 info->regmap_pmu = syscon_node_to_regmap(node);
2052                 if (IS_ERR(info->regmap_pmu))
2053                         return PTR_ERR(info->regmap_pmu);
2054         }
2055
2056         ret = rockchip_gpiolib_register(pdev, info);
2057         if (ret)
2058                 return ret;
2059
2060         ret = rockchip_pinctrl_register(pdev, info);
2061         if (ret) {
2062                 rockchip_gpiolib_unregister(pdev, info);
2063                 return ret;
2064         }
2065
2066         platform_set_drvdata(pdev, info);
2067 #ifdef CONFIG_PM
2068         register_syscore_ops(&rockchip_gpio_syscore_ops);
2069 #endif
2070
2071         return 0;
2072 }
2073
2074 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2075         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
2076         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2077         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2078         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2079 };
2080
2081 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2082                 .pin_banks              = rk3228_pin_banks,
2083                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2084                 .label                  = "RK3228-GPIO",
2085                 .type                   = RK3228,
2086                 .grf_mux_offset         = 0x0,
2087                 .pmu_mux_offset         = 0x0,
2088                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2089 };
2090 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2091         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2092                              IOMUX_SOURCE_PMU,
2093                              IOMUX_SOURCE_PMU,
2094                              IOMUX_SOURCE_PMU),
2095         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2096         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2097         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2098 };
2099
2100 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2101                 .pin_banks              = rk3368_pin_banks,
2102                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2103                 .label                  = "RK3368-GPIO",
2104                 .type                   = RK3368,
2105                 .grf_mux_offset         = 0x0,
2106                 .pmu_mux_offset         = 0x0,
2107                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2108 };
2109
2110 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2111         { .compatible = "rockchip,rk3228-pinctrl",
2112                 .data = (void *)&rk3228_pin_ctrl },
2113         { .compatible = "rockchip,rk3368-pinctrl",
2114                 .data = (void *)&rk3368_pin_ctrl },
2115         {},
2116 };
2117 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2118
2119 static struct platform_driver rockchip_pinctrl_driver = {
2120         .probe          = rockchip_pinctrl_probe,
2121         .driver = {
2122                 .name   = "rk3368-pinctrl",
2123                 .owner  = THIS_MODULE,
2124                 .of_match_table = rockchip_pinctrl_dt_match,
2125         },
2126 };
2127
2128 static int __init rockchip_pinctrl_drv_register(void)
2129 {
2130         return platform_driver_register(&rockchip_pinctrl_driver);
2131 }
2132 postcore_initcall(rockchip_pinctrl_drv_register);
2133
2134 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2135 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2136 MODULE_LICENSE("GPL v2");