2 * Copyright (C) ST-Ericsson SA 2013
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/err.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/mfd/abx500.h>
26 #include <linux/mfd/abx500/ab8500.h>
27 #include <linux/mfd/abx500/ab8500-gpio.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
34 #include "pinctrl-abx500.h"
37 * The AB9540 and AB8540 GPIO support are extended versions
38 * of the AB8500 GPIO support.
39 * The AB9540 supports an additional (7th) register so that
40 * more GPIO may be configured and used.
41 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
42 * internal pull-up and pull-down capabilities.
46 * GPIO registers offset
49 #define AB8500_GPIO_SEL1_REG 0x00
50 #define AB8500_GPIO_SEL2_REG 0x01
51 #define AB8500_GPIO_SEL3_REG 0x02
52 #define AB8500_GPIO_SEL4_REG 0x03
53 #define AB8500_GPIO_SEL5_REG 0x04
54 #define AB8500_GPIO_SEL6_REG 0x05
55 #define AB9540_GPIO_SEL7_REG 0x06
57 #define AB8500_GPIO_DIR1_REG 0x10
58 #define AB8500_GPIO_DIR2_REG 0x11
59 #define AB8500_GPIO_DIR3_REG 0x12
60 #define AB8500_GPIO_DIR4_REG 0x13
61 #define AB8500_GPIO_DIR5_REG 0x14
62 #define AB8500_GPIO_DIR6_REG 0x15
63 #define AB9540_GPIO_DIR7_REG 0x16
65 #define AB8500_GPIO_OUT1_REG 0x20
66 #define AB8500_GPIO_OUT2_REG 0x21
67 #define AB8500_GPIO_OUT3_REG 0x22
68 #define AB8500_GPIO_OUT4_REG 0x23
69 #define AB8500_GPIO_OUT5_REG 0x24
70 #define AB8500_GPIO_OUT6_REG 0x25
71 #define AB9540_GPIO_OUT7_REG 0x26
73 #define AB8500_GPIO_PUD1_REG 0x30
74 #define AB8500_GPIO_PUD2_REG 0x31
75 #define AB8500_GPIO_PUD3_REG 0x32
76 #define AB8500_GPIO_PUD4_REG 0x33
77 #define AB8500_GPIO_PUD5_REG 0x34
78 #define AB8500_GPIO_PUD6_REG 0x35
79 #define AB9540_GPIO_PUD7_REG 0x36
81 #define AB8500_GPIO_IN1_REG 0x40
82 #define AB8500_GPIO_IN2_REG 0x41
83 #define AB8500_GPIO_IN3_REG 0x42
84 #define AB8500_GPIO_IN4_REG 0x43
85 #define AB8500_GPIO_IN5_REG 0x44
86 #define AB8500_GPIO_IN6_REG 0x45
87 #define AB9540_GPIO_IN7_REG 0x46
88 #define AB8540_GPIO_VINSEL_REG 0x47
89 #define AB8540_GPIO_PULL_UPDOWN_REG 0x48
90 #define AB8500_GPIO_ALTFUN_REG 0x50
91 #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
92 #define AB8540_GPIO_VINSEL_MASK 0x03
93 #define AB8540_GPIOX_VBAT_START 51
94 #define AB8540_GPIOX_VBAT_END 54
96 struct abx500_pinctrl {
98 struct pinctrl_dev *pctldev;
99 struct abx500_pinctrl_soc_data *soc;
100 struct gpio_chip chip;
101 struct ab8500 *parent;
102 struct abx500_gpio_irq_cluster *irq_cluster;
103 int irq_cluster_size;
107 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
108 * @chip: Member of the structure abx500_pinctrl
110 static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
112 return container_of(chip, struct abx500_pinctrl, chip);
115 static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
116 unsigned offset, bool *bit)
118 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
124 ret = abx500_get_register_interruptible(pct->dev,
125 AB8500_MISC, reg, &val);
127 *bit = !!(val & BIT(pos));
131 "%s read reg =%x, offset=%x failed\n",
132 __func__, reg, offset);
137 static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
138 unsigned offset, int val)
140 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
145 ret = abx500_mask_and_set_register_interruptible(pct->dev,
146 AB8500_MISC, reg, BIT(pos), val << pos);
148 dev_err(pct->dev, "%s write failed\n", __func__);
154 * abx500_gpio_get() - Get the particular GPIO value
156 * @offset: GPIO number to read
158 static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
160 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
164 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
167 dev_err(pct->dev, "%s failed\n", __func__);
174 static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
176 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
179 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
181 dev_err(pct->dev, "%s write failed\n", __func__);
184 static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
185 int offset, enum abx500_gpio_pull_updown val)
189 struct pullud *pullud;
191 if (!pct->soc->pullud) {
192 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
198 pullud = pct->soc->pullud;
200 if ((offset < pullud->first_pin)
201 || (offset > pullud->last_pin)) {
206 pos = (offset - pullud->first_pin) << 1;
208 ret = abx500_mask_and_set_register_interruptible(pct->dev,
209 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
210 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
214 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
219 static int abx500_gpio_direction_output(struct gpio_chip *chip,
223 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
224 struct pullud *pullud = pct->soc->pullud;
228 /* set direction as output */
229 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
233 /* disable pull down */
234 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
238 /* if supported, disable both pull down and pull up */
240 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
241 ret = abx500_config_pull_updown(pct,
243 ABX500_GPIO_PULL_NONE);
248 /* set the output as 1 or 0 */
249 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
252 static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
254 /* set the register as input */
255 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
258 static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
260 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
261 /* The AB8500 GPIO numbers are off by one */
262 int gpio = offset + 1;
266 for (i = 0; i < pct->irq_cluster_size; i++) {
267 struct abx500_gpio_irq_cluster *cluster =
268 &pct->irq_cluster[i];
270 if (gpio >= cluster->start && gpio <= cluster->end) {
272 * The ABx500 GPIO's associated IRQs are clustered together
273 * throughout the interrupt numbers at irregular intervals.
274 * To solve this quandry, we have placed the read-in values
275 * into the cluster information table.
277 hwirq = gpio - cluster->start + cluster->to_irq;
278 return irq_create_mapping(pct->parent->domain, hwirq);
285 static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
286 unsigned gpio, int alt_setting)
288 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
289 struct alternate_functions af = pct->soc->alternate_functions[gpio];
294 const char *modes[] = {
295 [ABX500_DEFAULT] = "default",
296 [ABX500_ALT_A] = "altA",
297 [ABX500_ALT_B] = "altB",
298 [ABX500_ALT_C] = "altC",
302 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
303 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
304 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
305 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
310 /* on ABx5xx, there is no GPIO0, so adjust the offset */
313 switch (alt_setting) {
316 * for ABx5xx family, default mode is always selected by
317 * writing 0 to GPIOSELx register, except for pins which
318 * support at least ALT_B mode, default mode is selected
319 * by writing 1 to GPIOSELx register
322 if (af.alt_bit1 != UNUSED)
325 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
331 * for ABx5xx family, alt_a mode is always selected by
332 * writing 1 to GPIOSELx register, except for pins which
333 * support at least ALT_B mode, alt_a mode is selected
334 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
337 if (af.alt_bit1 != UNUSED) {
338 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
340 ret = abx500_gpio_set_bits(chip,
341 AB8500_GPIO_ALTFUN_REG,
343 !!(af.alta_val && BIT(0)));
344 if (af.alt_bit2 != UNUSED)
345 ret = abx500_gpio_set_bits(chip,
346 AB8500_GPIO_ALTFUN_REG,
348 !!(af.alta_val && BIT(1)));
350 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
355 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
357 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
358 af.alt_bit1, !!(af.altb_val && BIT(0)));
359 if (af.alt_bit2 != UNUSED)
360 ret = abx500_gpio_set_bits(chip,
361 AB8500_GPIO_ALTFUN_REG,
363 !!(af.altb_val && BIT(1)));
367 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
369 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
370 af.alt_bit2, !!(af.altc_val && BIT(0)));
371 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
372 af.alt_bit2, !!(af.altc_val && BIT(1)));
376 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
384 static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
391 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
392 struct alternate_functions af = pct->soc->alternate_functions[gpio];
393 /* on ABx5xx, there is no GPIO0, so adjust the offset */
394 unsigned offset = gpio - 1;
397 * if gpiosel_bit is set to unused,
398 * it means no GPIO or special case
400 if (af.gpiosel_bit == UNUSED)
401 return ABX500_DEFAULT;
403 /* read GpioSelx register */
404 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
405 af.gpiosel_bit, &bit_mode);
409 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
410 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
412 "alt_bitX value not in correct range (-1 to 7)\n");
416 /* if alt_bit2 is used, alt_bit1 must be used too */
417 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
419 "if alt_bit2 is used, alt_bit1 can't be unused\n");
423 /* check if pin use AlternateFunction register */
424 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
427 * if pin GPIOSEL bit is set and pin supports alternate function,
428 * it means DEFAULT mode
431 return ABX500_DEFAULT;
434 * pin use the AlternatFunction register
435 * read alt_bit1 value
437 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
438 af.alt_bit1, &alt_bit1);
440 if (af.alt_bit2 != UNUSED)
441 /* read alt_bit2 value */
442 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
447 mode = (alt_bit2 << 1) + alt_bit1;
448 if (mode == af.alta_val)
450 else if (mode == af.altb_val)
456 #ifdef CONFIG_DEBUG_FS
458 #include <linux/seq_file.h>
460 static void abx500_gpio_dbg_show_one(struct seq_file *s,
461 struct pinctrl_dev *pctldev,
462 struct gpio_chip *chip,
463 unsigned offset, unsigned gpio)
465 const char *label = gpiochip_is_requested(chip, offset - 1);
466 u8 gpio_offset = offset - 1;
471 const char *modes[] = {
472 [ABX500_DEFAULT] = "default",
473 [ABX500_ALT_A] = "altA",
474 [ABX500_ALT_B] = "altB",
475 [ABX500_ALT_C] = "altC",
478 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
479 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
482 mode = abx500_get_mode(pctldev, chip, offset);
484 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
485 gpio, label ?: "(none)",
486 is_out ? "out" : "in ",
489 ? (chip->get(chip, offset) ? "hi" : "lo")
491 : (pull ? "pull up" : "pull down"),
492 (mode < 0) ? "unknown" : modes[mode]);
495 static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
498 unsigned gpio = chip->base;
499 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
500 struct pinctrl_dev *pctldev = pct->pctldev;
502 for (i = 0; i < chip->ngpio; i++, gpio++) {
503 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
504 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
510 static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
511 struct pinctrl_dev *pctldev,
512 struct gpio_chip *chip,
513 unsigned offset, unsigned gpio)
516 #define abx500_gpio_dbg_show NULL
519 static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
521 int gpio = chip->base + offset;
523 return pinctrl_request_gpio(gpio);
526 static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
528 int gpio = chip->base + offset;
530 pinctrl_free_gpio(gpio);
533 static struct gpio_chip abx500gpio_chip = {
534 .label = "abx500-gpio",
535 .owner = THIS_MODULE,
536 .request = abx500_gpio_request,
537 .free = abx500_gpio_free,
538 .direction_input = abx500_gpio_direction_input,
539 .get = abx500_gpio_get,
540 .direction_output = abx500_gpio_direction_output,
541 .set = abx500_gpio_set,
542 .to_irq = abx500_gpio_to_irq,
543 .dbg_show = abx500_gpio_dbg_show,
546 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
548 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
550 return pct->soc->nfunctions;
553 static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
556 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
558 return pct->soc->functions[function].name;
561 static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
563 const char * const **groups,
564 unsigned * const num_groups)
566 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
568 *groups = pct->soc->functions[function].groups;
569 *num_groups = pct->soc->functions[function].ngroups;
574 static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
577 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
578 struct gpio_chip *chip = &pct->chip;
579 const struct abx500_pingroup *g;
583 g = &pct->soc->groups[group];
584 if (g->altsetting < 0)
587 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
589 for (i = 0; i < g->npins; i++) {
590 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
591 g->pins[i], g->altsetting);
593 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
599 static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
600 unsigned function, unsigned group)
602 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
603 const struct abx500_pingroup *g;
605 g = &pct->soc->groups[group];
606 if (g->altsetting < 0)
609 /* FIXME: poke out the mux, set the pin to some default state? */
610 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
613 static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
614 struct pinctrl_gpio_range *range,
617 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
618 const struct abx500_pinrange *p;
623 * Different ranges have different ways to enable GPIO function on a
624 * pin, so refer back to our local range type, where we handily define
625 * what altfunc enables GPIO for a certain pin.
627 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
628 p = &pct->soc->gpio_ranges[i];
629 if ((offset >= p->offset) &&
630 (offset < (p->offset + p->npins)))
634 if (i == pct->soc->gpio_num_ranges) {
635 dev_err(pct->dev, "%s failed to locate range\n", __func__);
639 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
642 ret = abx500_set_mode(pct->pctldev, &pct->chip,
645 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
652 static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
653 struct pinctrl_gpio_range *range,
658 static const struct pinmux_ops abx500_pinmux_ops = {
659 .get_functions_count = abx500_pmx_get_funcs_cnt,
660 .get_function_name = abx500_pmx_get_func_name,
661 .get_function_groups = abx500_pmx_get_func_groups,
662 .enable = abx500_pmx_enable,
663 .disable = abx500_pmx_disable,
664 .gpio_request_enable = abx500_gpio_request_enable,
665 .gpio_disable_free = abx500_gpio_disable_free,
668 static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
670 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
672 return pct->soc->ngroups;
675 static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
678 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
680 return pct->soc->groups[selector].name;
683 static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
685 const unsigned **pins,
688 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
690 *pins = pct->soc->groups[selector].pins;
691 *num_pins = pct->soc->groups[selector].npins;
696 static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
697 struct seq_file *s, unsigned offset)
699 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
700 struct gpio_chip *chip = &pct->chip;
702 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
703 chip->base + offset - 1);
706 static const struct pinctrl_ops abx500_pinctrl_ops = {
707 .get_groups_count = abx500_get_groups_cnt,
708 .get_group_name = abx500_get_group_name,
709 .get_group_pins = abx500_get_group_pins,
710 .pin_dbg_show = abx500_pin_dbg_show,
713 static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
715 unsigned long *config)
720 static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
722 unsigned long config)
724 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
725 struct pullud *pullud = pct->soc->pullud;
726 struct gpio_chip *chip = &pct->chip;
729 enum pin_config_param param = pinconf_to_config_param(config);
730 enum pin_config_param argument = pinconf_to_config_argument(config);
732 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
733 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
734 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
735 (argument ? "pull up" : "pull down"));
737 /* on ABx500, there is no GPIO0, so adjust the offset */
741 case PIN_CONFIG_BIAS_PULL_DOWN:
743 * if argument = 1 set the pull down
744 * else clear the pull down
746 ret = abx500_gpio_direction_input(chip, offset);
748 * Some chips only support pull down, while some actually
749 * support both pull up and pull down. Such chips have
750 * a "pullud" range specified for the pins that support
751 * both features. If the pin is not within that range, we
752 * fall back to the old bit set that only support pull down.
755 pin >= pullud->first_pin &&
756 pin <= pullud->last_pin)
757 ret = abx500_config_pull_updown(pct,
759 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
761 /* Chip only supports pull down */
762 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
763 offset, argument ? 0 : 1);
766 case PIN_CONFIG_OUTPUT:
767 ret = abx500_gpio_direction_output(chip, offset, argument);
772 dev_err(chip->dev, "illegal configuration requested\n");
780 static const struct pinconf_ops abx500_pinconf_ops = {
781 .pin_config_get = abx500_pin_config_get,
782 .pin_config_set = abx500_pin_config_set,
785 static struct pinctrl_desc abx500_pinctrl_desc = {
786 .name = "pinctrl-abx500",
787 .pctlops = &abx500_pinctrl_ops,
788 .pmxops = &abx500_pinmux_ops,
789 .confops = &abx500_pinconf_ops,
790 .owner = THIS_MODULE,
793 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
795 unsigned int lowest = 0;
796 unsigned int highest = 0;
797 unsigned int npins = 0;
801 * Compute number of GPIOs from the last SoC gpio range descriptors
802 * These ranges may include "holes" but the GPIO number space shall
803 * still be homogeneous, so we need to detect and account for any
804 * such holes so that these are included in the number of GPIO pins.
806 for (i = 0; i < soc->gpio_num_ranges; i++) {
809 const struct abx500_pinrange *p;
811 p = &soc->gpio_ranges[i];
813 gend = p->offset + p->npins - 1;
816 /* First iteration, set start values */
826 /* this gives the absolute number of pins */
827 npins = highest - lowest + 1;
831 static const struct of_device_id abx500_gpio_match[] = {
832 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
833 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
834 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
835 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
839 static int abx500_gpio_probe(struct platform_device *pdev)
841 struct ab8500_platform_data *abx500_pdata =
842 dev_get_platdata(pdev->dev.parent);
843 struct abx500_gpio_platform_data *pdata = NULL;
844 struct device_node *np = pdev->dev.of_node;
845 struct abx500_pinctrl *pct;
846 const struct platform_device_id *platid = platform_get_device_id(pdev);
847 unsigned int id = -1;
852 pdata = abx500_pdata->gpio;
854 if (!(pdata || np)) {
855 dev_err(&pdev->dev, "gpio dt and platform data missing\n");
859 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
863 "failed to allocate memory for pct\n");
867 pct->dev = &pdev->dev;
868 pct->parent = dev_get_drvdata(pdev->dev.parent);
869 pct->chip = abx500gpio_chip;
870 pct->chip.dev = &pdev->dev;
871 pct->chip.base = (np) ? -1 : pdata->gpio_base;
874 id = platid->driver_data;
876 const struct of_device_id *match;
878 match = of_match_device(abx500_gpio_match, &pdev->dev);
880 id = (unsigned long)match->data;
883 /* Poke in other ASIC variants here */
886 abx500_pinctrl_ab8500_init(&pct->soc);
889 abx500_pinctrl_ab8540_init(&pct->soc);
892 abx500_pinctrl_ab9540_init(&pct->soc);
895 abx500_pinctrl_ab8505_init(&pct->soc);
898 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
903 dev_err(&pdev->dev, "Invalid SOC data\n");
907 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
908 pct->irq_cluster = pct->soc->gpio_irq_cluster;
909 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
911 ret = gpiochip_add(&pct->chip);
913 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
916 dev_info(&pdev->dev, "added gpiochip\n");
918 abx500_pinctrl_desc.pins = pct->soc->pins;
919 abx500_pinctrl_desc.npins = pct->soc->npins;
920 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
923 "could not register abx500 pinctrl driver\n");
927 dev_info(&pdev->dev, "registered pin controller\n");
929 /* We will handle a range of GPIO pins */
930 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
931 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
933 ret = gpiochip_add_pin_range(&pct->chip,
934 dev_name(&pdev->dev),
935 p->offset - 1, p->offset, p->npins);
940 platform_set_drvdata(pdev, pct);
941 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
946 err = gpiochip_remove(&pct->chip);
948 dev_info(&pdev->dev, "failed to remove gpiochip\n");
954 * abx500_gpio_remove() - remove Ab8500-gpio driver
955 * @pdev: Platform device registered
957 static int abx500_gpio_remove(struct platform_device *pdev)
959 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
962 ret = gpiochip_remove(&pct->chip);
964 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
972 static const struct platform_device_id abx500_pinctrl_id[] = {
973 { "pinctrl-ab8500", PINCTRL_AB8500 },
974 { "pinctrl-ab8540", PINCTRL_AB8540 },
975 { "pinctrl-ab9540", PINCTRL_AB9540 },
976 { "pinctrl-ab8505", PINCTRL_AB8505 },
980 static struct platform_driver abx500_gpio_driver = {
982 .name = "abx500-gpio",
983 .owner = THIS_MODULE,
984 .of_match_table = abx500_gpio_match,
986 .probe = abx500_gpio_probe,
987 .remove = abx500_gpio_remove,
988 .id_table = abx500_pinctrl_id,
991 static int __init abx500_gpio_init(void)
993 return platform_driver_register(&abx500_gpio_driver);
995 core_initcall(abx500_gpio_init);
997 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
998 MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
999 MODULE_ALIAS("platform:abx500-gpio");
1000 MODULE_LICENSE("GPL v2");