2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/gpio.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/bitops.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <dt-bindings/pinctrl/mt65xx.h>
39 #include "../pinconf.h"
40 #include "../pinctrl-utils.h"
41 #include "pinctrl-mtk-common.h"
43 #define MAX_GPIO_MODE_PER_REG 5
44 #define GPIO_MODE_BITS 3
46 static const char * const mtk_gpio_functions[] = {
47 "func0", "func1", "func2", "func3",
48 "func4", "func5", "func6", "func7",
52 * There are two base address for pull related configuration
53 * in mt8135, and different GPIO pins use different base address.
54 * When pin number greater than type1_start and less than type1_end,
55 * should use the second base address.
57 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
60 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
65 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
67 /* Different SoC has different mask and port shift. */
68 return ((pin >> 4) & pctl->devdata->port_mask)
69 << pctl->devdata->port_shf;
72 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
73 struct pinctrl_gpio_range *range, unsigned offset,
76 unsigned int reg_addr;
78 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
80 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
81 bit = BIT(offset & 0xf);
84 /* Different SoC has different alignment offset. */
85 reg_addr = CLR_ADDR(reg_addr, pctl);
87 reg_addr = SET_ADDR(reg_addr, pctl);
89 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
93 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
95 unsigned int reg_addr;
97 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
99 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
100 bit = BIT(offset & 0xf);
103 reg_addr = SET_ADDR(reg_addr, pctl);
105 reg_addr = CLR_ADDR(reg_addr, pctl);
107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
110 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
111 int value, enum pin_config_param arg)
113 unsigned int reg_addr, offset;
117 * Due to some soc are not support ies/smt config, add this special
118 * control to handle it.
120 if (!pctl->devdata->spec_ies_smt_set &&
121 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
122 arg == PIN_CONFIG_INPUT_ENABLE)
125 if (!pctl->devdata->spec_ies_smt_set &&
126 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
127 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
131 * Due to some pins are irregular, their input enable and smt
132 * control register are discontinuous, so we need this special handle.
134 if (pctl->devdata->spec_ies_smt_set) {
135 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
136 pin, pctl->devdata->port_align, value, arg);
139 bit = BIT(pin & 0xf);
141 if (arg == PIN_CONFIG_INPUT_ENABLE)
142 offset = pctl->devdata->ies_offset;
144 offset = pctl->devdata->smt_offset;
147 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
149 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
151 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
155 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
156 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
157 unsigned int pin, unsigned char align, int value)
159 unsigned int i, reg_addr, bit;
161 for (i = 0; i < info_num; i++) {
162 if (pin >= ies_smt_infos[i].start &&
163 pin <= ies_smt_infos[i].end) {
172 reg_addr = ies_smt_infos[i].offset + align;
174 reg_addr = ies_smt_infos[i].offset + (align << 1);
176 bit = BIT(ies_smt_infos[i].bit);
177 regmap_write(regmap, reg_addr, bit);
181 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
182 struct mtk_pinctrl *pctl, unsigned long pin) {
185 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
186 const struct mtk_pin_drv_grp *pin_drv =
187 pctl->devdata->pin_drv_grp + i;
188 if (pin == pin_drv->pin)
195 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
196 unsigned int pin, unsigned char driving)
198 const struct mtk_pin_drv_grp *pin_drv;
200 unsigned int bits, mask, shift;
201 const struct mtk_drv_group_desc *drv_grp;
203 if (pin >= pctl->devdata->npins)
206 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
207 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
210 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
211 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
212 && !(driving % drv_grp->step)) {
213 val = driving / drv_grp->step - 1;
214 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
215 mask = BIT(bits) - 1;
216 shift = pin_drv->bit + drv_grp->low_bit;
219 return regmap_update_bits(mtk_get_regmap(pctl, pin),
220 pin_drv->offset, mask, val);
226 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
227 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
228 unsigned int info_num, unsigned int pin,
229 unsigned char align, bool isup, unsigned int r1r0)
232 unsigned int reg_pupd, reg_set, reg_rst;
233 unsigned int bit_pupd, bit_r0, bit_r1;
234 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
237 for (i = 0; i < info_num; i++) {
238 if (pin == pupd_infos[i].pin) {
247 spec_pupd_pin = pupd_infos + i;
248 reg_set = spec_pupd_pin->offset + align;
249 reg_rst = spec_pupd_pin->offset + (align << 1);
256 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
257 regmap_write(regmap, reg_pupd, bit_pupd);
259 bit_r0 = BIT(spec_pupd_pin->r0_bit);
260 bit_r1 = BIT(spec_pupd_pin->r1_bit);
263 case MTK_PUPD_SET_R1R0_00:
264 regmap_write(regmap, reg_rst, bit_r0);
265 regmap_write(regmap, reg_rst, bit_r1);
267 case MTK_PUPD_SET_R1R0_01:
268 regmap_write(regmap, reg_set, bit_r0);
269 regmap_write(regmap, reg_rst, bit_r1);
271 case MTK_PUPD_SET_R1R0_10:
272 regmap_write(regmap, reg_rst, bit_r0);
273 regmap_write(regmap, reg_set, bit_r1);
275 case MTK_PUPD_SET_R1R0_11:
276 regmap_write(regmap, reg_set, bit_r0);
277 regmap_write(regmap, reg_set, bit_r1);
286 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
287 unsigned int pin, bool enable, bool isup, unsigned int arg)
290 unsigned int reg_pullen, reg_pullsel;
293 /* Some pins' pull setting are very different,
294 * they have separate pull up/down bit, R0 and R1
295 * resistor bit, so we need this special handle.
297 if (pctl->devdata->spec_pull_set) {
298 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
299 pin, pctl->devdata->port_align, isup, arg);
304 /* For generic pull config, default arg value should be 0 or 1. */
305 if (arg != 0 && arg != 1) {
306 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
311 bit = BIT(pin & 0xf);
313 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
314 pctl->devdata->pullen_offset, pctl);
316 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
317 pctl->devdata->pullen_offset, pctl);
320 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
321 pctl->devdata->pullsel_offset, pctl);
323 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
324 pctl->devdata->pullsel_offset, pctl);
326 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
331 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
332 unsigned int pin, enum pin_config_param param,
333 enum pin_config_param arg)
336 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
339 case PIN_CONFIG_BIAS_DISABLE:
340 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
342 case PIN_CONFIG_BIAS_PULL_UP:
343 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
345 case PIN_CONFIG_BIAS_PULL_DOWN:
346 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
348 case PIN_CONFIG_INPUT_ENABLE:
349 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
351 case PIN_CONFIG_OUTPUT:
352 mtk_gpio_set(pctl->chip, pin, arg);
353 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
355 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
356 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
358 case PIN_CONFIG_DRIVE_STRENGTH:
359 ret = mtk_pconf_set_driving(pctl, pin, arg);
368 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
370 unsigned long *config)
372 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
374 *config = pctl->groups[group].config;
379 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
380 unsigned long *configs, unsigned num_configs)
382 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
383 struct mtk_pinctrl_group *g = &pctl->groups[group];
386 for (i = 0; i < num_configs; i++) {
387 ret = mtk_pconf_parse_conf(pctldev, g->pin,
388 pinconf_to_config_param(configs[i]),
389 pinconf_to_config_argument(configs[i]));
393 g->config = configs[i];
399 static const struct pinconf_ops mtk_pconf_ops = {
400 .pin_config_group_get = mtk_pconf_group_get,
401 .pin_config_group_set = mtk_pconf_group_set,
404 static struct mtk_pinctrl_group *
405 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
409 for (i = 0; i < pctl->ngroups; i++) {
410 struct mtk_pinctrl_group *grp = pctl->groups + i;
419 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
420 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
422 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
423 const struct mtk_desc_function *func = pin->functions;
425 while (func && func->name) {
426 if (func->muxval == fnum)
434 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
435 u32 pin_num, u32 fnum)
439 for (i = 0; i < pctl->devdata->npins; i++) {
440 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
442 if (pin->pin.number == pin_num) {
443 const struct mtk_desc_function *func =
446 while (func && func->name) {
447 if (func->muxval == fnum)
459 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
460 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
461 struct pinctrl_map **map, unsigned *reserved_maps,
466 if (*num_maps == *reserved_maps)
469 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
470 (*map)[*num_maps].data.mux.group = grp->name;
472 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
474 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
479 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
485 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
486 struct device_node *node,
487 struct pinctrl_map **map,
488 unsigned *reserved_maps,
491 struct property *pins;
492 u32 pinfunc, pin, func;
493 int num_pins, num_funcs, maps_per_pin;
494 unsigned long *configs;
495 unsigned int num_configs;
498 unsigned reserve = 0;
499 struct mtk_pinctrl_group *grp;
500 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
502 pins = of_find_property(node, "pinmux", NULL);
504 dev_err(pctl->dev, "missing pins property in node %s .\n",
509 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
514 num_pins = pins->length / sizeof(u32);
515 num_funcs = num_pins;
519 if (has_config && num_pins >= 1)
522 if (!num_pins || !maps_per_pin)
525 reserve = num_pins * maps_per_pin;
527 err = pinctrl_utils_reserve_map(pctldev, map,
528 reserved_maps, num_maps, reserve);
532 for (i = 0; i < num_pins; i++) {
533 err = of_property_read_u32_index(node, "pinmux",
538 pin = MTK_GET_PIN_NO(pinfunc);
539 func = MTK_GET_PIN_FUNC(pinfunc);
541 if (pin >= pctl->devdata->npins ||
542 func >= ARRAY_SIZE(mtk_gpio_functions)) {
543 dev_err(pctl->dev, "invalid pins value.\n");
548 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
550 dev_err(pctl->dev, "unable to match pin %d to group\n",
555 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
556 reserved_maps, num_maps);
561 err = pinctrl_utils_add_map_configs(pctldev, map,
562 reserved_maps, num_maps, grp->name,
563 configs, num_configs,
564 PIN_MAP_TYPE_CONFIGS_GROUP);
576 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
577 struct device_node *np_config,
578 struct pinctrl_map **map, unsigned *num_maps)
580 struct device_node *np;
581 unsigned reserved_maps;
588 for_each_child_of_node(np_config, np) {
589 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
590 &reserved_maps, num_maps);
592 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
600 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
602 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
604 return pctl->ngroups;
607 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
610 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
612 return pctl->groups[group].name;
615 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
617 const unsigned **pins,
620 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
622 *pins = (unsigned *)&pctl->groups[group].pin;
628 static const struct pinctrl_ops mtk_pctrl_ops = {
629 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
630 .dt_free_map = pinctrl_utils_dt_free_map,
631 .get_groups_count = mtk_pctrl_get_groups_count,
632 .get_group_name = mtk_pctrl_get_group_name,
633 .get_group_pins = mtk_pctrl_get_group_pins,
636 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
638 return ARRAY_SIZE(mtk_gpio_functions);
641 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
644 return mtk_gpio_functions[selector];
647 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
649 const char * const **groups,
650 unsigned * const num_groups)
652 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
654 *groups = pctl->grp_names;
655 *num_groups = pctl->ngroups;
660 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
661 unsigned long pin, unsigned long mode)
663 unsigned int reg_addr;
666 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
667 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
669 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
670 + pctl->devdata->pinmux_offset;
672 bit = pin % MAX_GPIO_MODE_PER_REG;
673 mask <<= (GPIO_MODE_BITS * bit);
674 val = (mode << (GPIO_MODE_BITS * bit));
675 return regmap_update_bits(mtk_get_regmap(pctl, pin),
676 reg_addr, mask, val);
679 static const struct mtk_desc_pin *
680 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
683 const struct mtk_desc_pin *pin;
685 for (i = 0; i < pctl->devdata->npins; i++) {
686 pin = pctl->devdata->pins + i;
687 if (pin->eint.eintnum == eint_num)
694 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
699 const struct mtk_desc_function *desc;
700 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
701 struct mtk_pinctrl_group *g = pctl->groups + group;
703 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
705 dev_err(pctl->dev, "invaild function %d on group %d .\n",
710 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
713 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
717 static const struct pinmux_ops mtk_pmx_ops = {
718 .get_functions_count = mtk_pmx_get_funcs_cnt,
719 .get_function_name = mtk_pmx_get_func_name,
720 .get_function_groups = mtk_pmx_get_func_groups,
721 .set_mux = mtk_pmx_set_mux,
722 .gpio_set_direction = mtk_pmx_gpio_set_direction,
725 static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
727 return pinctrl_request_gpio(chip->base + offset);
730 static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
732 pinctrl_free_gpio(chip->base + offset);
735 static int mtk_gpio_direction_input(struct gpio_chip *chip,
738 return pinctrl_gpio_direction_input(chip->base + offset);
741 static int mtk_gpio_direction_output(struct gpio_chip *chip,
742 unsigned offset, int value)
744 mtk_gpio_set(chip, offset, value);
745 return pinctrl_gpio_direction_output(chip->base + offset);
748 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
750 unsigned int reg_addr;
752 unsigned int read_val = 0;
754 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
756 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
757 bit = BIT(offset & 0xf);
758 regmap_read(pctl->regmap1, reg_addr, &read_val);
759 return !!(read_val & bit);
762 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
764 unsigned int reg_addr;
766 unsigned int read_val = 0;
767 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
769 if (mtk_gpio_get_direction(chip, offset))
770 reg_addr = mtk_get_port(pctl, offset) +
771 pctl->devdata->dout_offset;
773 reg_addr = mtk_get_port(pctl, offset) +
774 pctl->devdata->din_offset;
776 bit = BIT(offset & 0xf);
777 regmap_read(pctl->regmap1, reg_addr, &read_val);
778 return !!(read_val & bit);
781 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
783 const struct mtk_desc_pin *pin;
784 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
787 pin = pctl->devdata->pins + offset;
788 if (pin->eint.eintnum == NO_EINT_SUPPORT)
791 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
798 static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
800 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
801 const struct mtk_desc_pin *pin;
804 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
807 dev_err(pctl->dev, "Can not find pin\n");
811 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
813 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
818 /* set mux to INT mode */
819 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
824 static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
826 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
827 const struct mtk_desc_pin *pin;
829 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
832 dev_err(pctl->dev, "Can not find pin\n");
836 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
839 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
840 unsigned int eint_num, unsigned int offset)
842 unsigned int eint_base = 0;
845 if (eint_num >= pctl->devdata->ap_num)
846 eint_base = pctl->devdata->ap_num;
848 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
854 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
855 * @eint_num: the EINT number to setmtk_pinctrl
857 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
858 unsigned int eint_num)
861 unsigned int bit = BIT(eint_num % 32);
862 const struct mtk_eint_offsets *eint_offsets =
863 &pctl->devdata->eint_offsets;
865 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
868 if (readl(reg) & bit)
869 sens = MT_LEVEL_SENSITIVE;
871 sens = MT_EDGE_SENSITIVE;
873 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
880 * mtk_eint_get_mask: To get the eint mask
881 * @eint_num: the EINT number to get
883 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
884 unsigned int eint_num)
886 unsigned int bit = BIT(eint_num % 32);
887 const struct mtk_eint_offsets *eint_offsets =
888 &pctl->devdata->eint_offsets;
890 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
893 return !!(readl(reg) & bit);
896 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
898 int start_level, curr_level;
899 unsigned int reg_offset;
900 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
901 u32 mask = 1 << (hwirq & 0x1f);
902 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
903 void __iomem *reg = pctl->eint_reg_base + (port << 2);
904 const struct mtk_desc_pin *pin;
906 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
907 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
909 start_level = curr_level;
911 reg_offset = eint_offsets->pol_clr;
913 reg_offset = eint_offsets->pol_set;
914 writel(mask, reg + reg_offset);
916 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
917 } while (start_level != curr_level);
922 static void mtk_eint_mask(struct irq_data *d)
924 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
925 const struct mtk_eint_offsets *eint_offsets =
926 &pctl->devdata->eint_offsets;
927 u32 mask = BIT(d->hwirq & 0x1f);
928 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
929 eint_offsets->mask_set);
934 static void mtk_eint_unmask(struct irq_data *d)
936 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
937 const struct mtk_eint_offsets *eint_offsets =
938 &pctl->devdata->eint_offsets;
939 u32 mask = BIT(d->hwirq & 0x1f);
940 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
941 eint_offsets->mask_clr);
945 if (pctl->eint_dual_edges[d->hwirq])
946 mtk_eint_flip_edge(pctl, d->hwirq);
949 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
952 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
953 int eint_num, virq, eint_offset;
954 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
955 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
956 const struct mtk_desc_pin *pin;
959 pin = pctl->devdata->pins + offset;
960 if (pin->eint.eintnum == NO_EINT_SUPPORT)
963 eint_num = pin->eint.eintnum;
964 virq = irq_find_mapping(pctl->domain, eint_num);
965 eint_offset = (eint_num % 4) * 8;
966 d = irq_get_irq_data(virq);
968 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
969 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
970 if (!mtk_eint_can_en_debounce(pctl, eint_num))
973 dbnc = ARRAY_SIZE(dbnc_arr);
974 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
975 if (debounce <= dbnc_arr[i]) {
981 if (!mtk_eint_get_mask(pctl, eint_num)) {
988 clr_bit = 0xff << eint_offset;
989 writel(clr_bit, pctl->eint_reg_base + clr_offset);
991 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
993 rst = EINT_DBNC_RST_BIT << eint_offset;
994 writel(rst | bit, pctl->eint_reg_base + set_offset);
996 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1005 static struct gpio_chip mtk_gpio_chip = {
1006 .owner = THIS_MODULE,
1007 .request = mtk_gpio_request,
1008 .free = mtk_gpio_free,
1009 .direction_input = mtk_gpio_direction_input,
1010 .direction_output = mtk_gpio_direction_output,
1011 .get = mtk_gpio_get,
1012 .set = mtk_gpio_set,
1013 .to_irq = mtk_gpio_to_irq,
1014 .set_debounce = mtk_gpio_set_debounce,
1015 .of_gpio_n_cells = 2,
1018 static int mtk_eint_set_type(struct irq_data *d,
1021 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1022 const struct mtk_eint_offsets *eint_offsets =
1023 &pctl->devdata->eint_offsets;
1024 u32 mask = BIT(d->hwirq & 0x1f);
1027 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
1028 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1029 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1030 d->irq, d->hwirq, type);
1034 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1035 pctl->eint_dual_edges[d->hwirq] = 1;
1037 pctl->eint_dual_edges[d->hwirq] = 0;
1039 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1040 reg = mtk_eint_get_offset(pctl, d->hwirq,
1041 eint_offsets->pol_clr);
1044 reg = mtk_eint_get_offset(pctl, d->hwirq,
1045 eint_offsets->pol_set);
1049 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1050 reg = mtk_eint_get_offset(pctl, d->hwirq,
1051 eint_offsets->sens_clr);
1054 reg = mtk_eint_get_offset(pctl, d->hwirq,
1055 eint_offsets->sens_set);
1059 if (pctl->eint_dual_edges[d->hwirq])
1060 mtk_eint_flip_edge(pctl, d->hwirq);
1065 static void mtk_eint_ack(struct irq_data *d)
1067 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1068 const struct mtk_eint_offsets *eint_offsets =
1069 &pctl->devdata->eint_offsets;
1070 u32 mask = BIT(d->hwirq & 0x1f);
1071 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1077 static struct irq_chip mtk_pinctrl_irq_chip = {
1079 .irq_mask = mtk_eint_mask,
1080 .irq_unmask = mtk_eint_unmask,
1081 .irq_ack = mtk_eint_ack,
1082 .irq_set_type = mtk_eint_set_type,
1083 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1084 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1087 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1089 const struct mtk_eint_offsets *eint_offsets =
1090 &pctl->devdata->eint_offsets;
1091 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1094 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1095 writel(0xffffffff, reg);
1102 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1104 unsigned int rst, ctrl_offset;
1105 unsigned int bit, dbnc;
1106 const struct mtk_eint_offsets *eint_offsets =
1107 &pctl->devdata->eint_offsets;
1109 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1110 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1111 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1112 if ((bit & dbnc) > 0) {
1113 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1114 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1115 writel(rst, pctl->eint_reg_base + ctrl_offset);
1119 static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
1121 struct irq_chip *chip = irq_get_chip(irq);
1122 struct mtk_pinctrl *pctl = irq_get_handler_data(irq);
1123 unsigned int status, eint_num;
1124 int offset, index, virq;
1125 const struct mtk_eint_offsets *eint_offsets =
1126 &pctl->devdata->eint_offsets;
1127 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1128 int dual_edges, start_level, curr_level;
1129 const struct mtk_desc_pin *pin;
1131 chained_irq_enter(chip, desc);
1132 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1133 status = readl(reg);
1136 offset = __ffs(status);
1137 index = eint_num + offset;
1138 virq = irq_find_mapping(pctl->domain, index);
1139 status &= ~BIT(offset);
1141 dual_edges = pctl->eint_dual_edges[index];
1143 /* Clear soft-irq in case we raised it
1145 writel(BIT(offset), reg - eint_offsets->stat +
1146 eint_offsets->soft_clr);
1148 pin = mtk_find_pin_by_eint_num(pctl, index);
1149 start_level = mtk_gpio_get(pctl->chip,
1153 generic_handle_irq(virq);
1156 curr_level = mtk_eint_flip_edge(pctl, index);
1158 /* If level changed, we might lost one edge
1159 interrupt, raised it through soft-irq */
1160 if (start_level != curr_level)
1161 writel(BIT(offset), reg -
1162 eint_offsets->stat +
1163 eint_offsets->soft_set);
1166 if (index < pctl->devdata->db_cnt)
1167 mtk_eint_debounce_process(pctl , index);
1170 chained_irq_exit(chip, desc);
1173 static int mtk_pctrl_build_state(struct platform_device *pdev)
1175 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1178 pctl->ngroups = pctl->devdata->npins;
1180 /* Allocate groups */
1181 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1182 sizeof(*pctl->groups), GFP_KERNEL);
1186 /* We assume that one pin is one group, use pin name as group name. */
1187 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1188 sizeof(*pctl->grp_names), GFP_KERNEL);
1189 if (!pctl->grp_names)
1192 for (i = 0; i < pctl->devdata->npins; i++) {
1193 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1194 struct mtk_pinctrl_group *group = pctl->groups + i;
1196 group->name = pin->pin.name;
1197 group->pin = pin->pin.number;
1199 pctl->grp_names[i] = pin->pin.name;
1205 static struct pinctrl_desc mtk_pctrl_desc = {
1206 .confops = &mtk_pconf_ops,
1207 .pctlops = &mtk_pctrl_ops,
1208 .pmxops = &mtk_pmx_ops,
1211 int mtk_pctrl_init(struct platform_device *pdev,
1212 const struct mtk_pinctrl_devdata *data,
1213 struct regmap *regmap)
1215 struct pinctrl_pin_desc *pins;
1216 struct mtk_pinctrl *pctl;
1217 struct device_node *np = pdev->dev.of_node, *node;
1218 struct property *prop;
1219 struct resource *res;
1222 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1226 platform_set_drvdata(pdev, pctl);
1228 prop = of_find_property(np, "pins-are-numbered", NULL);
1230 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1234 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1236 pctl->regmap1 = syscon_node_to_regmap(node);
1237 if (IS_ERR(pctl->regmap1))
1238 return PTR_ERR(pctl->regmap1);
1239 } else if (regmap) {
1240 pctl->regmap1 = regmap;
1242 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1246 /* Only 8135 has two base addr, other SoCs have only one. */
1247 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1249 pctl->regmap2 = syscon_node_to_regmap(node);
1250 if (IS_ERR(pctl->regmap2))
1251 return PTR_ERR(pctl->regmap2);
1254 pctl->devdata = data;
1255 ret = mtk_pctrl_build_state(pdev);
1257 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1261 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1266 for (i = 0; i < pctl->devdata->npins; i++)
1267 pins[i] = pctl->devdata->pins[i].pin;
1268 mtk_pctrl_desc.name = dev_name(&pdev->dev);
1269 mtk_pctrl_desc.owner = THIS_MODULE;
1270 mtk_pctrl_desc.pins = pins;
1271 mtk_pctrl_desc.npins = pctl->devdata->npins;
1272 pctl->dev = &pdev->dev;
1273 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
1274 if (IS_ERR(pctl->pctl_dev)) {
1275 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1276 return PTR_ERR(pctl->pctl_dev);
1279 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1285 *pctl->chip = mtk_gpio_chip;
1286 pctl->chip->ngpio = pctl->devdata->npins;
1287 pctl->chip->label = dev_name(&pdev->dev);
1288 pctl->chip->dev = &pdev->dev;
1289 pctl->chip->base = -1;
1291 ret = gpiochip_add(pctl->chip);
1297 /* Register the GPIO to pin mappings. */
1298 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1299 0, 0, pctl->devdata->npins);
1305 if (!of_property_read_bool(np, "interrupt-controller"))
1308 /* Get EINT register base from dts. */
1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1311 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1316 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1317 if (IS_ERR(pctl->eint_reg_base)) {
1322 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1323 sizeof(int), GFP_KERNEL);
1324 if (!pctl->eint_dual_edges) {
1329 irq = irq_of_parse_and_map(np, 0);
1331 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1336 pctl->domain = irq_domain_add_linear(np,
1337 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1338 if (!pctl->domain) {
1339 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1344 mtk_eint_init(pctl);
1345 for (i = 0; i < pctl->devdata->ap_num; i++) {
1346 int virq = irq_create_mapping(pctl->domain, i);
1348 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1350 irq_set_chip_data(virq, pctl);
1351 set_irq_flags(virq, IRQF_VALID);
1354 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1355 set_irq_flags(irq, IRQF_VALID);
1359 gpiochip_remove(pctl->chip);
1361 pinctrl_unregister(pctl->pctl_dev);
1365 MODULE_LICENSE("GPL");
1366 MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1367 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");