2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/types.h>
21 #include <linux/bitops.h>
22 #include <linux/interrupt.h>
23 #include <linux/gpio.h>
24 #include <linux/acpi.h>
25 #include <linux/platform_device.h>
26 #include <linux/seq_file.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pinctrl/pinctrl.h>
31 /* memory mapped register offsets */
32 #define BYT_CONF0_REG 0x000
33 #define BYT_CONF1_REG 0x004
34 #define BYT_VAL_REG 0x008
35 #define BYT_DFT_REG 0x00c
36 #define BYT_INT_STAT_REG 0x800
38 /* BYT_CONF0_REG register bits */
39 #define BYT_IODEN BIT(31)
40 #define BYT_DIRECT_IRQ_EN BIT(27)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_PULL_STR_SHIFT 9
45 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
46 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
47 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
48 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
49 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
50 #define BYT_PULL_ASSIGN_SHIFT 7
51 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
52 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
53 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
54 #define BYT_PIN_MUX 0x07
56 /* BYT_VAL_REG register bits */
57 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
58 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
59 #define BYT_LEVEL BIT(0)
61 #define BYT_DIR_MASK (BIT(1) | BIT(2))
62 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
64 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
66 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68 #define BYT_NGPIO_SCORE 102
69 #define BYT_NGPIO_NCORE 28
70 #define BYT_NGPIO_SUS 44
72 #define BYT_SCORE_ACPI_UID "1"
73 #define BYT_NCORE_ACPI_UID "2"
74 #define BYT_SUS_ACPI_UID "3"
77 * Baytrail gpio controller consist of three separate sub-controllers called
78 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
80 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
81 * _not_ correspond to the first gpio register at controller's gpio base.
82 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
83 * each sub-controller needs to have its own mapping table
86 /* score_pins[gpio_nr] = pad_nr */
88 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
89 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
90 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
91 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
92 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
93 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
94 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
95 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
96 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
97 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
98 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
102 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
103 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
104 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
105 3, 6, 10, 13, 2, 5, 9, 7,
108 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
109 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
110 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
111 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
112 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
116 static struct pinctrl_gpio_range byt_ranges[] = {
118 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
119 .npins = BYT_NGPIO_SCORE,
123 .name = BYT_NCORE_ACPI_UID,
124 .npins = BYT_NGPIO_NCORE,
128 .name = BYT_SUS_ACPI_UID,
129 .npins = BYT_NGPIO_SUS,
136 struct byt_gpio_pin_context {
142 struct gpio_chip chip;
143 struct platform_device *pdev;
145 void __iomem *reg_base;
146 struct pinctrl_gpio_range *range;
147 struct byt_gpio_pin_context *saved_context;
150 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
152 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
155 struct byt_gpio *vg = to_byt_gpio(chip);
158 if (reg == BYT_INT_STAT_REG)
159 reg_offset = (offset / 32) * 4;
161 reg_offset = vg->range->pins[offset] * 16;
163 return vg->reg_base + reg_offset + reg;
166 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
168 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
172 spin_lock_irqsave(&vg->lock, flags);
174 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
176 spin_unlock_irqrestore(&vg->lock, flags);
179 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
181 /* SCORE pin 92-93 */
182 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
183 offset >= 92 && offset <= 93)
187 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
188 offset >= 11 && offset <= 21)
194 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
196 struct byt_gpio *vg = to_byt_gpio(chip);
197 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
201 * In most cases, func pin mux 000 means GPIO function.
202 * But, some pins may have func pin mux 001 represents
205 * Because there are devices out there where some pins were not
206 * configured correctly we allow changing the mux value from
207 * request (but print out warning about that).
209 value = readl(reg) & BYT_PIN_MUX;
210 gpio_mux = byt_get_gpio_mux(vg, offset);
211 if (WARN_ON(gpio_mux != value)) {
214 spin_lock_irqsave(&vg->lock, flags);
215 value = readl(reg) & ~BYT_PIN_MUX;
218 spin_unlock_irqrestore(&vg->lock, flags);
220 dev_warn(&vg->pdev->dev,
221 "pin %u forcibly re-configured as GPIO\n", offset);
224 pm_runtime_get(&vg->pdev->dev);
229 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
231 struct byt_gpio *vg = to_byt_gpio(chip);
233 byt_gpio_clear_triggering(vg, offset);
234 pm_runtime_put(&vg->pdev->dev);
237 static int byt_irq_type(struct irq_data *d, unsigned type)
239 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
240 u32 offset = irqd_to_hwirq(d);
243 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
245 if (offset >= vg->chip.ngpio)
248 spin_lock_irqsave(&vg->lock, flags);
251 WARN(value & BYT_DIRECT_IRQ_EN,
252 "Bad pad config for io mode, force direct_irq_en bit clearing");
254 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
255 * are used to indicate high and low level triggering
257 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
262 if (type & IRQ_TYPE_EDGE_BOTH)
263 irq_set_handler_locked(d, handle_edge_irq);
264 else if (type & IRQ_TYPE_LEVEL_MASK)
265 irq_set_handler_locked(d, handle_level_irq);
267 spin_unlock_irqrestore(&vg->lock, flags);
272 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
274 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
275 return readl(reg) & BYT_LEVEL;
278 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
280 struct byt_gpio *vg = to_byt_gpio(chip);
281 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
285 spin_lock_irqsave(&vg->lock, flags);
287 old_val = readl(reg);
290 writel(old_val | BYT_LEVEL, reg);
292 writel(old_val & ~BYT_LEVEL, reg);
294 spin_unlock_irqrestore(&vg->lock, flags);
297 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
299 struct byt_gpio *vg = to_byt_gpio(chip);
300 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
304 spin_lock_irqsave(&vg->lock, flags);
306 value = readl(reg) | BYT_DIR_MASK;
307 value &= ~BYT_INPUT_EN; /* active low */
310 spin_unlock_irqrestore(&vg->lock, flags);
315 static int byt_gpio_direction_output(struct gpio_chip *chip,
316 unsigned gpio, int value)
318 struct byt_gpio *vg = to_byt_gpio(chip);
319 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
320 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
324 spin_lock_irqsave(&vg->lock, flags);
327 * Before making any direction modifications, do a check if gpio
328 * is set for direct IRQ. On baytrail, setting GPIO to output does
329 * not make sense, so let's at least warn the caller before they shoot
330 * themselves in the foot.
332 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
333 "Potential Error: Setting GPIO with direct_irq_en to output");
335 reg_val = readl(reg) | BYT_DIR_MASK;
336 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
339 writel(reg_val | BYT_LEVEL, reg);
341 writel(reg_val & ~BYT_LEVEL, reg);
343 spin_unlock_irqrestore(&vg->lock, flags);
348 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
350 struct byt_gpio *vg = to_byt_gpio(chip);
353 u32 conf0, val, offs;
355 spin_lock_irqsave(&vg->lock, flags);
357 for (i = 0; i < vg->chip.ngpio; i++) {
358 const char *pull_str = NULL;
359 const char *pull = NULL;
361 offs = vg->range->pins[i] * 16;
362 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
363 val = readl(vg->reg_base + offs + BYT_VAL_REG);
365 label = gpiochip_is_requested(chip, i);
367 label = "Unrequested";
369 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
370 case BYT_PULL_ASSIGN_UP:
373 case BYT_PULL_ASSIGN_DOWN:
378 switch (conf0 & BYT_PULL_STR_MASK) {
379 case BYT_PULL_STR_2K:
382 case BYT_PULL_STR_10K:
385 case BYT_PULL_STR_20K:
388 case BYT_PULL_STR_40K:
394 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
397 val & BYT_INPUT_EN ? " " : "in",
398 val & BYT_OUTPUT_EN ? " " : "out",
399 val & BYT_LEVEL ? "hi" : "lo",
400 vg->range->pins[i], offs,
402 conf0 & BYT_TRIG_NEG ? " fall" : " ",
403 conf0 & BYT_TRIG_POS ? " rise" : " ",
404 conf0 & BYT_TRIG_LVL ? " level" : " ");
406 if (pull && pull_str)
407 seq_printf(s, " %-4s %-3s", pull, pull_str);
411 if (conf0 & BYT_IODEN)
412 seq_puts(s, " open-drain");
416 spin_unlock_irqrestore(&vg->lock, flags);
419 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
421 struct irq_data *data = irq_desc_get_irq_data(desc);
422 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
423 struct irq_chip *chip = irq_data_get_irq_chip(data);
426 unsigned long pending;
429 /* check from GPIO controller which pin triggered the interrupt */
430 for (base = 0; base < vg->chip.ngpio; base += 32) {
431 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
432 pending = readl(reg);
433 for_each_set_bit(pin, &pending, 32) {
434 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
435 generic_handle_irq(virq);
441 static void byt_irq_ack(struct irq_data *d)
443 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
444 struct byt_gpio *vg = to_byt_gpio(gc);
445 unsigned offset = irqd_to_hwirq(d);
448 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
449 writel(BIT(offset % 32), reg);
452 static void byt_irq_unmask(struct irq_data *d)
454 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
455 struct byt_gpio *vg = to_byt_gpio(gc);
456 unsigned offset = irqd_to_hwirq(d);
461 spin_lock_irqsave(&vg->lock, flags);
463 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
466 switch (irqd_get_trigger_type(d)) {
467 case IRQ_TYPE_LEVEL_HIGH:
468 value |= BYT_TRIG_LVL;
469 case IRQ_TYPE_EDGE_RISING:
470 value |= BYT_TRIG_POS;
472 case IRQ_TYPE_LEVEL_LOW:
473 value |= BYT_TRIG_LVL;
474 case IRQ_TYPE_EDGE_FALLING:
475 value |= BYT_TRIG_NEG;
477 case IRQ_TYPE_EDGE_BOTH:
478 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
484 spin_unlock_irqrestore(&vg->lock, flags);
487 static void byt_irq_mask(struct irq_data *d)
489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
490 struct byt_gpio *vg = to_byt_gpio(gc);
492 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
495 static struct irq_chip byt_irqchip = {
497 .irq_ack = byt_irq_ack,
498 .irq_mask = byt_irq_mask,
499 .irq_unmask = byt_irq_unmask,
500 .irq_set_type = byt_irq_type,
501 .flags = IRQCHIP_SKIP_SET_WAKE,
504 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
511 * Clear interrupt triggers for all pins that are GPIOs and
512 * do not use direct IRQ mode. This will prevent spurious
513 * interrupts from misconfigured pins.
515 for (i = 0; i < vg->chip.ngpio; i++) {
516 value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
517 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
518 !(value & BYT_DIRECT_IRQ_EN)) {
519 byt_gpio_clear_triggering(vg, i);
520 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
524 /* clear interrupt status trigger registers */
525 for (base = 0; base < vg->chip.ngpio; base += 32) {
526 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
527 writel(0xffffffff, reg);
528 /* make sure trigger bits are cleared, if not then a pin
529 might be misconfigured in bios */
532 dev_err(&vg->pdev->dev,
533 "GPIO interrupt error, pins misconfigured\n");
537 static int byt_gpio_probe(struct platform_device *pdev)
540 struct gpio_chip *gc;
541 struct resource *mem_rc, *irq_rc;
542 struct device *dev = &pdev->dev;
543 struct acpi_device *acpi_dev;
544 struct pinctrl_gpio_range *range;
545 acpi_handle handle = ACPI_HANDLE(dev);
548 if (acpi_bus_get_device(handle, &acpi_dev))
551 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
553 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
557 for (range = byt_ranges; range->name; range++) {
558 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
559 vg->chip.ngpio = range->npins;
565 if (!vg->chip.ngpio || !vg->range)
569 platform_set_drvdata(pdev, vg);
571 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
573 if (IS_ERR(vg->reg_base))
574 return PTR_ERR(vg->reg_base);
576 spin_lock_init(&vg->lock);
579 gc->label = dev_name(&pdev->dev);
580 gc->owner = THIS_MODULE;
581 gc->request = byt_gpio_request;
582 gc->free = byt_gpio_free;
583 gc->direction_input = byt_gpio_direction_input;
584 gc->direction_output = byt_gpio_direction_output;
585 gc->get = byt_gpio_get;
586 gc->set = byt_gpio_set;
587 gc->dbg_show = byt_gpio_dbg_show;
589 gc->can_sleep = false;
592 #ifdef CONFIG_PM_SLEEP
593 vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio,
594 sizeof(*vg->saved_context), GFP_KERNEL);
597 ret = gpiochip_add(gc);
599 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
603 /* set up interrupts */
604 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
605 if (irq_rc && irq_rc->start) {
606 byt_gpio_irq_init_hw(vg);
607 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
608 handle_simple_irq, IRQ_TYPE_NONE);
610 dev_err(dev, "failed to add irqchip\n");
615 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
616 (unsigned)irq_rc->start,
617 byt_gpio_irq_handler);
620 pm_runtime_enable(dev);
625 #ifdef CONFIG_PM_SLEEP
626 static int byt_gpio_suspend(struct device *dev)
628 struct platform_device *pdev = to_platform_device(dev);
629 struct byt_gpio *vg = platform_get_drvdata(pdev);
632 for (i = 0; i < vg->chip.ngpio; i++) {
636 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
637 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
638 vg->saved_context[i].conf0 = value;
640 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
641 value = readl(reg) & BYT_VAL_RESTORE_MASK;
642 vg->saved_context[i].val = value;
648 static int byt_gpio_resume(struct device *dev)
650 struct platform_device *pdev = to_platform_device(dev);
651 struct byt_gpio *vg = platform_get_drvdata(pdev);
654 for (i = 0; i < vg->chip.ngpio; i++) {
658 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
660 if ((value & BYT_CONF0_RESTORE_MASK) !=
661 vg->saved_context[i].conf0) {
662 value &= ~BYT_CONF0_RESTORE_MASK;
663 value |= vg->saved_context[i].conf0;
665 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
668 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
670 if ((value & BYT_VAL_RESTORE_MASK) !=
671 vg->saved_context[i].val) {
674 v = value & ~BYT_VAL_RESTORE_MASK;
675 v |= vg->saved_context[i].val;
678 dev_dbg(dev, "restored pin %d val %#08x\n",
688 static int byt_gpio_runtime_suspend(struct device *dev)
693 static int byt_gpio_runtime_resume(struct device *dev)
698 static const struct dev_pm_ops byt_gpio_pm_ops = {
699 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
700 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
704 static const struct acpi_device_id byt_gpio_acpi_match[] = {
709 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
711 static int byt_gpio_remove(struct platform_device *pdev)
713 struct byt_gpio *vg = platform_get_drvdata(pdev);
715 pm_runtime_disable(&pdev->dev);
716 gpiochip_remove(&vg->chip);
721 static struct platform_driver byt_gpio_driver = {
722 .probe = byt_gpio_probe,
723 .remove = byt_gpio_remove,
726 .pm = &byt_gpio_pm_ops,
727 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
731 static int __init byt_gpio_init(void)
733 return platform_driver_register(&byt_gpio_driver);
735 subsys_initcall(byt_gpio_init);
737 static void __exit byt_gpio_exit(void)
739 platform_driver_unregister(&byt_gpio_driver);
741 module_exit(byt_gpio_exit);