drivers/phy/phy-rockchip-usb.c

   1 /*
   2  * Rockchip usb PHY driver
   3  *
   4  * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/regmap.h>
  31 #include <linux/mfd/syscon.h>
  32
  33 /*
  34  * The higher 16-bit of this register is used for write protection
  35  * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
  36  */
  37 #define SIDDQ_WRITE_ENA BIT(29)
  38 #define SIDDQ_ON                BIT(13)
  39 #define SIDDQ_OFF               (0 << 13)
  40
  41 #define USB2_PHY_WRITE_ENA      (0xffff << 16)
  42 #define USB2_PHY_SUSPEND        (0x5 << 0 | 0xd << 4 | 0x1 << 8)
  43 #define USB2_PHY_RESUME (0)
  44
  45 struct rockchip_usb_phys {
  46         int reg;
  47         const char *pll_name;
  48 };
  49
  50 struct rockchip_usb_phy_pdata {
  51         struct rockchip_usb_phys *phys;
  52         unsigned int phy_pw_on;
  53         unsigned int phy_pw_off;
  54         bool siddq_ctl;
  55 };
  56
  57 struct rockchip_usb_phy_base {
  58         struct device *dev;
  59         struct regmap *reg_base;
  60         const struct rockchip_usb_phy_pdata *pdata;
  61 };
  62
  63 struct rockchip_usb_phy {
  64         struct rockchip_usb_phy_base *base;
  65         struct device_node *np;
  66         unsigned int    reg_offset;
  67         struct clk      *clk;
  68         struct clk      *clk480m;
  69         struct clk_hw   clk480m_hw;
  70         struct phy      *phy;
  71 };
  72
  73 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
  74                                            bool off)
  75 {
  76         unsigned int val;
  77
  78         val = !off ? phy->base->pdata->phy_pw_on : phy->base->pdata->phy_pw_off;
  79         return regmap_write(phy->base->reg_base, phy->reg_offset, val);
  80 }
  81
  82 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
  83                                                 unsigned long parent_rate)
  84 {
  85         return 480000000;
  86 }
  87
  88 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
  89 {
  90         struct rockchip_usb_phy *phy = container_of(hw,
  91                                                     struct rockchip_usb_phy,
  92                                                     clk480m_hw);
  93
  94         /* Power down usb phy analog blocks by set siddq 1 */
  95         if (phy->base->pdata->siddq_ctl)
  96                 rockchip_usb_phy_power(phy, 1);
  97 }
  98
  99 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
 100 {
 101         int ret = 0;
 102         struct rockchip_usb_phy *phy = container_of(hw,
 103                                                     struct rockchip_usb_phy,
 104                                                     clk480m_hw);
 105
 106         /* Power up usb phy analog blocks by set siddq 0 */
 107         if (phy->base->pdata->siddq_ctl)
 108                 ret = rockchip_usb_phy_power(phy, 0);
 109
 110         return ret;
 111 }
 112
 113 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
 114 {
 115         struct rockchip_usb_phy *phy = container_of(hw,
 116                                                     struct rockchip_usb_phy,
 117                                                     clk480m_hw);
 118         int ret = 1;
 119         u32 val;
 120
 121         if (phy->base->pdata->siddq_ctl) {
 122                 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
 123                 if (ret < 0)
 124                         return ret;
 125
 126                 ret = (val & SIDDQ_ON) ? 0 : 1;
 127         }
 128
 129         return ret;
 130 }
 131
 132 static const struct clk_ops rockchip_usb_phy480m_ops = {
 133         .enable = rockchip_usb_phy480m_enable,
 134         .disable = rockchip_usb_phy480m_disable,
 135         .is_enabled = rockchip_usb_phy480m_is_enabled,
 136         .recalc_rate = rockchip_usb_phy480m_recalc_rate,
 137 };
 138
 139 static int rockchip_usb_phy_power_off(struct phy *_phy)
 140 {
 141         int ret = 0;
 142         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 143
 144         if (!phy->base->pdata->siddq_ctl) {
 145                 ret = rockchip_usb_phy_power(phy, 1);
 146                 if (ret)
 147                         return ret;
 148         }
 149
 150         clk_disable_unprepare(phy->clk480m);
 151         return 0;
 152 }
 153
 154 static int rockchip_usb_phy_power_on(struct phy *_phy)
 155 {
 156         int ret = 0;
 157         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 158
 159         ret = clk_prepare_enable(phy->clk480m);
 160         if (ret)
 161                 return ret;
 162
 163         if (!phy->base->pdata->siddq_ctl)
 164                 ret = rockchip_usb_phy_power(phy, 0);
 165
 166         return ret;
 167 }
 168
 169 static const struct phy_ops ops = {
 170         .power_on       = rockchip_usb_phy_power_on,
 171         .power_off      = rockchip_usb_phy_power_off,
 172         .owner          = THIS_MODULE,
 173 };
 174
 175 static void rockchip_usb_phy_action(void *data)
 176 {
 177         struct rockchip_usb_phy *rk_phy = data;
 178
 179         of_clk_del_provider(rk_phy->np);
 180         clk_unregister(rk_phy->clk480m);
 181
 182         if (rk_phy->clk)
 183                 clk_put(rk_phy->clk);
 184 }
 185
 186 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 187                                  struct device_node *child)
 188 {
 189         struct rockchip_usb_phy *rk_phy;
 190         unsigned int reg_offset;
 191         const char *clk_name;
 192         struct clk_init_data init;
 193         int err, i;
 194
 195         rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
 196         if (!rk_phy)
 197                 return -ENOMEM;
 198
 199         rk_phy->base = base;
 200         rk_phy->np = child;
 201
 202         if (of_property_read_u32(child, "reg", &reg_offset)) {
 203                 dev_err(base->dev, "missing reg property in node %s\n",
 204                         child->name);
 205                 return -EINVAL;
 206         }
 207
 208         rk_phy->reg_offset = reg_offset;
 209
 210         rk_phy->clk = of_clk_get_by_name(child, "phyclk");
 211         if (IS_ERR(rk_phy->clk))
 212                 rk_phy->clk = NULL;
 213
 214         i = 0;
 215         init.name = NULL;
 216         while (base->pdata->phys[i].reg) {
 217                 if (base->pdata->phys[i].reg == reg_offset) {
 218                         init.name = base->pdata->phys[i].pll_name;
 219                         break;
 220                 }
 221                 i++;
 222         }
 223
 224         if (!init.name) {
 225                 dev_err(base->dev, "phy data not found\n");
 226                 return -EINVAL;
 227         }
 228
 229         if (rk_phy->clk) {
 230                 clk_name = __clk_get_name(rk_phy->clk);
 231                 init.flags = 0;
 232                 init.parent_names = &clk_name;
 233                 init.num_parents = 1;
 234         } else {
 235                 init.flags = CLK_IS_ROOT;
 236                 init.parent_names = NULL;
 237                 init.num_parents = 0;
 238         }
 239
 240         init.ops = &rockchip_usb_phy480m_ops;
 241         rk_phy->clk480m_hw.init = &init;
 242
 243         rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
 244         if (IS_ERR(rk_phy->clk480m)) {
 245                 err = PTR_ERR(rk_phy->clk480m);
 246                 goto err_clk;
 247         }
 248
 249         err = of_clk_add_provider(child, of_clk_src_simple_get,
 250                                   rk_phy->clk480m);
 251         if (err < 0)
 252                 goto err_clk_prov;
 253
 254         err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
 255         if (err)
 256                 goto err_devm_action;
 257
 258         rk_phy->phy = devm_phy_create(base->dev, child, &ops);
 259         if (IS_ERR(rk_phy->phy)) {
 260                 dev_err(base->dev, "failed to create PHY\n");
 261                 return PTR_ERR(rk_phy->phy);
 262         }
 263         phy_set_drvdata(rk_phy->phy, rk_phy);
 264
 265         /* only power up usb phy when it use, so disable it when init*/
 266         return rockchip_usb_phy_power(rk_phy, 1);
 267
 268 err_devm_action:
 269         of_clk_del_provider(child);
 270 err_clk_prov:
 271         clk_unregister(rk_phy->clk480m);
 272 err_clk:
 273         if (rk_phy->clk)
 274                 clk_put(rk_phy->clk);
 275         return err;
 276 }
 277
 278 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
 279         .phys = (struct rockchip_usb_phys[]){
 280                 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
 281                 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
 282                 { /* sentinel */ }
 283         },
 284         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 285         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 286         .siddq_ctl  = true,
 287 };
 288
 289 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
 290         .phys = (struct rockchip_usb_phys[]){
 291                 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
 292                 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
 293                 { /* sentinel */ }
 294         },
 295         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 296         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 297         .siddq_ctl  = true,
 298 };
 299
 300 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
 301         .phys = (struct rockchip_usb_phys[]){
 302                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
 303                 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
 304                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
 305                 { /* sentinel */ }
 306         },
 307         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 308         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 309         .siddq_ctl  = true,
 310 };
 311
 312 static const struct rockchip_usb_phy_pdata rk336x_pdata = {
 313         .phys = (struct rockchip_usb_phys[]){
 314                 { .reg = 0x700, .pll_name = "sclk_otgphy0_480m" },
 315                 { .reg = 0x728, .pll_name = "sclk_otgphy1_480m" },
 316                 { /* sentinel */ }
 317         },
 318         .phy_pw_on  = USB2_PHY_WRITE_ENA | USB2_PHY_RESUME,
 319         .phy_pw_off = USB2_PHY_WRITE_ENA | USB2_PHY_SUSPEND,
 320         .siddq_ctl  = false,
 321 };
 322
 323 static int rockchip_usb_phy_probe(struct platform_device *pdev)
 324 {
 325         struct device *dev = &pdev->dev;
 326         struct rockchip_usb_phy_base *phy_base;
 327         struct phy_provider *phy_provider;
 328         const struct of_device_id *match;
 329         struct device_node *child;
 330         int err;
 331
 332         phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
 333         if (!phy_base)
 334                 return -ENOMEM;
 335
 336         match = of_match_device(dev->driver->of_match_table, dev);
 337         if (!match || !match->data) {
 338                 dev_err(dev, "missing phy data\n");
 339                 return -EINVAL;
 340         }
 341
 342         phy_base->pdata = match->data;
 343
 344         phy_base->dev = dev;
 345         phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
 346                                                              "rockchip,grf");
 347         if (IS_ERR(phy_base->reg_base)) {
 348                 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
 349                 return PTR_ERR(phy_base->reg_base);
 350         }
 351
 352         for_each_available_child_of_node(dev->of_node, child) {
 353                 err = rockchip_usb_phy_init(phy_base, child);
 354                 if (err) {
 355                         of_node_put(child);
 356                         return err;
 357                 }
 358         }
 359
 360         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 361         return PTR_ERR_OR_ZERO(phy_provider);
 362 }
 363
 364 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
 365         { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
 366         { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
 367         { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
 368         { .compatible = "rockchip,rk336x-usb-phy", .data = &rk336x_pdata },
 369         {}
 370 };
 371
 372 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
 373
 374 static struct platform_driver rockchip_usb_driver = {
 375         .probe          = rockchip_usb_phy_probe,
 376         .driver         = {
 377                 .name   = "rockchip-usb-phy",
 378                 .of_match_table = rockchip_usb_phy_dt_ids,
 379         },
 380 };
 381
 382 module_platform_driver(rockchip_usb_driver);
 383
 384 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 385 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 386 MODULE_LICENSE("GPL v2");